KR100191076B1 - Semiconductor package - Google Patents

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Publication number
KR100191076B1
KR100191076B1 KR1019950061438A KR19950061438A KR100191076B1 KR 100191076 B1 KR100191076 B1 KR 100191076B1 KR 1019950061438 A KR1019950061438 A KR 1019950061438A KR 19950061438 A KR19950061438 A KR 19950061438A KR 100191076 B1 KR100191076 B1 KR 100191076B1
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KR
South Korea
Prior art keywords
mask layer
solder mask
encapsulant
semiconductor package
forming
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KR1019950061438A
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Korean (ko)
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KR970053754A (en
Inventor
이무응
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김규현
아남반도체주식회사
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Priority to KR1019950061438A priority Critical patent/KR100191076B1/en
Publication of KR970053754A publication Critical patent/KR970053754A/en
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Publication of KR100191076B1 publication Critical patent/KR100191076B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 회로기판(PCB)상에 반도체칩(5)을 실장하고 실장부위를 봉지재(Liquid Encapsulant)로 충전하여서 이루어지는 반도체패키지에 대한 것으로, 본 발명에서는 봉지재의 넘쳐흐름을 방지하기 위하여 회로기판(PCB)의 chl상부에 별도의 댐(3)을 형성하지 않고 회로기판(PCB)에 2단계로 도핑되는 솔더마스크층(2) 중상층부 자체를 활용하여 거기에 여러 형상의 넘침방지수단을 부여함으로써 별도의 부재를 추가함이 없이 봉지재의 충전작업을 보다 용이하게 실시할 수 있는 효과를 제공하게 되는 것이다.The present invention relates to a semiconductor package formed by mounting a semiconductor chip (5) on a circuit board (PCB) and filling the mounting portion with a liquid encapsulant, and in the present invention, to prevent the overflow of the encapsulant. Instead of forming a separate dam 3 on the upper chl of the PCB, the upper portion of the solder mask layer 2 which is doped to the PCB in two stages is utilized to impart various types of overflow prevention measures thereto. By doing so it is to provide an effect that can be carried out the filling operation of the encapsulant more easily without adding a separate member.

Description

반도체패키지Semiconductor Package

본 발명은 회로기판상에 반도체칩을 실장하고 실장부위를 봉지재로 충전하여서 이루어지는 반도체패키지에 대한 것으로서, 특히 2단계로 형성되는 솔더 마스크층의 최상층부 구역을 선택적으로 형성함으로써 자체적으로 넘침방지수단이 구비되도록 하여 봉지재의 충전시 액상의 봉지재가 외부로 흘러넘쳐 번지는 것을 방지하도록 한 것이다.The present invention relates to a semiconductor package formed by mounting a semiconductor chip on a circuit board and filling the mounting portion with an encapsulant, and in particular, by selectively forming the uppermost region of the solder mask layer formed in two steps, It is to be provided so as to prevent the liquid encapsulant overflows to the outside during filling of the encapsulant.

일반적으로 봉지재(1; Liquid Encapsulant)를 충전하여 만들어지는 종래 반도체패키지의 경우는 제6도에 단면으로 예시한 바와 같이 상단의 솔더마스크층(2)위에 일정 높이의 댐(3 ; 봉지재의 점도를 높인 것)을 형성하여 봉지재(1)의 충전시 봉지재의 흘러 넘침을 방지토록 하는 구조를 취하고 있음이 보통이다.In general, in the case of a conventional semiconductor package made by filling an encapsulant (1; Liquid Encapsulant), as shown in the cross section in FIG. 6, a dam 3 having a predetermined height on the upper solder mask layer 2 (viscosity of the encapsulant) It is common to take a structure to prevent the overflow of the encapsulant during the filling of the encapsulant (1) to form.

그러나 상기와 같은 종래의 구조는 댐(3)을 형성할 별도의 재료가 필요하고 댐의 형성시 불량발생 및 회로기판의 단가상승을 수반하게 되는 것이다.However, the conventional structure as described above requires a separate material for forming the dam 3 and involves the occurrence of defects and an increase in the cost of the circuit board when the dam is formed.

이에 본 발명에서는 이러한 종래의 댐 형성 방식이 갖는 제반 문제점을 감안 하여 안출한 것으로서, 본 발명은 2단계로 도핑하는 상층부의 솔더마스크층 자체를 활용하여 거기에 여러 형상의 넘침 방지수단을 부여함으로써 별도의 부재를 추가 함이 없이 봉지재의 충전작업이 쉽게 이루어질 수 있도록 하는 데 그 목적이 있다.Accordingly, the present invention has been made in view of all the problems of the conventional dam formation method, and the present invention utilizes the solder mask layer itself of the upper layer to be doped in two stages, thereby providing overflow protection means having various shapes therein. The purpose is to make the filling operation of the encapsulant easily without adding a member of the.

제1도는 본 발명의 반도체패키지 구성 단면도.1 is a cross-sectional view of a semiconductor package configuration of the present invention.

제2도는 본 발명의 반도체패키지 평면 예시도.2 is a schematic view illustrating a semiconductor package of the present invention.

제3도 ∼ 제5도는 본 발명의 다른 실시예.3 to 5 show another embodiment of the present invention.

제6도는 종래 반도체패키지의 구성 단면도.6 is a cross-sectional view of a conventional semiconductor package.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 봉지재 2 : 솔더마스크층1 encapsulation material 2 solder mask layer

3 : 댐 4 : 요입부3: dam 4: recessed part

5 : 반도체칩 6 : 와이어5 semiconductor chip 6 wire

7a, 7b, 7c, 7d : (각 형태의) 넘침방지수단7a, 7b, 7c, 7d: overflow protection means of each type

PCB : 회로기판PCB: Circuit Board

상기한 목적을 이루기 위하여 본 발명은 솔더마스크층(2)이 2단계로 도핑되는 회로기판에 반도체칩(5)을 실장하고 실장부위를 봉지재(1)로 충전하여 구성되는 반도체패키지에 있어서, 충전되는 봉지재(1)가 넘쳐 흐로는 것을 막을 수 있도록 상기 솔더 마스크층(2)의 최상층부 형성시 선택적으로 영역을 선택하여 형성하는 넘침방지수단을 구비한 것을 특징으로 하는 반도체패키지를 제공한다.In order to achieve the above object, the present invention provides a semiconductor package comprising a semiconductor chip 5 mounted on a circuit board on which a solder mask layer 2 is doped in two stages, and a mounting portion is filled with an encapsulant 1, In order to prevent the filling encapsulant 1 from overflowing, the semiconductor package is provided with overflow prevention means for selectively selecting and forming a region when forming the uppermost layer of the solder mask layer 2.

이하 첨부된 비한정의 예시도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제1도∼도5는 본 발명에 의한 봉지재(1)의 넘침을 막아 주기 위한 넘침방지수단에 대하여 바람직한 실시예들을 예시한 것이다.1 to 5 illustrate preferred embodiments of the overflow preventing means for preventing the overflow of the encapsulant 1 according to the present invention.

본 발명의 반도체 패키지를 구성하는 회로기판(PCB)은 구리(Cu)의 적층판으로 구성되며 그 중앙의 요입부(4)에 반도체칩(5)을 부착하여 와이어(6)의 연결을 실시한 후, 반도체칩(5)이 실장된 부위에 충전물질인 액상의 봉지재(1)를 부어 충전하게 된다.The circuit board (PCB) constituting the semiconductor package of the present invention is composed of a laminated sheet of copper (Cu), and the semiconductor chip 5 is attached to the concave portion 4 in the center thereof, and then the wire 6 is connected thereto. The liquid encapsulant 1, which is a filling material, is poured into a portion where the semiconductor chip 5 is mounted to be filled.

이때 본 발명에서는 액상의 봉지재(1)가 흘러 넘치는 것을 방지하기 위하여2단계로 도핑되는 솔더마스크층(2)의 최상층부에 넘침방지수단을 구비함으로써 이를 해결하였다.In this case, in order to prevent the liquid encapsulant 1 from flowing out, the present invention solves this problem by providing an overflow preventing unit at the top layer of the solder mask layer 2 doped in two steps.

즉 제1도 및 제2도에 각각 단면도와 평면도로 예시한 바와 같이 솔더마스크층(2)의 최상층부 형성시 선택되는 소정 영역을 제외시킴으로써 사각홈을 이루도록 하여 봉지재(1)가 넘쳐흐르는 것을 방지하는 사각홈형상(7a)의 넘침방지수단을 구현한 것이다.That is, as shown in the first and second views, respectively, in the cross-sectional view and the plan view, the encapsulant 1 is prevented from overflowing by excluding a predetermined area selected when forming the uppermost part of the solder mask layer 2 to form a rectangular groove. To implement the overflow prevention means of the square groove shape (7a).

또한 다른 실시예로서는 제3도에 나타낸 바와 같이 솔더마스크층(2)의 최상층부 형성시 선택되는 소정영역만을 형성함으로써 평면에서 볼 때 사각상이고 단면으로 볼 때 돌출된 형상인 사각철형상(四角凸形狀 ; 7b)의 넘침방지수단을 형성하여 봉지재(1)가 넘쳐 흐르는 것을 방지할 수 있다.In another embodiment, as shown in FIG. 3, by forming only a predetermined region selected when forming the uppermost part of the solder mask layer 2, the rectangular iron shape is rectangular in plan view and protruded in cross section. The overflow preventing means of 7b) can be formed to prevent the encapsulant 1 from overflowing.

또한 또 다른 실시예로서 제4도에 나타낸 바와 같이 솔더마스크층(2)의 최상 층부 형성시 외부쪽만 형성하고 내측 일부분만을 제외시켜 수직 벽형상(7c)으로 형성한 넘침방지수단을 구비하여 봉지재(1)가 넘쳐 흐르는 것을 방지할 수 있다.As another embodiment, as shown in FIG. 4, when forming the uppermost layer of the solder mask layer 2, only the outer side is formed and the inner portion is excluded, and the bag is provided with overflow preventing means formed in the vertical wall shape 7c. The ash 1 can be prevented from overflowing.

또한 제5도에 예시한 바와 같이 솔더마스트층(2)의 최상층부 형성시 내측 일부를 제외시킨 벽형상(7c)으로 형성함과 동시에 이와 인접되게 외부쪽으로 예비홈형상(7d)을 더 형성하여 넘침방지수단을 2중으로 구비함으로써 만약에 흘러 넘칠지도 모르는 봉지재(1)를 더 이상 번지지 않도록 2중으로 구비한 넘침방지수단을 구비할 수도 있는 것이다.In addition, as illustrated in FIG. 5, the uppermost portion of the solder mast layer 2 is formed as a wall shape 7c excluding the inner part, and a preliminary groove shape 7d is further overflowed adjacent to the outside. By providing the prevention means in duplicate, it may be provided with the overflow prevention means provided in double so that the sealing material 1 which may overflow may no longer spread.

이상과 같이 본 발명에서는 회로기판(PCB)에 반도체칩(5)을 실장한 후 그 실장부위를 액상의 봉지재로 충전함에 있어서, 봉지재(1)의 흘러 넘침을 예방하기 위하여 별도의 댐을 형성하지 않고 회로기판(PCB)의 솔더마스크증 중 최상층부에 도핑되는 솔더마스크층을 선택적으로 영역을 선택하여 자체적으로 넘침방지수단이 구비되도록 함으로써 봉지재의 충전시 액상의 봉지재가 외부로 흘러넘쳐 번지는 것을 방지하는 효과가 있다.As described above, in the present invention, after mounting the semiconductor chip 5 on the circuit board (PCB) and filling the mounting portion with a liquid encapsulant, a separate dam is provided to prevent the encapsulant 1 from overflowing. When the filling of the encapsulant, the liquid encapsulant overflows to the outside by filling the encapsulant by selectively selecting a region of the solder mask layer doped at the uppermost layer of the solder mask of the PCB without forming it. It is effective to prevent that.

Claims (5)

솔더마스크층(2)이 2단계로 도핑되는 회로기판(PCB)에 반도체칩(5)을 실장하고 실장부위를 봉지재(1)로 충전하여 구성되는 반도체패키지에 있어서, 충전되는 봉지재(1)가 넘쳐 흐르는 것을 막을 수 있도록 상기 솔더마스크층(2)의 최상층부 형성시 선택적으로 영역을 선택하여 형성하는 넘침방지수단을 구비한 것을 특징으로 하는 반도체패키지.In a semiconductor package formed by mounting a semiconductor chip 5 on a circuit board (PCB) where the solder mask layer 2 is doped in two stages and filling the mounting portion with the encapsulant 1, the encapsulant 1 to be filled And an overflow prevention means for selectively selecting and forming a region when forming the uppermost layer of the solder mask layer (2) to prevent the overflow of the solder mask layer (2). 제1항에 있어서, 상기 넘침방지수단은 솔더마스크층(2)의 최상부 형성시 일부분을 사각홈형상(7a)으로 제외시켜 형성한 것을 특징으로 하는 반도체패키지.The semiconductor package according to claim 1, wherein the overflow preventing means is formed by excluding a portion of the solder mask layer (2a) into a rectangular groove shape (7a) when forming the uppermost portion of the solder mask layer (2). 제1항에 있어서, 상기 넘침방지수단은 최상층 솔더마스크층(2)의 일부분만을 사각철형상(7b)으로 형성한 것을 특징으로 하는 반도체패키지.The semiconductor package according to claim 1, wherein the overflow preventing means is formed by forming only a portion of the uppermost solder mask layer (2b) in a rectangular iron shape (7b). 제1항에 있어서, 상기 넘침방지수단은 솔더마스크층(2)의 최상층부 형성시 내측 일부분만을 제외시켜 수직 벽형상(7c)으로 형성한 것을 특징으로 하는 반도체패키지.The semiconductor package according to claim 1, wherein the overflow preventing means is formed in a vertical wall shape (7c) by excluding only an inner portion when forming the uppermost part of the solder mask layer (2). 제1항 또는 제4항에 있어서, 상기 넘침방지수단은 솔더마스크층(2)의 최상층부 형성시 내측 일부를 제외시킨 벽형상(7c)을 형성함과 동시에 이와 인접되게 외부쪽으로 형성한 예비홈형상(7d)을 더 포함하여 2중으로 구비된 것을 특징으로 하는 반도체 패키지.The preliminary groove shape according to claim 1 or 4, wherein the overflow preventing means forms a wall shape 7c excluding the inner part of the solder mask layer 2 while forming the uppermost part of the solder mask layer 2, and is formed outwardly adjacent thereto. The semiconductor package further comprises a double (7d).
KR1019950061438A 1995-12-28 1995-12-28 Semiconductor package KR100191076B1 (en)

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Publication number Priority date Publication date Assignee Title
KR20020069288A (en) * 2001-02-24 2002-08-30 삼성전자 주식회사 Semiconductor package using tape circuit board forming groove for preventing the encapsulant from overflowing and method for manufacturing thereof

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KR100370852B1 (en) * 1999-12-20 2003-02-05 앰코 테크놀로지 코리아 주식회사 semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020069288A (en) * 2001-02-24 2002-08-30 삼성전자 주식회사 Semiconductor package using tape circuit board forming groove for preventing the encapsulant from overflowing and method for manufacturing thereof

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