KR0186179B1 - Esd protection circuit - Google Patents
Esd protection circuit Download PDFInfo
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- KR0186179B1 KR0186179B1 KR1019950023581A KR19950023581A KR0186179B1 KR 0186179 B1 KR0186179 B1 KR 0186179B1 KR 1019950023581 A KR1019950023581 A KR 1019950023581A KR 19950023581 A KR19950023581 A KR 19950023581A KR 0186179 B1 KR0186179 B1 KR 0186179B1
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- 239000012535 impurity Substances 0.000 claims description 32
- 238000009792 diffusion process Methods 0.000 claims description 30
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 8
- 238000002955 isolation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
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- 230000006378 damage Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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Abstract
본 발명은 ESD(Electro Static Discharge) 보호회로에 관한 것으로, 특히 디램(DRAM)에서 P웰에 주입된 전하의 방전을 용이하게 하여 입력 ESD(Electro Static Discharge) 보호회로의 성능을 향상시키기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to facilitate discharge of charge injected into a P well in a DRAM, thereby improving performance of an input electrostatic discharge (ESD) protection circuit.
이와 같은 본 발명의 ESD(Electro Static Discharge) 보호회로는 내부회로의 입력패드와 정전압원(Vcc) 사이에 제1트랜지스터(Q1)가 연결되고, 상기 입력패드와 접지단(Vss) 사이에 제2트랜지스터(Q2)가 연결되고, 상기 제1, 제2 트랜지스터의 베이스는 제3트랜지스터(Q3)를 통해 접지단(Vss)에 연결되고, 상기 제3트랜지스터(Q3)의 게이트는 정전압원(Vcc)에 인가되도록 구성됨을 특징으로 한 것이다.In the electrostatic discharge (ESD) protection circuit of the present invention, the first transistor Q 1 is connected between the input pad of the internal circuit and the constant voltage source Vcc, and is provided between the input pad and the ground terminal Vss. 2, and the transistor (Q 2) connected to the first base of the second transistor is coupled to the third transistor ground terminal (Vss) through (Q 3), the gate of the third transistor (Q 3) is a constant-voltage It is characterized in that configured to be applied to the circle (Vcc).
Description
제1도는 종래의 ESD 보호회로의 구조단면도.1 is a structural cross-sectional view of a conventional ESD protection circuit.
제2도는 종래의 ESD 보호회로의 등가회로도.2 is an equivalent circuit diagram of a conventional ESD protection circuit.
제3도는 본 발명의 ESD 보호회로의 구조단면도.3 is a structural cross-sectional view of the ESD protection circuit of the present invention.
제4도는 본 발명의 ESD 보호회로의 등가회로도.4 is an equivalent circuit diagram of an ESD protection circuit of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : P형 웰21 semiconductor substrate 22 P-type well
23 : n형 웰 24 : 게이트 전극23 n-type well 24 gate electrode
25 : 필드산화막 25a : 격리산화막25: field oxide film 25a: isolated oxide film
26, 27, 28, 29 : 고농도 n형 불순물 확산영역26, 27, 28, 29: high concentration n-type impurity diffusion region
30, 31 : 고농도 P형 불순물 확산영역 32 : 금속패턴30, 31: high concentration P-type impurity diffusion region 32: metal pattern
본 발명은 ESD(Electro Static Discharge) 보호회로에 관한 것으로, 특히 디램(DRAM)에서 P웰에 주입된 전하의 방전을 용이하게 한 입력 ESD 보호회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to an input ESD protection circuit that facilitates the discharge of charge injected into a P well in a DRAM.
일반적으로, ESD 보호회로는 ESD에 의한 디바이스의 파괴를 줄이기 위해 디바이스(Device) 주위의 ESD 발생원인을 제거하는 방법과, 디바이스(Device)에 인가되는 ESD를 적절한 보호회로를 사용하여 내부회로에 영향을 주지 않고 방전시키는 방법이 있다.In general, an ESD protection circuit is a method of eliminating the cause of ESD occurrence around the device to reduce the destruction of the device by the ESD, and the ESD applied to the device to the internal circuit using the appropriate protection circuit There is a method of discharging without giving.
이하, 첨부도면을 참조하여 종래의 ESD 보호회로를 설명하면 다음과 같다.Hereinafter, a conventional ESD protection circuit will be described with reference to the accompanying drawings.
제1도는 종래의 ESD 보호회로의 구조를 나타낸 단면도이고, 제2도는 종래의 ESD 보호회로의 등가회로이다.1 is a cross-sectional view showing the structure of a conventional ESD protection circuit, and FIG. 2 is an equivalent circuit of a conventional ESD protection circuit.
먼저 제1도와 같이, n형 반도체 기판(1)상에 형성된 P웰(2)상에 필드영역과 활성영역을 정의하여 필드영역에 필드산화막(3)이 형성되고, 활성영역내에는 불순물 확산영역을 격리시키기 위한 복수개의 격리산화막(3a)이 형성된다.First, as shown in FIG. 1, the field oxide film 3 is formed in the field region by defining a field region and an active region on the P well 2 formed on the n-type semiconductor substrate 1, and the impurity diffusion region in the active region. A plurality of isolation oxide films 3a are formed for isolating them.
그리고, 격리산화막(3a) 사이 사이의 P형 웰(2)상에 고농도 n+불순물 확산영역(4)이 형성되어 npn형 바이폴라 트랜지스터 구조가 형성한다.Then, a high concentration n + impurity diffusion region 4 is formed on the P type well 2 between the isolation oxide films 3a to form an npn type bipolar transistor structure.
상기 각각의 고농도 n+불순물 확산영역(4)에는 전기적 연결을 위한 금속패턴(5)이 형성된다.In each of the high concentration n + impurity diffusion regions 4, a metal pattern 5 for electrical connection is formed.
상기와 같이 구성된 종래의 ESD(Electro Static Discharge) 보호회로의 동작을 설명하면 다음과 같다.Referring to the operation of the conventional electrostatic discharge (ESD) protection circuit configured as described above is as follows.
제1도에서와 같이 입력패트(PAD)에 양(+) 전하가 인가되면 상기 입력패드에 연결된 고농도 n+불순물 확산영역과 P웰간의 접합부의 디플리션 폭(Depletion Width)이 점차 증가하여 결국 인접한 Vcc나 Vss에 연결된 고농도 n+영역과 맞닿게 되는 펀치스로우(Punch Through)가 발생되며, 상기 펀치스로우 현상에 의해 Vcc나 Vss로 전하가 방전된다.As shown in FIG. 1, when a positive charge is applied to the input pad PAD, the depletion width of the junction between the high concentration n + impurity diffusion region and the P well connected to the input pad gradually increases and eventually occurs. Punch through is brought into contact with the high concentration n + region connected to adjacent Vcc or Vss, and the charge is discharged to Vcc or Vss by the punch throw phenomenon.
도한 입력패드에 부(-)전하가 인가되면 상기 입력패드에 연결된 고농도 n+불순물 확산영역과 P웰의 접합부가 순방향이 되어 P웰의 전압이 강하되고 Vcc나 Vss에 연결된 고농도 n+영역과 P웰과의 접합부에 브레이크 다운(Breakdown)이 발생되어 제2도의 종래의 ESD(Electro Static Discharge) 보호회로의 등가회로도에 나타낸 바와 같이 Q1과 Q2가 동작하여 입력전하를 방전한다.In addition, when negative charge is applied to the input pad, the high concentration n + impurity diffusion region connected to the input pad and the junction of the P well are forward, so that the voltage of the P well drops and the high concentration n + region and P connected to Vcc or Vss. Breakdown occurs at the junction with the well, and Q 1 and Q 2 operate to discharge the input charge as shown in the equivalent circuit diagram of the conventional electrostatic discharge (ESD) protection circuit of FIG.
그러나, 상기와 같은 종래의 ESD(Electro Static Discharge) 보호회로는 입력패드에 부(-)전압을 인가하면 입력패드에 연결된 고농도 n+불순물 확산영역과 P웰간의 접합부가 순 바이어스가 되고, 상기 P 웰과 Vcc나 Vss에 연결된 고농도 n+불순물 확산영역의 접합부에는 역 바이어스가 인가되므로 P 웰의 포텐셜(Potential)은 강하되어, 결국 P 웰과 n+정션 브레이크 다운(Breakdown)이 발생하고 상기 브레이크 다운(Breakdown)에 의해 전하가 방전하게 되지만, 상기 브레이크 다운(Breakdown)이 일어나기 이전에는 전하가 방전되지 못하므로 브레이크 다운이 일어나기 이전에 입력된 전하에 의해 내부회로가 파괴될 수 있는 문제점이 있었다.However, in the conventional electrostatic discharge (ESD) protection circuit, when a negative voltage is applied to an input pad, a junction between the high concentration n + impurity diffusion region connected to the input pad and the P well becomes a net bias, and the P Since the reverse bias is applied to the junction of the well and the high concentration n + impurity diffusion region connected to Vcc or Vss, the potential of the P well is lowered, resulting in P well and n + junction breakdown and the breakdown. The charge is discharged by the breakdown, but since the charge is not discharged before the breakdown occurs, the internal circuit may be destroyed by the input charge before the breakdown occurs.
본 발명은 상술한 종래의 ESD(Electro Static Discharge) 보호회로의 문제점을 해결하기 위해 안출한 것으로, P웰과 Vss 사이에 P 채널 모오스 트랜지스터를 형성하여 ESD(Electro Static Discharge) 보호회로의 기능을 향상시키는데 그 목적이 있다.The present invention has been made to solve the problems of the conventional electrostatic discharge (ESD) protection circuit described above, and forms a P-channel MOS transistor between the P well and Vss to improve the function of the electrostatic discharge (ESD) protection circuit. The purpose is to.
상기 목적을 달성하기 위한 본 발명의 ESD(Electro Static Discharge) 보호회로는 내부회로의 입력패드와 정전압원(Vcc) 사이에 제1트랜지스터(Q1)가 연결되고, 상기 입력패드와 접지단(Vss) 사이에 제2트랜지스터(Q2)가 연결되고, 상기 제1, 제2트랜지스터의 베이스는 제3트랜지스터(Q3)를 통해 접지단(Vcc)에 연결되고, 상기 제3트랜지스터(Q3)의 게이트는 정전압원(Vcc)에 연결되고, 상기 제3트랜지스터(Q3)의 게이트는 정전압원(Vcc)에 인가되도록 구성됨을 특징을 한다.Electrostatic discharge (ESD) protection circuit of the present invention for achieving the above object is a first transistor (Q 1 ) is connected between the input pad and the constant voltage source (Vcc) of the internal circuit, the input pad and the ground terminal (Vss) ), and the second transistor (Q 2) connected between the first, and the base of the second transistor is coupled to a third transistor (ground terminal (Vcc) through Q 3), the third transistor (Q 3) The gate of is connected to the constant voltage source (Vcc), the gate of the third transistor (Q 3 ) is characterized in that configured to be applied to the constant voltage source (Vcc).
이하, 첨부도면을 참조하여 본 발명의 ESD(Electro Static Discharge) 보호회로를 설명하면 다음과 같다.Hereinafter, an electrostatic discharge (ESD) protection circuit of the present invention will be described with reference to the accompanying drawings.
제3도는 본 발명의 ESD(Electro Static Discharge) 보호회로의 구조단면도이고, 제4도는 본 발명에 따른 ESD(Electro Static Discharge) 보호회로의 등가회로도이다.3 is a structural cross-sectional view of an electrostatic discharge (ESD) protection circuit of the present invention, and FIG. 4 is an equivalent circuit diagram of an electrostatic discharge (ESD) protection circuit according to the present invention.
본 발명의 ESD 보호회로는 제4도와 같이, 내부회로의 입력패드와 정전압원(Vcc) 및 접지단(Vss) 사이에 각각 제1트랜지스터(Q1)와 제2트랜지스터(Q2)가 연결되고, 상기 제1,제2트랜지스터(Q1)(Q2)의 베이스단은 공통으로 MOS 트랜지스터(Q3)의 소오스단에 연결되며, 상기 MOS 트랜지스터(Q3)의 게이트에는 정전압원(Vcc)이 인가되고, 드레인단은 접지되도록 구성되어 ESD를 보호하도록 되어 있다.In the ESD protection circuit of the present invention, as shown in FIG. 4, a first transistor Q 1 and a second transistor Q 2 are connected between an input pad of an internal circuit, a constant voltage source Vcc, and a ground terminal Vss, respectively. , the first and second base of the transistor (Q 1) (Q 2) is commonly connected to the source terminal of the MOS transistor (Q 3), has a constant voltage source (Vcc) the gate of the MOS transistor (Q 3) Is applied, and the drain terminal is configured to be grounded to protect the ESD.
이와 같은 ESD 보호회로의 반도체적 구성은 제3도와 같다.The semiconductor configuration of such an ESD protection circuit is shown in FIG.
즉, 제3도에서와 같이 n형 반도체 기판(21)상에 P형 제1웰(22)이 형성되고, 상기 P형 제1웰(22) 영역내의소정부분에 n형 제2웰(23)이 형성한다.That is, as shown in FIG. 3, the P-type first well 22 is formed on the n-type semiconductor substrate 21, and the n-type second well 23 is formed in a predetermined portion in the region of the P-type first well 22. ) Forms.
상기 P형 제1웰(22)과 n형 제2웰(23) 영역상의 필드영역과 활성영역이 정의되고 활성영역 중에도 격리영역이 정의되어 상기 필드영역에 필드산화막(25)이 형성되고, 격리영역에 격리산화막(25a)이 형성된다.A field region and an active region on the P-type first well 22 and the n-type second well 23 are defined, and an isolation region is defined among the active regions, and a field oxide film 25 is formed in the field region. An isolation oxide film 25a is formed in the region.
n형 제2웰(23)상의 일측에 게이트 전극(24)이 형성되고, 상기 게이트 전극(24) 양측의 n형 제2웰(23)영역에 고농도 P형 불순물을 확산영역(30)(31)이 형성된다.A gate electrode 24 is formed on one side of the n-type second well 23, and high concentration P-type impurities are diffused into the n-type second well 23 region on both sides of the gate electrode 24. ) Is formed.
n형 제2웰(23)상의 타측과, p형 제1웰(22)상의 각 격리산화막(25a) 사이에 고농도 n형 불순물 확산영역(26)(27)(28)(29)이 형성된다.High concentration n-type impurity diffusion regions 26, 27, 28, and 29 are formed between the other side of the n-type second well 23 and each of the isolation oxide films 25a on the p-type first well 22. .
그리고, 상기와 같이 형성된 기판(21)의 고농도 n형 불순물 확산영역((26)(27)(28)(29) 및 고농도 P형 불순물 확산영역(30)(31)에는 전기적으로 연결하기 위한 금속패드(32)가 형성된다.In addition, the metal for electrically connecting to the high concentration n-type impurity diffusion regions (26, 27) 28 and 29 and the high concentration P-type impurity diffusion regions 30 and 31 of the substrate 21 formed as described above. Pad 32 is formed.
여기서, 고농도 n형 불순물 확산영역(26)(29)과 게이트 전극(24)에는 정전압원(Vcc)이 인가되고, 고농도 n형 불순물 확산영역(27)에는 보호받고자 하는 내부회로의 입력단이 연결되며, 고농도 n형 불순물 확산영역(29)과, 고농도 P형 불순물 확산영역(30)에는 접지전압(Vss)이 인가된다.Here, a constant voltage source Vcc is applied to the high concentration n-type impurity diffusion regions 26 and 29 and the gate electrode 24, and an input terminal of an internal circuit to be protected is connected to the high concentration n-type impurity diffusion region 27. The ground voltage Vss is applied to the high concentration n-type impurity diffusion region 29 and the high concentration P-type impurity diffusion region 30.
상기와 같이 구성된 본 발명의 ESD(Electro Static Discharge) 보호회로의 동작을 설명하면 다음과 같다.Referring to the operation of the electrostatic discharge (ESD) protection circuit of the present invention configured as described above are as follows.
먼저 제3도 및 제4도에서 입력패드(PAD)에 정(+) 전하의 정전기가 인가되면 P웰 제1웰과 상기 입력패드에 접촉된 고농도 n형 불순물 확산영역(27) 접합부의 디플리션 폭(Depletion Width)이 점차 증가하여 인접한 Vcc나 Vss에 접촉된 고농도 n형 불순물 영역(26)(28)과 맞닿게 되어 펀치스로우(Punch Through) 현상이 일어나고, 상기 펀치스로우(Punch Through)현상에 의해 Vcc와 Vss로 전하가 방전하게 된다.First, in FIG. 3 and FIG. 4, when positive static electricity is applied to the input pad PAD, the dip well of the junction of the high concentration n-type impurity diffusion region 27 in contact with the first well of the P well and the input pad is shown. Deption width gradually increases to contact high-concentration n-type impurity regions 26 and 28 in contact with adjacent Vcc or Vss, resulting in a punch through phenomenon, and a punch through phenomenon. The charges are discharged to Vcc and Vss.
이어서, 입력패드(PAD)에 부(-) 전하에 정전기가 인가되면 상기 입력패드(PAD)에 연결된 고농도 n형 불순물 확장영역(27)과 P형 제1웰(22)이 순방향이 되어 전하가 P형 제1웰(22)로 흐르게 된다.Subsequently, when static electricity is applied to the negative charge to the input pad PAD, the high concentration n-type impurity extension region 27 and the P-type first well 22 connected to the input pad PAD are in a forward direction, so that charge is transferred. It flows into the P-type first well 22.
그 결과 P형 제1웰(22)의 포텬셜(Potential)은 (-)로 강하하게 된다.As a result, the potential of the P-type first well 22 drops to negative (-).
이때, P채널 모오스 트랜지스터의 게이트 전극(24)에 인가된 하이(High)전압에 의해 상기 트랜지스터는 오프(OFF)상태가 유지되지만, P형 제1웰(22)에 인가된 전압에 의해 고농도 P형 불순물 확산영역(31) 접합부의 디플리션 영역이 점차 증가되어 결국 고농도 P형 불순물 확산영역(30)과 맞닿게 되는 펀치스로우(Punch Through)가 발생하게 되어 입력패드에 인가된 전하를 P채널 모오스 트랜지스터의 Vss로 방전하게 된다.At this time, the transistor is maintained in an OFF state due to the high voltage applied to the gate electrode 24 of the P-channel MOS transistor, but the concentration P is high due to the voltage applied to the P-type first well 22. The depletion region of the junction of the type impurity diffusion region 31 gradually increases, resulting in a punch through contacting the high concentration P-type impurity diffusion region 30, thereby transferring the charge applied to the input pad to the P channel. It discharges to Vss of a MOS transistor.
결과적으로, P채널 모오스 트랜지스터의 소오스 전압의 증가에 의해 디플리션 영역폭이 증가되어 드레인 영역과 맞닿게 되는 BVDss 전압은 P웰과 n+접합의 브레이크 다운(Breakdown) 전압보다 낮기 때문에 상기 브레이크 다운(Breakdown)이 발생하기 전에, BVDss에 의한 펀치스로우(Punch Through)에 의해 입력전하를 Vss로 방전하게 된다.As a result, the BVDss voltage, which is in contact with the drain region by increasing the depletion region width due to the increase of the source voltage of the P-channel Morse transistor, is lower than the breakdown voltage of the P well and n + junction. Before (Breakdown) occurs, the input charge is discharged to Vss by punch through by BVDss.
이상 상술한 바와 같이 본 발명의 ESD(Electro Static Discharge) 보호회로는 P웰과 Vss 사이에 P채널 모오스 트랜지스터를 추가하여 입력전하에 의해 내부회로가 파괴되는 것을 방지하여 ESD(Electro Static Discharge) 보호회로의 성능을 향상시키는 효과가 있다.As described above, the electrostatic discharge (ESD) protection circuit of the present invention adds a P-channel MOS transistor between the P well and Vss to prevent the internal circuit from being destroyed by the input charge, thereby preventing the ESD (Electro Static Discharge) protection circuit. Has the effect of improving performance.
Claims (3)
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| KR1019950023581A KR0186179B1 (en) | 1995-07-31 | 1995-07-31 | Esd protection circuit |
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| KR1019950023581A KR0186179B1 (en) | 1995-07-31 | 1995-07-31 | Esd protection circuit |
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