KR0185978B1 - Electrically-programmable semiconductor memories with buried injector region - Google Patents

Abstract

The memory cell of the electrically erasable semiconductor memory has field effect transistors 5, 611, 12 having charge accumulation regions 11. Efficient and rapid injection of hot carriers 18 into the charge accumulation region 11 is implanted buried by application of programming voltages Vb and Vd to the surface of the control gate 12 and the punch draw region 2. This is achieved by punch draw in the vertical direction of the depletion layer 1 'to the region 2. The non-injected carrier 19 is removed through at least the transistor drain 6 between programmings. A clear punch draw region 1 can be obtained by a higher doping concentration boundary region 3 on at least one side of the punch draw region 1, thereby limiting the transverse direction of the depletion layer in the transverse direction and causing parasitics. Bonding is prevented. As a result, the implant region may be located closer to another region of the memory cell, for example, the regions of the source 5 and the drain 6, and the implant region 2 may be adjacent to the buried insulating field pattern 29. The compact cell array layout may be formed by a common coupling region 8 for the implant region 2 of two adjacent cells and the source 5 or drain 6 region of four other adjacent cells. The control gate 12 and the erase gate 14 can be equally coupled to the charge accumulation region 11, and each cell can be operated by complementary voltage levels during writing and erasing. The feedback mechanism at the start of injection from the punch draw region 1 and the injection region 2 can limit the clear charge level for erasing.

Description

Electrically programmable semiconductor memory

1 is a schematic cross-sectional view of a portion of a memory cell of a semiconductor memory according to the present invention.

2 is a cross-sectional view of a specific memory cell structure according to the present invention (direction perpendicular to the cross-sectional view of FIG. 1).

3 through 5 are plan views showing various regions of the structure of FIG. 2 of two adjacent memory cells.

FIG. 6 is a plan view showing an area of a plurality of memory cells having a structure similar to the memory cells of FIGS.

FIG. 7 is a cross-sectional view of another specific memory cell structure according to the present invention, illustrating a modification of the structure shown in FIG.

8 through 10 are cross-sectional views (directions perpendicular to the cross-sectional views of Figs. 2 and 7) illustrating other modifications in the memory cell according to the present invention.

* Explanation of symbols for main parts of the drawings

1: first area 2: injection area

5: source region 6: drain region

11 charge charge region 12 control gate

14 erase gate 21 first insulating layer

22: second insulating layer

The present invention relates to an electrically programmable semiconductor memory having a plurality of memory cells, each memory cell having a charge accumulation region (e.g., a floating gate), wherein the charge state of that region defines the memory state of the memory cell. will be. These memories can be, for example, EEPROM (electrically erasable and programmable read only memory) or very simple EPROM (electrically programmable read only memory) types.

British Patent Application No. GB-A-1 425 985 (PHN 6347) describes that each cell has a field effect transistor, and that the charge state of the charge accumulation region is electrically provided with a plurality of memory cells defining the memory state of the memory cell. Programmable semiconductor memory is described. This well-known semiconductor device has a semiconductor body in which each cell has a first insulating layer portion on a main surface of the main body on a first region of a semiconductor body of a first conductivity type, and the charge accumulation region is a portion of the first insulating layer portion. It is serialized on the surface. Each cell consisting of a second conductive type implantation region of a conductivity type opposite to the conductive type forming a pn junction with the first region has program means, and a control gate is capacitively coupled with the charge accumulation region. .

Various forms of EPROM are known to use an injection memory in which charge carriers (and especially hot electrons) are injected into the first insulating layer portion to set the charge state of the charge accumulation region. In recently used EPROM designs, hot electrons are caused to cause avalanche breakdown to the drain or source of an MOS (insulated gate field effect) transistor with a floating gate, or a sufficiently high electric field is applied to the transistor. By generating the hot electrons in the channel. However, in these cases, since electrons are generally accelerated in a direction parallel to the surface of the body, it is necessary to direct them to the surface in order to achieve effective injection into the charge accumulation region. Moreover, the doping profile of the source and / or drain is adjusted to produce sufficient hot electrons at a suitable voltage level, thereby providing for the memory cell as compared to the desired fabrication process in other parts of the integrated circuit device. Other MOS transistor process technologies must be used. During programming, if hot electrons are used in the channel portion of the memory transistor, for this purpose any one of the source and drain geometry and doping characteristics can be utilized in different ways and the read and write voltages may be Applied to the terminal. Programming at low voltages requires channel lengths shorter than these conventional desired channel lengths. Alternatively, the memory cell consists of two transistors, the first transistor of which is used between reads and the second transistor of which is used between writes. These two transistor arrays can occupy a large space in the memory cell.

As another form of injector, it is also known that hot electrons are generated by biasing the diode in the forward direction. This diode may be inserted under the memory transistor, for example, as described in British Patent No. 425 985 described above. This form has several advantages, including that other transistors in the circuit and the memory transistor can use the same transistor fabrication process. However, it is necessary to generate a negative diode voltage in the circuit, which can also disperse large substrate currents because it injects electrons in all directions (including directions into the substrate).

According to the present invention, an electrically programmable semiconductor memory comprising a plurality of memory cells, each memory cell having a field effect transistor having a charge accumulation region having a charge accumulation region defining a memory state of each of the cells The memory includes a semiconductor body having a first insulating layer portion for each cell on the surface of the main body on the first region of the first conductive type body, the charge accumulation region extending on the surface of the first insulating layer portion; And electrical programming means for each cell consisting of an implanted region of a second conductivity type of opposite conductivity type forming a pn junction with said first conductive region, and a control gate capacitively coupled to said charge accumulation region. The semiconductor memory programmable as in claim 1, wherein the injection region is a first region below the charge accumulation region. Positioned in the body so as to lie down, the cell for biasing a surface of the first region with respect to the control gate and the injection region in at least one drain, the control gate and the injection region of the transistor of each cell; Coupling means for applying a program voltage every time is provided such that a desired charge state of the charge accumulation region of the cell is established by injection of hot charge carriers through the first insulating layer portion in a vertical direction from the injection region, One region is sufficiently of the first conductivity type on the injection region to punch-through to the injection region through a depletion layer in a vertical direction crossing the thickness direction of the first region in accordance with the application of the program voltage. Hot charge carriers that have a low doping concentration and that are not injected into the first insulating layer portion By programming the coupling means while the cell is characterized in that the removal of the drain of the cell transistor.

In this aspect, a desired charge state of the charge accumulation region is obtained by hot carrier injection in the vertical direction from the injection region to the charge accumulation region. The same fabrication technique can be used for the memory cell as with other circuit parts, and a bias voltage supply of opposite polarity is not all required for the implant region. An effective programming mechanism is used to enable higher speed programming or to allow programming of lower value currents. In addition, as a result of this effective programming mechanism, it is possible to trap less charge in the insulating layer, so that more erasing and writing can be performed before serious degradation of the insulating layer occurs. .

It is noted that Japanese Patent Application Laid-Open No. 63-172471 describes a semiconductor memory using a punch draw of depletion to the buried region from below the floating gate charge accumulation region on the insulating layer. The desired one memory state of one or more cells in this memory is a separate charge state (i.e. floating potential), which is applied to the surface of the semiconductor body by applying a low program voltage to the control gate above the selected cell. It is written first, and then the memory state becomes nonvolatile by applying a high voltage to the control gates of all the cells. Depletion layer punch draw and implantation of hot carriers into the charge accumulation region occurs only in cells in the discrete charge state of 1 which are temporarily written to the semiconductor surface. As will be seen later, it can be seen that the employment of the arrangement described in Japanese Patent Application Laid-Open No. 63-172471 does not provide an effective injection of hot carriers into the charge accumulation region. Therefore, uninjected carriers are accumulated on the surface without being removed between programming, so that the isolated surface potential (determined by the temporarily written volatile charge-state of the surface) decreases in size between the programming and In fact, these two elements seem to cause an immediate stop of the injection. The punch-draw memory arrangement of US Pat. No. 63-172471 omits the transistor coupling means according to the present invention to bias the surface of the first region and eliminate non-injected charge carriers between programmings.

The present invention is directed to a vertical draw from the injection region to the bias surface (and to the portion of the insulating layer having the charge accumulation region) by means of a supported vertical punch draw of a depletion in the downward direction of the charge accumulation region. Already have the optimal direction to be injected effectively, while the non-injected carrier is removed from the bias surface to at least the drain of the transistor according to the invention via coupling means. In this aspect, locally effective implantation can be maintained between programming processes. By applying the special arrangement according to the present invention, the desired injection region can be confined below a part of the charge accumulation region by the punch draw in the vertical direction, and the compact (in spite of the injection region drain coupling) compact device structure can be achieved.

According to one aspect of the invention, there is provided a semiconductor memory that is electrically programmable such that the transverse expansion of the depletion layer during the vertical punch draw into the implantation region is defined by the boundary region. By reducing the influence of the cross-depletion layer in relation to other components of the memory cell, it is possible to facilitate the storage of the injector in a compact cell structure. This boundary region may constitute a buried insulating layer pattern. Fortunately, however, in the semiconductor memory device according to the present invention, at least one boundary region 3 has a higher doping concentration than the first conductive type present in at least one side of the low-doped first region 1 of each cell. And a semiconducting zone having a cross-sectional area and defining a transverse expansion of the depletion layer on the side during a punch draw crossing the thickness of the first region of low doping concentration in the longitudinal direction.

For example, in a compact cell structure, at least one boundary region of high doping concentration may be formed in the injection region and the source and drain to prevent punch draw coupling by either depletion layer of either source or drain of the transistor of the injection region. Between either side of the region can be provided according to the invention. The boundary region may be one or more boundaries that may separate the transistor region laterally from the punch draw first region on the injection region, or may separate one of the source and drain of the transistor from the channel region, for example. It can be formed in an area. The boundary area according to the invention can also be used to prevent parasitic coupling of the surface and the injection area, or for example adjacent to the buried field insulating layer pattern at the peripheral part of the injection area or the island part of the memory cell. Traverse

According to another aspect of the invention, an implantable region of one cell provides an electrically programmable semiconductor memory having a junction region of a second conductivity type that forms a common bond of other regions of adjacent memory cells (e.g., six). do. The compact memory array structure may have only a small number of combinations per cell, for example, only in two contact windows shared by each cell. Each such memory cell has an island portion of the body and the device further comprises two adjacent adjacent contiguous regions of the second conductive type that form a common bond to the implant regions of the two adjacent cells. The island portion of the cell is adjacent. This coupling region may be extended to four other adjacent island portions (in addition to the two adjacent island portions) to form the source or drain coupling of each transistor of the four island portions.

According to another aspect of the invention, each memory cell has an erase gate coupled to the charge accumulation region (eg, by being on a second insulating layer on the charge accumulation region), and an erase voltage is applied to the erase gate. The application allows electrical erasing of the memory state of the cell. Such a structure having both the erase gate and the control gate coupled to the charge accumulation region (e.g., through the second insulating layer) allows a bias loop to prevent over erasure by forming a feedback loop using hot carrier injection. Can be. Therefore, for approaching an over erase of the charge accumulation region, it is compensated by the start of hot-carrier injection through the punch-draw region in the vertical direction from the injection region in the downward direction of the charge accumulation region.

Therefore, according to another aspect of the present invention, each cell includes a plurality of memory cells each having a charge accumulation region in which the charge state of the charge accumulation region defines the memory state of the cell, and a first region below the charge accumulation region. An electrically programmable semiconductor memory having programming means for each cell comprising an implant region forming a pn junction, and a control gate capacitively coupled with the charge accumulation region, wherein the control gate and the implant region Applying a programming voltage to bias the surface of the first region relative to the injection region to establish a desired charge state of the charge accumulation region by a punch draw through a depletion layer across the thickness direction of the first region of Means, thereby permitting the injection region into the charge accumulation region. The desired programmed charge state is established by hot carrier injection from the memory, and the memory is also erased in which each memory cell is coupled to the charge accumulation region by less capacitance coupling than that of the charge accumulation means and the control gate. A gate and an erase gate that enables electrical erasing of the programmed charge state of the cell when biasing the control gate with a low voltage and biasing the surfaces of the first region and the implantation region with a programming voltage. And means for applying a low erase voltage, thereby enabling hot carrier injection from the injection region to the charge accumulation region that compensates for the over erase of the memory state.

These and other features of the present invention are described below through several specific embodiments with reference to the accompanying schematic drawings.

It is to be noted that the accompanying drawings are schematic and not drawn to practical measurement. Portions of the accompanying drawings are drawn to scale up or shorten for clarity and brevity of the drawings. The same reference numerals used in one embodiment use the same reference numbers in principle with respect to corresponding or similar parts in other embodiments. Although the depletion layer is shown without diagonal lines in FIG. 1, other features not shown in the cross-sectional view are shown in diagonal lines to facilitate visualization in FIGS. 3 through 6.

Figure 1 illustrates a portion of one memory cell of an electrically programmable semiconductor memory in accordance with the present invention. This memory consists of a plurality of such memory cells, which are identical or symmetric to each other in their design. Each cell has a field-effect transistor 5, 6, 11 having a charge accumulation region 11 (preferably in the form of a floating gate, eg doped polysilicon) whose charge state defines the memory state of the cell. , 12). This memory consists of a semiconductor body 10 (e.g. silicon), the semiconductor body 10 of which the body 10 on the p-conductive first region 1 of the body 10 is formed for each cell. It has a first insulating layer portion 21 (eg silicon dioxide) present on the surface. The floating gate 11 extends on the surface of the first insulating layer portion 21. Each cell has at least a source region 5 and a drain region 6 of each transistor in a part of the first region 1 in the downward direction of the charge accumulation region 11. Each cell has programming means constituting the n-type implanted region 2 present in the body 10 and forming a p-n junction with the first region 1. A control gate 12 (eg doped polysilicon) is capacitively coupled with the floating gate 11. This capacitive coupling is preferably achieved by providing a control gate 12 on the second insulating layer portion 22, wherein the floating gate 11 extends between the insulating layers 21 and 22.

According to the invention, the injection region 2 is located in the body 10 (eg in the form of a buried layer) so as to be below the first region 1 below the floating gate 10. The p-type first region 1 passes through the depletion layer 1 'that crosses the thickness T direction of the first region 1 in the vertical direction to the injection region 2 by application of the programming voltages Vb and Vd. It has a sufficiently low acceptor doping concentration Na at least over the injection region 2 to cause a punch draw. The control gate 12 and the surface of the first region 1 and the injection region 2 have a programming voltage Vb for biasing the control gate 12 (via the source and drain regions 5, 6) (eg about 15V) and connection terminals B, (S + D), and A for applying a programming voltage Vd (e.g., about 5V) for biasing the surface of the first region 1 with respect to the injection region 2 Each exists. As a result, the desired charge state of the floating gate 11 is set by hot electron injection in the vertical direction from the n-type injection region 2 to the floating gate 11 (so that the cell is programmed). The n-type implanted region 2 is biased with zero voltage between programming. The peripheral p-type body portion may be 0V.

The zero bias potential barrier Vo of the p-n junction between the injection region 2 and the first region 1 is lowered by the punch draw of the depletion layer formed in the region 1 by the voltages Vd and Vb. If this depletion layer punches against a narrow zero bias depletion layer (of width Xo) around the region 2, the pn junction is biased in the forward direction and the electrons are punched out from the n-type implanted region 2 It flows into the area 1. These electrons are heated by acceleration to the depletion layer 1 'and, as indicated by the arrow 18, are directed to the insulating layer 21 by this electric charge. An important part of these hot electrons has sufficient energy for ingress into the insulating layer 21 and drift to the floating gate 11 under the attraction force of the constant voltage Vb coupled from the control gate 12. During programming, electrons that did not enter the layer 21 are drawn out by the source region 5 and the drain region 6 of the transistor of the memory cell, as indicated by arrow 19. Since these source 5 and drain region 6 are preferably located outside of the substrate surface of FIG. 1, as described with reference to FIGS. Except for the part located in 3), it is shown by the outline of a dashed-dotted line in FIG. During programming, these n-type source and drain regions 5, 6 are held at a potential (e.g., 5V), and the associated depletion layers 5 'and 6' are also shown as dashed outlines. Since a continuous channel inversion layer is formed in the depletion layer on the surface of the p-type main body below the gate structure, the potential of the surface of the region 1 is applied to the source 5 and drain 6 region Vd voltage. Vc = Vd + 2φF, where φF represents a potential difference between the Fermi level and the mid-bandgap level of the region 1. This injection arrangement has several advantages. The injector 2 does not need an extra bias voltage. The injector 2 is only injected when the cell is programmed. In addition, the injector 2 is not direct to the injection, and for example, the substrate current is very small since no injection is made to the lower substrate.

When the injector 2 is grounded, the control gate 12 and the source 5 and drain regions 6 of the transistors are raised to high potentials (e.g. 15V and 5V, respectively) to maintain voltage distribution on the punch draw region. Thus it can be understood that punch throw can occur only when electrons can be injected into the floating gate 11 by this. When the n-type injector 2 is raised to an electric potential (for example, 5V) instead of grounded, or when the source 5 and the drain region 6 are 0V instead of 5V or the control gate is 0V. All punch draws are prevented. Therefore, in the case of a programming cell in which one row of the memory matrix is selected, the injector 2 of the unselected adjacent rows can be prevented by applying these different voltages. This allows for a simple coupling design as described with reference to FIG.

The minimum voltage Vp required for the punch draw depends very much on the doping level Na and the thickness T of the region 1 between the injection region 2 and the body surface. This punch draw voltage Vp is: Vp + Vo = A. Na (T-Xo) ² , where A is an integer.

The calculation shows that for a punch draw voltage Vp of 4 V, the distance T is about 0.5 μm for a doping level Na of 5 × 10 ¹⁶ cm ⁻³ and about 0.8 μm for a doping level Na of 2 × 10 ¹⁶ cm ⁻³ . .

By increasing the programming voltage above Vp, the potential barrier of the pn junction between region 1 and region 2 decreases as a result of the flow of current from injection region 2 to punch draw region 1. do. This punch draw electron current I is: I = Io.exp ((-B.Xo / T) (Vc-Vp)), where B is an integer and Vc is the voltage applied to the punch draw region.

A high electric field for heating electrons is generated in the punch draw depletion layer 1 '. In order to achieve high implantation efficiency, the accelerated electric field in the depletion layer should be higher than the barrier between the semiconductor body 10 and the first insulating layer 21 (e.g., about 3.2V of the barrier between silicon and dicyclic silicon). . Therefore, it can be achieved by biasing the source 5 and the drain region 6 from a conventional 5V supply. Control gate 12 requires a voltage Vb that is high enough to keep the transistor on during programming. This Vb size depends on the size of the capacitive coupling and also on the surface of the body (the depletion layer) even within the higher doping concentration boundary region 3 (see below) between the transistor channel region and the punch draw region 1 (see below). Should be sufficient to maintain the inversion layer. Vb is typically between 15V and 20V. Since the control gate 12 draws only a small current, this high voltage Vb can be generated by a simpler method of charge pump than the 5V voltage source.

Preferably, in order to facilitate the manufacture of the device, the punch-draw first region 1 in which the same doping level Na is the same as in the transistor region 4 of the cell (at least to the same depth T). Exist within. Therefore, for example, the implantation region 2 may constitute an ion implanted n-type well in the p-type portion (substrate) of the main body 10, and also shallower ions formed in the portion adjacent to the transverse direction of the p-type portion. The p-type wells of the implant may overlap and doped over a portion of the n-type region to form a punch draw first region 1 above the implant region 2. This cell structure is shown in FIG. The doping level Na thus affects several parameters of the memory cell. (1) The floating gate voltage allows injection of electron injection beyond the silicon to the silicon dioxide barrier, which voltage is minimum for a doping level Na of approximately 2 × 10 ¹⁶ to 5 × 10 ¹⁶ cm ⁻³ . (2) Either of the source and drain voltages decreases with increasing doping level Na (to cross the same barrier) and is less than 5V for doping levels greater than 1 × 10 ¹⁶ cm ⁻³ . (3) the implantation probability increases due to an increase in the doping level Na, and (4) the threshold voltage of the non-programmed cell increases with an increase in the doping level Na, but this is also the same process in other parts of the circuit. It relates to the threshold voltage for the n-type channel MOS transistor formed. (5) With the increase of the doping level Na, the punch draw voltage Vp increases, which also changes due to the change in the depth T at which the injector 2 is located.

Considering these various parameters, the high value of the doping level Na is suitable for high programming speeds, but should not exceed about 5x10 ¹⁶ cm ^-3 if the use of a low programming voltage is required. Moreover, it is desirable to limit Na to obtain sufficient threshold voltages for n-type channel MOS transistors in other parts of the circuit. A punch draw voltage Vp and (e.g., about 4V) more sufficient for an acceptor doping concentration of 5x10 ¹⁶ cm ^-3 for the corresponding portion of the transistor region 4 can be obtained.

In the cell structure of FIGS. 2 to 5, if the same doping concentration Na on the thickness of the first region 1 is to exist throughout the length between the region 1 and the transistor region 4, the source of the transistor Punch draw coupling between the injection region 2 and the source 5 and the drain 6 by separating the injection region 2 laterally at a significant distance from the drain region 6 and the drain region 6. It is necessary to avoid the transverse expansion of the depletion layers 1 ', 5', 6 ', which results in. Therefore, for a doping concentration Na of about 5 × 10 ¹⁶ cm ⁻³ and a depth T of 0.5 μm, this separation distance should be at least 2.5 μm. This increases the size of the memory cell. However, according to the present invention, the lateral expansion of the punch draw depletion layer is limited by including at least one boundary region 3 of the same conductivity type as the punch draw region 1, but at this time, the doping concentration is higher. Increases. FIG. 2 shows a transistor region 4 which is laterally separated from the first region 1 of the punch draw by such a boundary region 3. Transistor source 5 and drain region 6 are present in region 4 (see FIGS. 3 to 5), but are not visible in the illustration of FIG. 2. Compared to the deeper depletion layers in the punch draw region 1 and the transistor region 4, only a very shallow depletion layer (with a surface inversion layer) has a higher concentration between the region 1 and the region 4. It extends on the surface of the boundary area 3. With this separation boundary region 3, the source 5 and the drain 6 of the transistor are further separated from the injection region 2, for example in a transverse separation of about 1.25 μm and in a transverse separation of less than about 0.7 μm. ), It is also possible to obtain a small compact cell structure.

The boundary region 3 can also prevent parasitic coupling of the injection region 2 to the body surface. Therefore, the inventors of the present invention have shown that ion implantation of an n-type well for forming the region 2 provides that a boundary region 3 of higher doping concentration is provided in the region (ie, the region shown in FIG. 2). Because it is not installed in the area, it extends to the surface between the area 1 and the area 4 (ie from the injector end 42 as shown in FIGS. 3 and 4). Can be an n-type protrusion. In addition, as shown in FIG. 3, each cell is laterally lateral in at least two longitudinal directions by a buried insulating layer comprising the first region 1 or forming part of the field oxidation pattern 29. An active island portion defined in the direction is formed in the main body 10. Other portions of the field oxidation pattern 29 around the island may be formed by other processes. Here, for example, most of the field oxidation pattern 29 may be buried by silicon local oxidation (LOCUS) in the initial stage of the manufacturing process, and further formed (for example, shallow n-type bonding region pattern 8). Afterwards, other portions of the field oxidation pattern 29 may be deposited, such as portions 29a of the adjacent source region 5 and drain region 6 and implantation coupling region 8. 3 is not a cross-sectional view, but the field pattern 29 is shown diagonally to facilitate visualization of the island structure. That is, in this particular embodiment the island portions of two adjacent cells in the common n-type coupling region 8 are adjacent to each other. The island portion has two longitudinal sides 30 and a cross section 31 which are symmetric about the plane 32. The n-type injection region 2 of each cell extends below the punch draw region 1 from the common coupling region 8. The region of the injection region 2 in the island portion is shown in FIG. 3, which region 2 extends between the longitudinal side surfaces 30 and up to the injector end 42. Can be. The parasitic n-type coupling of the implanted region 2 to the body surface may occur at these sides of the buried field pattern 29, or in order to avoid this, the p-type boundary region 3 has two It is provided so as to be adjacent to the buried field pattern 29 of the opposite side surface 30.

Thus, for this embodiment, each cell extends to the injector portion 42 along the two sides 30 so as to extend laterally around the lower doping concentration punch-draw region 1. The border area 3 (this form is shown by the diagonal line in FIG. 4) may be provided. In this way, the clear longitudinal punch draw region 1 is defined between the injection region 2 and the floating gate charge accumulation region 11.

Furthermore, the boundary region 3 separates the island portion transversely at opposing first and second ends extending across the island portion of each cell 42. The punch-draw region 1 and the downward injection region 2 extend below the portion of the floating gate charge accumulation region 11 at the first end (adjacent to the coupling region 8). The transistor source 5 and the drain region 6 extend in the second end (adjacent to the side surface 31). In other words, another portion of the floating gate charge accumulation region 11 extends at least on the channel region between the source region 5 and the drain region 6. This forms an island structure of particularly compact cells with a clear lateral punch draw. A compact design for forming a bond to these source region 5 and drain region 6 is described below with reference to FIG.

As shown in FIGS. 2 and 5, in the case of the control gate 12 and the EEPROM, the erase gate 14 is formed on the second insulating layer 22 on the floating gate 11. The erase gate 14 has an overlap region smaller than the floating gate 11 than the control gate 12, so that the capacitive coupling to the floating gate 11 results in the control gate 12 being coupled to the floating gate 11. Smaller than capacitive coupling. Erasure occurs by charge tunneling from the floating gate 11 to the erase gate 14 through the insulating layer 22. Both of the control gate 12 and the erasing gate 14 may be formed by, for example, impurity polycrystalline silicon tracks extending in parallel with each other and across the longitudinal lateral side 30 in the longitudinal direction of the island of the cell. Each of the cells in one column of the memory matrix has a common control gate track 12 and a common erase gate track 14. Another insulating layer (not shown) deposits gate tracks 12 and 14. The injection coupling region 8 may be connected to a window 28 in an insulating layer structure, or together in a row by metal tracks 18 extending parallel to the longitudinal side surfaces 30 of the island of the cell. May be combined.

In a representative example, the buried field pattern is 700 nm thick, using, for example, local oxidation (LOCOS) technology in p-type silicon body portion 10 having boron doping of about 2x10 ¹⁵ cm ^-3 . The main body may be, for example, an epitaxial layer having a thickness of 3 to 5 탆 on a p-type substrate having a higher doping concentration. Since p-type and n-type wells can be ion implanted using, for example, complementary masks, the entirety of the body surface is ion implanted in either p-type or n-type. High energy ion implantation of boron and phosphorus may be used to penetrate into the insertion field pattern 29. In the case of the p-type well, approximately 1.5 to approximately 1.2 × 10 ¹² cm ^-2 and 350KeV boron ions of boron ions of 210KeV × 10 ¹² cm ^-2 to about 1.5 × 10 ¹² ions cm boron ions ^-2 70KeV Used to form the bulk of the p-type wells (region 1 and transistor region 4) with threshold-adjusted ion implantation of. In the case of the n-type well (which includes the injector 2), about 2 × 10 ¹³ cm ⁻² of 1MeV ions are combined with a critically adjusted ion implantation of about 6 × 10 ¹¹ cm ⁻² of 50KeV boron ions. use. Similar to forming the regions 1, 2, and 4 in the memory cell region, these ion implanted n-type and p-type wells may be provided to other parts of the circuit arrangement, for example, to implement a CMOS circuit. In order to provide the boundary region 3, extra local boron ion implantation is carried out, for example, with about 5 × 10 ¹² cm ⁻² of boron ions of 150 KeV, and an n-type coupling protrusion (for example, facing the surface from the periphery of the implant region 2) In order to prevent spurs, the boundary region 3 will be at a concentration about three times higher than the punch draw region 1 and about half of the dose of the n-type well ion implantation. In the case of using a 1.25 microprocessing technique, for example, the width of the area 3 along the both sides 30 is about 1.25 μm such that a width of about 1.25 μm for the punch draw area 1 remains. The depth of the region 1 may be, for example, 0.5 μm. A gate oxide layer 21 of about 25 nm may be grown on the active region of the cell. Shallow source and drain regions of the transistor may be formed by low energy ion implantation into the active region, along with shallow high concentration contact regions such as surface doping for the implant coupling region 8.

The electrically erasable memory cell of FIGS. 2-5 with a punch draw voltage Vp of 4V operates as follows. (1) In the case of writing (programming), the substrate 10 (terminal E) and the injector 2 (terminal A) are 0 V, and the source 5 and the drain 6 (terminals S and D) and erase The gate 14 (terminal C) is, for example, 5V and applies a programming pulse Vb between 15V and 20V to the control gate 12 (terminal B). (2) In the case of erasing, the substrate 10 and the injector 2 may be 0V, and the control gate 12, the source 5, and the drain 6 may be 0V, but preferably 5V, for example, and the erase gate. 14 rises between 15V and 20V. (3) In the case of reading, a transistor with a source of 0V and a drain between 1V and 2V is used, while the control gate 12 and the erase gate 14 are for example 5V while the injector 2 remains at 0V. do. The application of other voltages to the memory cells is valid for circuitry circuitry of the memory. Each combination of the erase gate 14 and the control gate 12 to the underlying floating gate 11 defines a different charge state of the floating gate 11 for each case of erasing and programming. The combination of voltage Vd and control gate 12 sets the threshold voltage of the memory cell after programming. At voltage Vb (15-20V) on control gate 12, the potential of the floating gate is reduced to the level of the voltage at which the channel inversion layer of the transistor is blocked by injection of hot electrons 18 Programming stops. This is a definite level that depends on the threshold voltage. The erase of the program state of the floating gate 11 is effective for the erase gate 14 when the erase gate 14 rises to a high potential potential by electron tunneling through the insulating layer 22. Since it is possible to select the thickness of the insulating layer 22 and the roughness of the surface of the polycrystalline silicon gate 14, the same voltage level (15 to 20V) as that applied to the control gate 12 for programming is erased. It is used for the erase gate 14. The erase voltage level can be controlled by an effective feedback mechanism comprising the injector 2. The control gate 12 is kept at a low voltage (eg 5V) and the erase gate 14 raises to a high voltage (eg 15-20V) while the source 5 and drain 6 are at 5V, the injector 2 By biasing 0) to 0V (ie, programming mode), the erase will raise the floating gate voltage (by tunneling the electrons). In this case, if the potential of the floating gate 11 starts with an excessive electrostatic potential by transient erasing, and if the transistor is turned on, the level of the voltage on the other region is such that hot electron ion implantation 18 causes the punch draw region. In (11) it starts from master (2), and then erase will stop. Therefore, in the case of this apparatus, there is an advantageous feedback mechanism for compensating for the transient erasure, and as a result there is a clear termination state of the gate 11 for erasure. The difference of the threshold voltage (programming window) between the erase cell and the program cell is determined by the high voltage (15-20V) applied to the control gate 12 between programming and the low voltage (eg, 5V) applied to the control gate 12 between erasing. Is determined by the difference between If a difference in threshold voltage of only about 5V is desired, the low voltage may be about 13V when the high voltage is at 18V.

The results of the experiment show a highly effective injection of hot electrons and a threshold voltage shift of the transistor with this limited vertical punch draw structure. Therefore, it is possible to obtain a very high injection probability of about 10 ⁻⁴ . A fairly high oxidation current of about 0.8 A cm ^-2 is measured, suggesting a very high programming speed that prevents oxidation from breaking down.

According to the present invention, it is possible to design and operate a memory cell having, for example, a voltage level at which 0 V or 5 V is applied to the injection region 2 and the source region 5 and the drain region 6 of the transistor. Furthermore, in the case of cells programming, reading and erasing cells in adjacent rows and columns of the memory matrix according to the present invention, suitable voltage levels for the various regions may be obtained by compacting the cells as shown in FIG. It can be configured as a layout. This layout avoids the need for isolation contacts for the coupling of S and D to the source 5 and drain 6 regions of the transistor. Therefore, according to the present invention, each n-type coupling region 8 has a common coupling for the injection region 2 of two adjacent cells (e.g., as shown in FIGS. Or extend into four other adjacent cell regions to form a transistor source region 5 or a drain region 6 of that cell in each of these four cells (the source of the cell ( 5) and at least form a bond to the drain 6). In order to facilitate visualization of the layout layout, in FIG. 6 one such injection coupling region 8 and the island portion of one cell are indicated by diagonal lines. Parallel metal tracks 18 adjacent to the row of injection coupling regions 8 (via window 28) may form the bit lines of the memory matrix. The word line may be formed by a control gate track 12 (not shown in FIG. 6) extending perpendicular to the track 18. As shown in FIG. The state of the cells in one row can be read by controlling the voltage on two adjacent bit lines, or these two adjacent bit lines are also used to program and erase the cells.

As will be appreciated from the above description, it will be apparent to those skilled in the art of semiconductor memory design and semiconductor device technology that many variations and applications are possible within the scope of the invention. FIG. 7 shows a simple modification of the structure of FIG. 2, so that in this modification, the injection region 2 extends below the middle portion 33 of the buried field pattern 29 of the same conductivity type n. Die) is a buried layer 82. This intermediate portion 33 extends from the end 31 to the island portion at the opposite end. In this state, there is a danger that a punch draw of time rise or other coupling of the injection region 2 to the inversion layer below the gate 11 may occur on the side of the buried portion 33. Therefore, according to the present invention, the buried portion on the buried layer 82 includes a boundary region 3 which is of the same conductivity type as the punch draw region 1 or a boundary region having no higher doping concentration in the boundary region 3. Adjacent to this side of 33.

In the embodiment of FIGS. 2-7, the region of the source 5 and the drain 6 of the transistor is injector 2 via a boundary region 3 extending in a direction crossing the width of the island portion. It is in the island area 4 separated laterally from the area | region containing. 8 shows a modified structure, in which each cell has a source region 5 and a drain region 6 of a transistor, each of which is formed in the boundary region 3 of a higher doping concentration p +. These regions 3 extend below each of the source region 5 and the drain region 6 and are separated from each other in the channel region of the transistor below the floating gate 11. In this configuration, the injector 2 may be inserted near or below the regions of the source 5 and the drain 6, thus obtaining a more compact memory cell. These boundary regions 3, source 5 and drain 6 may be formed by impurity ion implantation using insulating gate 11 as a mask. The erase gate 14 may be capacitively coupled to the floating charge accumulation region 11. Thus, for example, the erase gate 14 may be present on the insulating layer 22 over a portion of the charge accumulation region 11 outside of the plane of FIG. 8.

FIG. 9 also shows another variant, in which the drain region 6 is formed in the boundary region 3 (as in FIG. 8), but the source region 5 is in the boundary region 3. It is not formed inside. In this case, only the coupling (at Vd) to the drain region 6 is used to remove these hot electrons that are not injected into the insulating layer 21 between programming and bias the semiconductor surface below the gate structure. . The source region 5 resides over one part of the injector 2 and is connected to the injector 2 by a short circuit region 52 formed simultaneously with the same conductivity type, for example an n-type well. In this case, a very compact cell structure can be obtained, but more current will flow between programming. Therefore, between programming, the bias of the drain 6 relative to the injector 2 and the source 5 will coincide with the punch draw current in the vertical direction and the current through the transistor will flow in the horizontal direction. In the memory cell of FIG. 9, the erase gate 14 may be capacitively coupled to the programming charge accumulation region 11. Thus, for example, the erase gate 14 may be present on the electrically insulating layer 22 over a portion of the charge accumulation region 11 outside of the figure of FIG.

FIG. 10 shows a variation of the structure of FIG. 9, in which the floating charge accumulation gate 11 is part of the transistor channel length between the source region 5 and the drain region 6 (the drain region ( Adjacent to 6), or in this structure, the insulating gate 14 extends (adjacent to the source region 5) over the remainder of the transistor channel length. By installing the floating charge accumulation gate 11 and the insulated gate 14 in this arrangement, the flow of current in the horizontal direction between the source region 5 and the drain region 6 described with reference to FIG. 9 is avoided. It is possible to block the channel of the transistor (below the gate 14) between programming. This gate 14 may be capacitively coupled to the floating gate 11 (not shown in FIG. 10) to form an erase gate of the memory cell. Therefore, in the structure of the memory cell of FIG. 10, the next voltage is applied for the programming state. That is, the control gate 12 is between 15 and 20V, the injector 2 (and source region 5) and the erase gate 14 are 0V, and the drain region 6 is between 4 and 10V (e.g. 5V ) These voltages are the same voltages applied for programming in other embodiments than the source region 5. Lateral expansion of the depletion layer punched into the injector 2 of the selected cell has a drain region 6 and is defined by a higher concentration boundary region 3. It will be necessary to further separate drain 6 from main wing ratio 2 even if it is not a high concentration boundary region 3 and a larger depletion layer (space) will be needed for the cell. Erasing can be performed in the same manner as in the other embodiments with the erasing gate 14 between 15V and 25V, while the other terminal being 0V. During programming, the unselected cells are placed in the following states. The entire terminal is set to 0V, or only the drain 6 is set to 4V to 10V, or the control gate 12 is set to 15 to 25V. Under these conditions, the entire cell cannot be programmed. Between readings, source region 5 (and injector 2) is at 0V, drain region 6 is between 1V and 2V, or gates 12 and 14 are, for example, 5V. That is, the voltage of the erase gate 14 induces a conductive inversion channel at the end of the transistor channel region adjacent to the source region 5, while the charge state of the programming gate 11 blocks or completes the transistor channel. Determine whether the transistor is on or off.

It will be apparent that other modifications and applications of the memory cell are possible with the present invention. Therefore, in some arrangements, the control gate 12 may have transverse extensions that exist in some portion of the channel region of the transistor but do not extend on the floating gate 11. 1 to 9 show the control gate 12 on the second insulating layer 22 on the floating gate 11, the control gates (and erasing gates) are for example the insulating layer 21 at the body surface thereof. It can also be configured in another way to have an impurity doped surface region in the body 10 to form a diode capacitively coupled to the programming gate 11 through. The erase gate 14 may exist below a part of the floating gate 11. Erasing does not use special gates 14 as a separate method, for example to transfer charge carriers through gate oxide 21 for source region 5 and drain region 6 or through thin oxide layers elsewhere. It will also be possible to do this. Instead of using a floating gate as the charge accumulation region 11, a charge trap is used to form the charge accumulation region 11 at the boundary between two insulating layers 22 and 21 (eg, silicon nitride on silicon dioxide). This may be done, but this is less effective directly in the injected hot electrons.

Although FIGS. 1 to 10 illustrate hot electron injection, hot hole injection is also performed by the n-type punch draw region 1 on the p-type injection region 2, and the highly doped (n +) It is also possible to use a longitudinal punch-draw injection arrangement of the n-type boundary region 3 and the p-type source 5 and drain 6 regions. However, the injection efficiency of hot holes is several times lower than the injection efficiency of hot electrons.

It will be apparent to those skilled in the art from this specification that other applications are easy. Such applications may include designs, fabrication and use of semiconductor memories, structures of memory devices, semiconductor circuits, and other features already known in these fabrication techniques, which may be used in place of or in addition to features already described. While the specification has described the scope of the claims with respect to particular embodiments of the invention, the scope of the invention disclosed herein is set forth explicitly or implicitly in this specification or as disclosed generally. Regardless of which novel combinations, or novel features of the features of the invention, are not the same as those described in the claims herein, or whether the invention solves some or all of the same technical problems as the invention is intended to solve, It will be clear. The Applicant discloses that there is a possibility of amending the claims and the description of the specification disclosed in this specification during the examination.

Claims (17)

A plurality of memory cells, each memory cell comprising: the plurality of memory cells having a field effect transistor having a charge accumulation region in which a charge state defines a memory state of each of the cells, and the on the first region of the first conductive body; A semiconductor body having a first insulating layer portion in each cell on the surface of the main body, wherein a pn junction is formed on the surface of the first insulating layer portion, the semiconductor main body in which the charge accumulation region extends, and the first conductive region. An electrically programmable semiconductor memory having a second reverse conductivity type injection region for each cell and a control gate capacitively coupled to the charge accumulation region, wherein the injection region is the charge accumulation. Located in the body so as to lie below the first region below the region, at least one of the transistors in each cell The drain, the control gate and the injection region are provided with coupling means for applying a program voltage per cell to bias the surfaces of the control gate and the first region relative to the injection region, in a vertical direction from the injection region. The desired charge state of the charge accumulation region of the cell is set by the injection of hot charge carriers through the first insulating layer portion, and the first region is the first region as the injection region in accordance with the application of the program voltage. Hot charge carriers having a sufficiently low doping concentration of the first conductivity type on the injection region for punching through a depletion layer traversing the thickness direction of the cell in a vertical direction, and which are not injected into the first insulating layer portion, Removed by the coupling means to the drain of the transistor of the cell during programming; At least one boundary region with a typical higher doping concentration lies on at least one side of the first region of each cell and the ball at the side during punch draw crossing the thickness of the first region in a vertical direction. An electrically programmable semiconductor memory, characterized by limiting lateral expansion of the pip layer. 2. The electrically programmable semiconductor memory of claim 1 wherein the boundary region is located above a peripheral portion of the implantation region to prevent parasitic coupling of the surface and the implantation region. 4. The body of claim 1, wherein each of the cells includes the first region and has an island portion in the body, the island portion being bordered by a field insulating layer pattern embedded in the surface of the body. And electrically adjacent to at least one side of the island portion. 4. The electrically injector of claim 3, wherein the injection region extends below the first region between two opposing ends of the island portion, and the boundary region is adjacent to the two opposing ends. Programmable Semiconductor Memory. 4. The method of claim 3, wherein the coupling means for the injection region has the second conductive buried layer extending below the middle portion of the field insulation layer pattern, and the boundary region is adjacent to the side of the middle portion. An electrically programmable semiconductor memory. The transistor of any one of claims 1, 2, 4 or 5, wherein the transistor of each cell has a source drain present in an area of the main body separated laterally by the boundary area from the first area. An electrically programmable semiconductor memory. 7. The cell of claim 6, wherein each cell has an island portion in the body and traverses the island portion so that the boundary region extends so as to separate the island portion into first and second ends that cross laterally. And the first region and the lower injection region are in the first end portion below the portion of the charge accumulation region, and extend in at least a channel region between the source and the drain of the transistor. The other part is present in the second end. 6. The transistor of any one of claims 1, 2, 4 or 5, wherein the transistor of each cell has a source and a drain of the second conductivity type each formed within a boundary region of a higher doping concentration of the first conductivity type. And the boundary region extends below each of the source and drain regions, and is separated from each other in the channel region of the transistor below the charge accumulation region. 3. The transistor of claim 1 or 2, wherein the transistor of each cell has a drain region of a second conductivity type within a boundary region of a high doping concentration of the first conductivity type, the transistor further being coupled to the implantation region. An electrically programmable semiconductor memory comprising a source region of a second conductivity type. 10. The method of claim 9, wherein the charge accumulation region extends only over a portion of the length of the transistor channel between the source and drain regions, and the insulated gate extends over the remainder of the length of the transistor channel. Electrically programmable semiconductor memory. 11. The electrically programmable semiconductor memory of claim 10 wherein said insulated gate is also capacitively coupled to said charge accumulation region for providing an erase gate of said memory cell. 12. The apparatus of any one of claims 1, 2, 4, 5, 7, 10 or 11, wherein each cell comprises an island portion of the body, wherein the island portion of the two adjacent cells is And electrically adjacent to each other a second conductive type coupling region that forms a common coupling to the implantation regions of two adjacent cells. 13. The method of claim 12, wherein the coupling region of the second conductivity type is in addition to the two adjacent island portions to form a coupling region of a source and a drain of the transistor in each of the four island portions. An electrically programmable semiconductor memory characterized in that it is serially arranged in four different adjacent island portions. 14. The device of claim 1, 2, 4, 5, 7, 10, 11 or 13, wherein the control gate is present in a portion of the second insulating layer on the charge accumulation region, and the charge accumulation region is the first. And a floating gate between the first and second insulating layer portions. 15. The memory cell of claim 14, wherein the memory cell has an erase gate, the erase gate on the charge accumulation region to perform an electrical erase of the memory state of the cell by applying an erase voltage to the erase gate. And electrically present in the second insulating layer. 16. The method of any one of claims 1, 2, 4, 5, 7, 10, 11, 13 or 15, wherein the charge accumulation region has a capacitive coupling smaller than that of the control gate. Each memory cell having an erase gate coupled and biasing the control gate to a lower voltage and electrically erasing the program charge state of the cell while biasing the surfaces of the first region and the implant region to a program voltage. And coupling means for applying an erase voltage to the erase gate for performing an operation, whereby hot carriers are injected from the injection region to the charge accumulation region to compensate for the over erasure of the memory state. Programmable Semiconductor Memory. 16. The implantation region of any of claims 1, 2, 4, 5, 7, 10, 11, 13 or 15, wherein the implant region has an n-type well implanted into the p-type portion of the body and is shallower. An ion-implanted p-type well is formed in a portion adjacent to the p-type portion in a transverse direction, and overlaps and overdopes a portion of the region of the n-type well on the implanted region. An electrically programmable semiconductor memory, characterized by forming one region.

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