KR0181837B1 - The demodulation device of ntsc color signal using equalizer - Google Patents

Abstract

The present invention relates to a demodulation device for NTSC color signals using an equalizer, comprising: a subtractor 106, first and second multipliers 108-1 and 108-2, each of which is comprised of first and second subtractors 106-1 and 106-2. In a television equipped with an equalizer for equalizing all of NTSC, VSB, and QAM signals including a multiplier 108 and a delay unit 110, the band pass filter unit 113 performs band pass filtering upon inputting an NTSC signal. )Wow; A first multiplexer (115) for selecting the filtered NTSC color signal; A second multiplexer (117) for selecting a color signal from the first multiplexer (115); And a complex multiplier 121 which receives the output signals of the first and second multiplexers 115 and 117 and outputs a color difference signal. And a digital phase locked loop 132 for outputting a positive cosine signal and a gain control signal, and inputting an NTSC signal using a derotator in an equalizer used to remove frequency and phase errors in inputting QAM and VSB signals. By demodulating the raw NTSC color signal, hardware is simplified and the cost can be reduced by eliminating the color burst synchronization and color signal demodulation circuits.

Description

NTSC color signal demodulation device using equalizer

1 is a block diagram of a conventional equalizer.

2 is a block diagram of a conventional finite shock response adaptive digital filter.

3 is a detailed block diagram of the finite shock response adaptive digital filter unit.

4 is a block diagram of a decision feedback equalizer that equalizes all NTSC, VSB, and QAM signals.

5 is a block diagram of a demodulation circuit of a conventional NTSC color signal.

6 is a block diagram of an NTSC color signal demodulation device using an equalizer according to the present invention.

* Explanation of symbols for main parts of the drawings

100: DC offset removing unit 102: feed forward filter unit

104: feedback filter section 106: subtraction section

108: multiplication unit 110: delay unit

113: band pass filter 113-1: multiplexer

113-2: digital filter 113-3: coefficient storage unit

115: first multiplexer 117: second multiplexer

119 subtractor 121 complex number multiplier

122: third multiplexer 124: signal discriminating unit

126: training signal generator 128: fourth multiplexer

130: tap coefficient calculating unit 132: digital phase locked loop

The present invention relates to an NTSC color signal demodulation device using an equalizer, and in particular, an analog NTSC (National Television Syste Committee) signal and a digital VSB signal (Vestigital SideBand: VSB). And a QAM signal (Quadrature Amplitude Modulation: QAM). The present invention relates to a color signal demodulation device for an NTSC signal configured to demodulate a color signal C of an NTSC signal using a derotator of an equalizer capable of equalizing both.

Since high definition television (HDTV) broadcasting is based on terrestrial broadcasting, signal degradation due to transmission appears to vary by region.

The biggest advantage of digital broadcasting is that the picture quality can be perfectly restored if the distortion of the signal is small enough to not misjudge the digital signal.

On the other hand, in the analog method adopted by the current NTSC method, since the distortion of the image quality is proportional to the distortion of the signal, perfect restoration is impossible, but even if a slight distortion occurs during transmission, the image quality does not become unrecognizable.

However, the digital system requires a device capable of preventing the degradation of the signal because it can seriously affect the image quality if the signal degradation causes an erroneous determination of the digital signal.

That is, the signal transmitted from the transmitter generates various distortions as it passes through the transmission channel.Further, the distortion is caused by Gaussian thermal noise, impulse noise, and fading. Or deformation due to multiplication noise, frequency variation, nonlinearity, time dispersion, or the like.

The technique of reducing the bit detection error at the receiving side by compensating for the distortion caused by the non-ideal transmission channel is called channel equalization, and the equalizer performing such a technique is a distortion of the signal transmitted at the transmitting end. It compensates for the characteristic change of the channel over time at that time.

Such a channel equalizer is an essential part of a receiver in a high definition television based on NTSC terrestrial broadcasting and simultaneous broadcasting.

The most basic principle of the equalizer is to obtain the transfer function of the transmission channel and configure the circuit to have the inverse of the transfer function.

However, since the characteristics of the channel are not always constant but change frequently depending on time and place, the equalizer must be configured to follow the channel characteristics at that time. Such an equalizer is called an adaptive equalizer.

The operation principle of the adaptive equalizer as described above is as follows.

If you do not know the characteristics of the channel at all, send a training sequence at the beginning of signal reception to determine that the tap coefficients of the equalizer cancel the distortion characteristics of the channel during this period. Mode is entered, and normal data transmission is performed.

1 is a block diagram of a conventional equalizer, which includes: an FFE filter unit 1 for filtering and outputting an input signal with an updated tap coefficient value; A DFE filter unit 2 for removing interference between existing signals using signal symbols previously detected with updated cap coefficient values; A subtractor (3) which subtracts the output signal of the DFE filter unit (2) from the output signal of the FFE filter unit (1); A first frequency mixer unit 4 which receives a signal subtracted by the subtractor 3 and a carrier recovery signal and mixes the base signal to output a base signal; A signal discriminating unit 6 which receives the output base signal and outputs a discriminating signal; A subtractor (8) which receives the base signal output from the first frequency mixer (4) and the discrimination signal output from the signal discriminator (6) and outputs a discrimination error signal as a difference signal between the two signals; A carrier recovery unit 10 receiving the subtracted determination error signal and outputting a carrier signal; A second frequency mixer unit 12 which receives the discrimination error signal output from the subtractor 8 and the carrier signal output from the carrier recovery unit 10 and mixes the mixed signal to output an error signal; An error calculator 14 for receiving the output error signal and outputting a calibration error signal calculated by a decision feedback equalization algorithm; And a tap coefficient updating unit 16 which receives the calibration error signal and updates the tap coefficient value of the filter unit 2 according to an adaptive algorithm, and then applies the updated tap coefficient signal to the filter unit 2. do.

The conventional equalizer configured as described above, after the input signal is filtered through the FFE filter unit 1 and the interference between the existing signals is removed by the DFE filter unit 2 using signal symbols detected in the past, the subtractor 3 Subtracts the output signal of the DFE filter unit 2 from the output signal of the FFE filter unit 1, and the subtracted signal and the carrier recovery signal are input to the first frequency mixer unit 4, and then A basis signal is inputted to the subtraction unit 8 together with the discrimination signal output through the signal discrimination unit 6, and a discrimination error signal is output as a difference signal between the two signals, and the output discrimination error signal is output. Is input to the carrier recovery unit 10 to output a carrier signal, and the carrier signal is input to the first frequency mixer 4 and the second frequency mixer 12 to convert the filter output signal into a base signal. Discriminant error signal error The error signal converted into an arc and input to the error calculating unit 14 as a result of the second frequency mixer 12 to output a correction error signal calculated by a decision feedback equalization algorithm, and receiving the correction error signal. The tap coefficient updating unit 16 updates the tap coefficient value according to the adaptation algorithm and applies the updated tap coefficient signal to the filter unit 2.

2 is a block diagram of a conventional finite-impact response adaptive digital filter, in which a finite impulse response filter (FIR filter) is updated by a tap coefficient signal and a tap address signal input over n + 1 times. A finite shock response adaptive digital filter unit for outputting a signal obtained by filtering an input signal with coefficients; A subtractor 22 for outputting an error signal that is a difference between the filtered signal and the request signal; A tap coefficient update value calculator 24 which receives the error signal and calculates a tap coefficient update value; A tap address generator 26 which generates and outputs a tap address signal corresponding to each tap of the finite shock response adaptive digital filter unit 20; And n + 1 tap coefficient values, which are the calculation results of the tap coefficient update value calculating unit 24, and apply tap coefficient values corresponding to the input tap address signals to the finite shock response adaptive digital filter unit 20. It consists of a tap coefficient buffer 28.

FIG. 3 is a detailed configuration diagram of the finite shock response adaptive digital filter unit. The finite shock response adaptive digital filter unit 20 includes a tap address signal and a tap coefficient buffer unit 28 from the tap address generator 26 of FIG. A multiplier that receives a tap coefficient signal from the tap coefficient register unit 30A-1 for outputting the tap coefficient and multiplies the input signal with the tap coefficient output from the tap coefficient register unit 30A-2, and outputs a multiplication result ( A basic filtering unit 30A composed of 30A-3); From the first input signal latch unit 30B-1a for receiving the input signal and outputting the first latch signal, and from the tap address signal and the tap coefficient buffer unit 28 from the tap address generator 26 in FIG. Multiplies the first tap coefficient register unit 30B-2a for receiving the tap coefficient signal and outputs the tap coefficient, and multiplies the first latch signal by the tap coefficient output from the first tap coefficient register unit 30B-2a; An auxiliary filtering unit 30B in which a plurality (n) of the first multipliers 30B-3a for outputting a result are connected in parallel; And an adder 30C for adding the multiplication results output from the respective multipliers 30a-3 and 30B-3a to 30B-3n to output an output signal obtained by filtering the input signal.

Referring to the operation of the conventional finite shock response adaptive digital filter configured as described above, the input signal is applied to the finite shock response adaptive digital filter 20 and the tap coefficient update value calculation unit 24.

In the finite shock response adaptive digital filter unit 20, when an input signal is applied to the first input signal latch unit 30B-1a and the multiplier 30A-3, the first input signal latch unit 30B-1a provides a first input signal. The latch signal is output, and the multiplier 30A-3 multiplies the tap coefficient output from the tap coefficient register section 30A-2 with the input signal and outputs the multiplication result. The multiplier 30A-3a also outputs the multiplication result. In the same manner as the multiplier 30A-3, the first latch signal is multiplied by the tap coefficient, which is the output of the first tap coefficient register unit 30B-2a, and the result is output to the adder 30C. The adder 30C adds up to the outputs of the n-th multiplier 30B-3n and outputs a signal.

In this case, the tap coefficient signal applied to the finite shock response adaptive digital filter unit 20 is stored in one of the tap coefficient register units 30A-2 and 30B-2a to 30B-2n selected by the tap address signal applied together. .

As a result, in order to write the new tap coefficient in all the tap coefficient register sections 30A-2 and 30B-2a to 30B-2n, the tap coefficient signal and the tap address signal must be inputted n + 1 times.

The tap coefficient update value calculation unit 24 receives an error signal that is a difference between the request signal and the output signal of the adder 30C, and performs a tap coefficient update value operation. All are recorded in the coefficient buffer unit 28.

The step address generator 26 outputs a tap address signal corresponding to each tap of the finite shock response adaptive digital filter unit 20 to the finite shock response adaptive digital filter unit 20 and the tap coefficient buffer unit 28. Is authorized.

The tap coefficient buffer unit 28 applies the tap coefficient value corresponding to the input tap address signal to the finite shock response adaptive digital filter unit 20 as a tap coefficient signal, and applies the tap coefficient signal of the finite shock response adaptive digital filter unit 20. Only after the tap coefficients are updated, the input signal is filtered and the filtered signal is output.

4 is a block diagram of a decision feedback equalizer for equalizing all NTSC, VSB, and QAM signals. The equalizer includes a DC offset remover 100 that removes a DC offset with respect to a signal of an in-phase channel and a quadrature-phase channel. Wow; A feedforward filter unit 102 for receiving the input signal from which the DC offset is removed and the coefficient updated signal and outputting the filtered signal; A feedback filter 104 which receives a signal selected from the discrimination signal and the training signal and a signal updated with coefficients and outputs a filtered signal; A subtraction unit 106 for subtracting the filtering signal from the feed forward filter unit 102 and the filtering signal from the feedback filter unit 104 to output a difference signal; A multiplier 108 for multiplying the difference signal and the automatic gain control signal; A delay unit (110) for delaying the multiplied in-phase (I) signal; A first multiplexer (112) for selecting one of the multiplied in-phase signal and the delay signal; A digital filter (114) for converting the multiplied in-phase signal into a quadrature phase signal; A coefficient storage unit (116) for storing coefficients of the digital filter (114); A second multiplexer (118) for selecting one signal from the quadrature phase signal output from the digital filter (114) and the multiplied quadrature phase signal of the multiplier (108); A complex multiplier (120) that receives a signal selected by the first multiplexer (112) and a signal selected by the second multiplexer (118), and multiplies a sine wave and a cosine wave to correct a frequency and a phase error of a carrier; A third multiplexer (122) which selects one signal from an in-phase signal from the complex multiplier (120) and a difference signal from the subtractor; A signal discriminating unit (124) for receiving a signal for the in-phase channel selected by the third multiplexer (122) and a signal for the quadrature phase channel output from the complex multiplier (120) and outputting a discrimination signal; A training signal generator 126 for generating a training signal; A fourth multiplexer (128) which selects one of the determination signal and the training signal and outputs a selection signal to the feedback filter (104); The output signal of the complex multiplier 120, the training signal, the signal selected by the fourth multiplexer 128, and a discrimination signal for a quadrature signal Q of the signal discriminating unit 124 are input. A tap coefficient calculator 130 for calculating a coefficient and outputting the calculated tap coefficient to the feedforward filter unit 102 and the feedback filter unit 104; And a digital phase locked loop 132 that receives the output signal of the complex multiplier 120, outputs a sine wave and a cosine wave to remove a phase error, and outputs a control signal to adjust a gain.

The block and operation required for equalization according to each signal are as follows.

1) When inputting QAM signal

Since the QAM signal includes a signal of an in-phase (I) channel and a signal of a quadrature (Q) channel, the first finite shock response in the feedforward filter unit 102 shown in FIG. Filter 102-1: C _I , second finite shock response filter 102-2: C _I , third finite shock response filter 102-3: C _Q , and fourth finite impact response filter 102-4 (C _Q ) are both used, the signal of the in-phase (I) channel is the first finite shock response filter (102-1: C _I ) and the second finite shock response filter (102-2: C _I ) The signal of the quadrature (Q) channel is filtered at the third finite shock response filter (102-3: C _Q ) and the fourth finite shock response filter (102-4: C _Q ).

Also, within the feedback filter unit 104 shown in FIG. 4, the first finite shock response filter 104-1 (D _I ), the second finite shock response filter 104-2 (D _I ), Filtering takes place in both the finite shock response filter 104-3: D _Q and the fourth finite shock response filter 104-4: D _Q.

The first multiplier 120-1, the second multiplier 120-2, the third multiplier 120-3 and the fourth multiplier 120-4 in the complex multiplier 120 shown in FIG. 4. All are used.

On the other hand, blocks that are not required for the equalization process when the QAM signal is input include the delay unit 110, the first multiplexer 112, the digital filter 114, the coefficient storage unit 116, the second multiplexer 118, and the third multiplexer ( 122), the training signal generator 126 and the fourth multiplexer 128. In the case of the QAM signal, since the signal of the quadrature phase channel is also input, there is no need to pass through the digital filter 114 which converts the signal of the in-phase channel into the signal of the quadrature phase channel, There is no need for time delay in the delay unit 110, and there is no need for the coefficient storage unit 116 in which the coefficients of the digital filter 114 are stored. Since the QAM signal compensates the channel by the magnetic force without the training signal, the training signal generator ( 128) is not necessary.

As described above, since the delay unit 110 is not needed, the first multiplexer 112 that selects one signal from the delayed signal and the non-delayed signal is not used, and the digital filter 114 is not required. Since the second multiplexer 118 that selects one of the unsigned signals is not used, and the NTSC output signal is not needed, the output signal of the first subtractor 106-1 in the subtractor 106 and the complex multiplier 120 are used. The first multiplexer 124 in the signal discriminating unit 124 is not used because the third multiplexer 122 which selects one of the output signals of the first adder 120-5 in the inside is not used, and the training signal does not have to be generated. The fourth multiplexer 128 that selects one signal from the discrimination signal of -1) and the training signal of the training signal generator 126 is not used.

As a result, when the QAM signal is input, the signal I 'of the equalized in-phase channel is output from the output terminal of the fourth multiplexer 128, and the signal Q' of the equalized quadrature phase channel is the signal discriminating unit 124. Is output from the output terminal of the second signal discriminator 124-2.

2) When inputting VSB signal and NTSC signal

When the VSB signal and the NTSC signal are input, the first finite shock response filter 102-1, the second finite shock response filter 102-2, and the third finite shock response filter in the feedforward filter unit 102 ( 102-3) Of the fourth finite shock response filters 102-4, only the first finite shock response filter 102-1 is used, and as described above, the first finite shock response filter 104 in the feedback filter section 104 is used. 1) only the first finite shock response filter 104-of the second finite shock response filter 104-2, the third finite shock response filter 104-3, and the fourth finite shock response filter 104-4. Only 1) is used.

In addition, in the case of the VSB signal and the NTSC signal, unlike the QAM signal, the training signal generator 126 for generating the training signal is used because the equalizer is converged by the training signal at the initial stage of the equalization.

When the VSB signal is input, the digital component 114 converts the signal component of the in-phase (I) channel into the signal component of the quadrature phase channel (Q) since the signal component of the quadrature phase (Q) channel is needed to remove the phase error. ) Is used, and the delay unit 110 delays the signal of the in-phase channel by the time required by the digital filter 114, wherein the first multiplexer (1) is selected to select one of the delayed and non-delayed signals. 112) is used.

In this case, the digital filter 114 performs a Hilbert transform in order to convert the signal component of the in-phase (I) channel into the signal component of the quadrature phase channel (Q), and converts the coefficients of the digital filter 114. The coefficient storage unit 116 is used for storage, and a second one is used to select one signal from the signal output from the digital filter 114 and the signal output from the second multiplier 108-2 in the multiplier 108. Multiplexer 118 is used.

The decision feedback equalizer for equalizing all of the NTSC, VSB, and QAM signals configured as described above is for receiving both current analog broadcasts and future digital broadcasts.

5 is a block diagram of a conventional NTSC color signal demodulation circuit, which includes a color burst amplifier 140 for amplifying an input color burst signal; An automatic phase controller (142) for automatically controlling a phase of the amplified color burst signal; A 3.58 MHz oscillator 144 for generating a 3.58 MHz signal in phase with the color burst signal; A first mixer 146 for mixing the cosine signal from the 3.58 MHz and the color signal to output an in-phase signal (I: in-phase); And a second mixer 148 for mixing the sinusoidal signal from the 3.58 MHz oscillator 144 and the color signal to output a quadrature (Q) of a quadrature phase channel.

Referring to the operation of the conventional NTSC color signal demodulation circuit configured as described above, the receiving end separates the carrier color signal and the color burst signal using a band amplification circuit (not shown), and then the color burst signal is transferred to the color burst amplifier 140. The color burst signal is inserted at the back porch of the horizontal synchronization signal at the transmitting end, and inserts 8 to 12 kHz of the 3.58 MHz color carrier which is used to generate the carrier color signal.

The color burst signal amplified by the color burst amplifier 140 is input to the automatic phase controller 142, which synchronizes the output phase of the 3.58 MHz oscillator 144 with the phase of the color burst signal. Play a role.

The cosine signal and the sinusoidal signal having a phase difference of 90 ° are output from the 3.58 MHz oscillator 144. In the first mixer 146, the cosine signal and the color signal are mixed to output a signal of the in-phase channel, and the second mixer 148 is provided. In, the sinusoidal signal and the color signal are mixed to output a signal of a quadrature phase channel.

In NTSC televisions it is common to demodulate the color signals in this manner, but in televisions with crystal feedback equalizers capable of equalizing all of the NTSC, VSB and QAM signals shown in FIG. There is a need to demodulate NTSC color signals using derotators.

Accordingly, the present invention provides a demodulation apparatus for an NTSC color signal using an equalizer configured to demodulate an NTSC color signal using a derotator of an equalizer that equalizes all NTSC, VSB, and QAM signals. The purpose is to provide.

The NTSC color signal demodulation device using the equalizer of the present invention for achieving the above object is a first subtractor and a second subtractor for outputting a difference signal by subtracting the filtering signal from the feed forward filter unit and the filtering signal from the feedback filter unit. NTSC, VSB, and a subtractor comprising an adder, a multiplier comprising a first multiplier and a second multiplier for multiplying the difference signal and the automatic gain control signal, and a delay unit for delaying a multiplication signal from the first multiplier; A television comprising an equalizer for equalizing all of the QAM signals, comprising: a band pass filter unit for receiving band pass filtering from an NTSC output signal from the first subtractor when an NTSC signal is input; A first multiplexer for selecting a band pass filtered NTSC signal from the band pass filter and outputting a color signal; A second multiplexer for selecting a color signal from the first multiplexer; A complex multiplier configured to receive a signal selected by the first multiplexer and a signal selected by the second multiplexer, correct a phase error of a carrier, and output a color difference signal; And a digital phase locked rope that receives the output signal of the complex multiplier, outputs a sine wave and a cosine wave to remove a phase error, and outputs a control signal to adjust a gain.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram of an NTSC color signal demodulation device using an equalizer according to the present invention. The present invention subtracts the filtering signal from the feedforward filter unit 102 and the filtering signal from the feedback filter unit 104. A subtractor 106 comprising a first subtractor 106-1 and a second subtractor 106-2 for outputting a signal, and a first multiplier 108-1 and a multiplier for multiplying the difference signal and the automatic gain control signal; An equalizer 108 comprising a double multiplier 108-2 and a delay unit 110 for delaying the multiplication signal from the first multiplier 108-1 are included to equalize all NTSC, VSB, and QAM signals. A television having an equalizer, comprising: a band pass filter (113) for performing band pass filtering upon receiving an NTSC output signal from the first subtractor (106-1) when an NTSC signal is input; A first multiplexer 115 for selecting a band pass filtered NTSC signal from the band pass filter 113 and outputting a color signal; A second multiplexer (117) for selecting a color signal from the first multiplexer (115); And a complex multiplier (121) for receiving a signal selected by the first multiplexer (115) and a signal selected by the second multiplexer (117) and outputting a color difference signal correcting a frequency and a phase error of a carrier; And a digital phase locked loop 132 that receives the output signal of the complex multiplier 121, outputs a sine wave and a cosine wave to remove a phase error, and outputs a control signal to adjust a gain.

Here, the band pass filter 113 includes a multiplexer 113-1 for selecting an NTSC output signal from the first subtractor 106-1 for band pass filtering when an NTSC signal is input; A digital filter (113-2) for bandpass filtering the selected NTSC signal; And a coefficient storage unit 113-3 storing coefficients of the digital filter 113-2.

The complex multiplier 121 may include a first multiplier 121-1 multiplying a signal and a cosine signal for an in-phase channel selected by the second multiplexer 117; A second multiplier (121-2) for multiplying a signal and a sinusoidal signal for a quadrature phase channel selected by the first multiplexer (115); A third multiplier 121-3 that multiplies the signal for the in-phase channel selected by the second multiplexer 117 and the sinusoidal signal; A fourth multiplier (121-4) for multiplying the signal and the cosine signal for the quadrature phase channel selected by the first multiplexer (115); A first adder (121-5) for summing the output signal of the first multiplier (121-1) and the output signal of the second multiplier (121-2); And a second adder 121-6 summing the output signal of the third multiplier 121-3 and the output signal of the fourth multiplier 121-4.

The digital phase locked loop 132 receives an output signal for an in-phase channel and an output signal for a quadrature phase channel from the complex multiplier 121 and detects a phase difference. Wow; An accumulator 132-2 for adjusting the gain of the detected phase error, and controlling and accumulating the gain; A sine and cosine signal generator 132-3 which receives the output signal of the accumulator 132-2 and outputs a sine signal and a cosine signal; And a cumulative limiter 132-4 that receives the generated cosine signal and outputs a gain control signal.

Referring to the operation and effects of the present invention configured as described above in detail.

When a signal of an in-phase channel (I) and a signal of a quadrature channel (Quadrature: Q) are respectively input to the DC offset canceller 100, the first-phase offset canceller 100-1 performs an in-phase channel. The direct current offset with respect to the signal I is removed and the second direct current offset remover 100-2 removes the direct current offset with respect to the signal Q of the rectangular weft channel.

If this is the DC offset cancellation signal input to the feed forward filter 102, a first finite impulse response filter (102-1: C _I) and a second finite impulse response filter (102-2: C _I) in the above The input signal corresponding to the phase in which the DC offset is removed and the coefficient updated signal are input to output the filtered signal, and the third finite shock response filter 102-3: C _Q and the fourth finite shock response filter 102 are output. 4: the C _Q) in the above, and a direct current offset removal is accepted that the quadrature input an input signal and a coefficient update signal to output a filtered signal, a subtracter (102-5), wherein the first finite impulse response filter ( 102-1 subtracts the output signal of the third finite shock response filter 102-3, and the adder 102-6 subtracts the output signal of the second finite shock response filter 102-2. The output signal of the fourth finite shock response filter 102-4 is added.

On the other hand, when the signal selected from the discrimination signal and the training signal and the signal updated by the coefficient are input to the feedback filter unit 104, the first finite shock response filter 104-1: D _I and the second finite shock response filter 104-. 2: D _I ) receives a signal selected from the discrimination signal and the training signal for the in-phase (I) channel and a signal updated by a coefficient and outputs a filtered signal, and outputs a filtered signal for the third finite shock response filter (104-3: D _Q). ) And the fourth finite shock response filter 104-4 (D _Q ) receive the discrimination signal and the coefficient updated signal for the quadrature phase (Q) channel, and output the filtered signal. The subtractor 104-5 outputs the filtered signal. The output signal of the third finite shock response filter 104-3 is subtracted from the output signal of the first finite shock response filter 104-1, and the second finite shock response filter 104 is added by the adder 104-6. The output signal of -2) and the output signal of the fourth finite impact response filter 104-4 are added.

When the filtering signal from the feedforward filter unit 102 and the filtering signal from the feedback filter unit 104 are input to the subtractor 106, the first subtractor 106-1 feeds the feedforward of the in-phase channel. When the NTSC signal is inputted by subtracting the feedback filtering signal of the in-phase channel from the filtering signal, and the NTSC signal is input, the NTSC signal equalized by the first subtractor 106-1 is output and the second subtractor 106-2. ) Subtracts the feedback filtering signal of the quadrature phase channel from the feedforward filtering signal of the quadrature phase channel and outputs a difference signal.

When the difference signal and the automatic gain control signal are input to the multiplier 108, the first multiplier 108-1 multiplies the difference signal for the phase-phase channel and the automatic gain control signal, and the second multiplier 108-2. ) Multiplies the difference signal and the automatic gain control signal for the quadrature phase channel.

The delay unit 110 delays the signal of the multiplied in-phase channel. If the VSB signal is input to the equalizer, the multiplexer 113-1 of the band pass filter unit 113 performs the first multiplier 108. -1) output signal is selected and the signal of the selected VSB in-phase channel is converted from the digital filter 113-2 to the signal of the quadrature phase channel and the coefficient of the digital filter 113-2 is converted into the coefficient storage unit 113-. 3) are stored.

The present invention relates to a device for demodulating NTSC color signals. When the NTSC signal is input, the present invention relates to a device for demodulating NTSC color signals. When the NTSC signal is input to the equalizer, the multiplexer 113-1 in the band pass filter 113 provides the first subtractor ( 106-1) selects the equalized NTSC output signal, and the selected NTSC output signal is subjected to band pass filtering in the digital filter 113-2, and the coefficient of the digital filter 113-2 is converted into the coefficient storage unit 113-. 3) are stored.

Here, the digital filter 113-2 is used as a band pass filter to separate the luminance signal and the color signal since the digital filter 113-2 is not used to convert the in-phase channel signal to the quadrature phase channel signal when the NTSC signal is input.

The first multiplexer 115 selects the band pass filtered NTSC signal from the band pass filter 113 and outputs a color signal. The second multiplexer 117 outputs the multiplied in-phase channel signal and the delay signal and Although the NTSC color signal is input, in the present invention, since the NTSC signal is input to the equalizer, the NTSC color signal is selected by the second multiplexer 117.

The subtractor 119 receives the color signal selected by the first multiplexer 115 and the signal output from the second multiplexer 117, and subtracts the two signals to output a luminance signal.

When the color signal selected by the first multiplexer 115 and the signal output from the second multiplexer 117 are input to the complex multiplier 121, the first multiplier 121-1 selects the color signal selected by the second multiplexer 117. Multiply the signal for the in-phase channel by the cosine signal from the digital phase-locked loop 132, and in the second multiplier 121-2, the signal for the quadrature phase channel selected by the first multiplexer 115 and the digital phase-locked signal. The sinusoidal signal from the loop 132 is multiplied, and the third multiplier 121-3 multiplies the signal for the in-phase channel selected by the second multiplexer 117 with the sinusoidal signal from the digital phase locked loop 132. In the fourth multiplier 121-4, the signal for the quadrature phase channel selected by the first multiplexer 115 and the cosine signal from the digital phase-locked loop 132 are multiplied. In the first adder 121-5, Output of the first multiplier 121-1 A sum signal and an output signal of the second multiplier 121-2 are added to output a signal of an NTSC in-phase channel I, which is a color difference signal, and the second adder 121-6 generates the third multiplier 121-3. ) And the output signal of the fourth multiplier 121-4 are summed to output a signal of the NTSC quadrature channel Q, which is a color difference signal.

In this case, the digital phase locked loop 132 not only outputs a sine wave and a cosine wave to each of the multipliers 121-1 to 121-4 of the complex multiplier 121 to remove frequency and phase errors, but also gains gain. A gain control signal is output to the multiplier 108 for adjustment.

After all, the complex multiplier 121 and the digital phase locked loop 132 are used to input an NTSC signal using a derotator used to remove frequency and phase errors during QAM and VSB signal input. It will demodulate the NTSC color signal.

The third multiplexer 122 selects one signal from an in-phase signal from the complex multiplier 121 and a difference signal from the subtractor 106.

The signal discrimination unit 124 receives a signal for the in-phase channel selected by the third multiplexer 122 and a signal for the quadrature phase channel output from the complex multiplier 121, and outputs a discrimination signal. The multiplexer 128 selects one signal from the determination signal and the training signal generated by the training signal generator 126 and outputs the selection signal to the feedback filter unit 104.

The tap coefficient calculator 130 inputs an output signal of the complex multiplier 121, a training signal, a signal selected by the fourth multiplexer 128, and a discrimination signal for a quadrature phase signal of the signal discriminator 124. The tap coefficient is calculated, and then the calculated tap coefficient is output to the feedforward filter unit 102 and the feedback filter unit 104.

When the output signal of the complex multiplier 21 is input to the digital phase lock loop 132, the error detector 132-1 outputs an output signal for the in-phase channel from the complex multiplier 121 and a quadrature phase channel. The phase difference is detected by receiving an output signal for the signal, and the accumulator 132-2 adjusts and accumulates the gain of the detected phase error. 132-2 receives the output signal and outputs a sine signal and a cosine signal, and the accumulation limiter 132-4 receives the generated cosine signal and outputs a gain control signal.

As described above, according to the present invention, a color burst synchronization circuit is demodulated by demodulating an NTSC color signal upon inputting an NTSC signal using a derotator in an equalizer used to remove frequency and phase errors when inputting a QAM signal and a VSB signal. Since the color signal demodulation circuit does not need to be provided separately, the hardware is simplified and the cost is reduced.

Claims (4)

Subtraction consisting of a first subtractor 106-1 and a second subtractor 106-2 which subtracts the filtering signal from the feedforward filter unit 102 and the filtering signal from the feedback filter unit 104 to output the difference signal. A multiplier 108 comprising a first multiplier 108-1 and a second multiplier 108-2 for multiplying the difference signal and the automatic gain control signal, and the first multiplier 108-1. In a television equipped with an equalizer for equalizing all NTSC, VSB, and QAM signals configured to include a delay unit 110 for delaying a multiplication signal from the first subtractor 106-1 when an NTSC signal is input. A band pass filter 113 for receiving the NTSC output signal from the band pass filtering unit; A first multiplexer 115 for selecting a band pass filtered NTSC signal from the band pass filter 113 and outputting a color signal; A second multiplexer (117) for selecting a color signal from the first multiplexer (115); A complex multiplier (121) configured to receive a signal selected by the first multiplexer (115) and a signal selected by the second multiplexer (117), correct a frequency and a phase error, and output a color difference signal; And a digital phase locked loop 132 that receives the output signal of the complex multiplier 121, outputs a sine signal and a cosine signal to remove a phase error, and outputs a control signal to adjust a gain. NTSC color signal demodulation device using an equalizer. The multiplexer 113-1 of claim 1, wherein the band pass filter 113 selects an NTSC output signal from the first subtractor 106-1 for band pass filtering when an NTSC signal is input. ; A digital filter (113-2) for bandpass filtering the selected NTSC signal; And a coefficient storage unit (113-3) for storing the coefficients of the digital filter (113-2). 2. The apparatus of claim 1, wherein the complex multiplier (121) comprises: a first multiplier (121-1) for multiplying a signal and a cosine signal for an in-phase channel selected by the second multiplexer (117); A second multiplier (121-2) for multiplying a signal and a sinusoidal signal for a quadrature phase channel selected by the first multiplexer (115); A third multiplier (121-3) for multiplying the signal for the in-phase channel selected by the second multiplexer (117) and the sinusoidal signal; A fourth multiplier (121-4) for multiplying the signal and the cosine signal for the quadrature phase channel selected by the first multiplexer (115); A first adder (121-5) for summing the output signal of the first multiplier (121-1) and the output signal of the second multiplier (121-2); And a second adder (121-6) for summing the output signal of the third multiplier (121-3) and the output signal of the fourth multiplier (121-4). Demodulation device. The error detection unit of claim 1, wherein the digital phase lock loop 132 receives an output signal for an in-phase channel and an output signal for a quadrature phase channel from the complex multiplier 121 to detect a phase difference ( 132-1); An accumulator 132-2 for adjusting and accumulating the gain of the detected phase error; A sine and cosine signal generator 132-3 which receives the output signal of the accumulator 132-2 and outputs a sine signal and a cosine signal; And a cumulative limiting unit (132-4) which receives the generated cosine signal and outputs a gain control signal.