KR0180213B1 - Method of data verification in semiconductor test - Google Patents

Abstract

According to the present invention, after determining a test item for verification, a plurality of sample chips are selected one by one from the top, bottom, left, right, and center portions of the wafer, and the sample chip selection step of dividing by X and Y coordinates and the sample chip selection. A calculation step of repeating at least 30 to 60 times of one of the plurality of chips selected in the step to calculate a ratio (CP) of the average process spread to the spread allowed by the process; and the data calculated in the calculation step A judgment step of determining whether there is a significant difference item using the same, and a step of completing data verification for repeatability if there is no cause of the significant difference item in the determination step. Accurate and reliable data by applying statistical test theory to test data analysis and verification The present invention relates to a method of verifying data in a semiconductor test that can uniformize the yield and the quality of a semiconductor device in a process of manufacturing the semiconductor device by establishing a data verification system.

Description

Data Verification Method in Semiconductor Test

The present invention relates to a data verification method (TEST DATA CORRELATION METHOD) in a semiconductor test.

The DATA CORRELATION refers to a procedure of equalizing data tested under different conditions by a certain standard. The test data is changed by a change in a program and a circuit component in an automated tester, and statistically The test theory was introduced to test data analysis and verification to establish an accurate and reliable data verification system.

Validation of test data in the semiconductor industry has a great effect on yield and quality uniformity, and errors caused by differences in verification methods can lead to poor productivity and poor quality. Has Existing data verification method used the repeatability and yield change before and after the verification of any sample as the basis of data verification, at the judgment of the testing operator.

Such a method is likely to make small errors, interspersed with factors that are difficult to require accuracy of judgment. Since these problems can adversely affect productivity, it is very important to rationalize the data verification procedure. Therefore, it is necessary to analyze the relevant parameters for the establishment of data verification procedures.

On the other hand, the present invention performs the repeatability verification through the F-test of the test theory, the verification of the equality of the mean value through the t-test, and the yield change verification with or without the change within 3% that is the result of applying the statistics considering the significance level. Its purpose is to provide a method for verifying significant differences in yield changes.

In order to achieve the above object, the present invention, after determining a test item for verification, selects a plurality of sample chips one by one from the top, bottom, left, right, and center portions on the wafer, and selects a sample chip divided by X and Y coordinates. A step of calculating a ratio (CP) of an average value and an actual process spread with respect to the dispersion allowed by the process by repeating at least 30-60 tests on one of the plurality of chips selected in the sample chip selecting step; And a determination step of determining whether there is a significant difference item using the data calculated in the calculation step, and a step of completing data verification of repeatability if there is no cause of the significant difference item in the determination step.

1 is a flowchart illustrating a data verification method in a semiconductor test according to the present invention.

2 is a table showing repeatability data measured by the present invention.

3 is a table showing the repeatability verification according to the present invention.

4 is an identity verification table of average values measured by the present invention.

Hereinafter, the present invention will be described in more detail with reference to the illustrated drawings.

The Cp cited in the present invention represents the ratio of the actual process spread to the spread allowed by the process. When the Cp value is large, the process is stable. Applying this to the repeated test shows that the test data is measured consistently as the value of Cp (r) increases, so that the test result is stable.

In addition, Cpk is a ratio indicating the degree of bias in which the distribution of quality characteristics does not coincide with the median values of both standards. The larger the absolute value of Cpk, the closer the center value of Spec is. Therefore, the Cpk (run) of the run distribution is a measure of how much margin of 3 sigma (run) is. Therefore, the larger the margin of 3 sigma (run), the more stable the process. As a result, we can examine the relationship with data verification. Based on this theory, the relationship between Cp (r), Cp (run) and Cpk (run) of Run distribution and data verification is established to stabilize test data verification.

If data verification is required, data between test jig, probe card, tester, and wafer / package is different, and data verification between testers is to verify each of the same products. Determine important test items.

After determining the test items for verification as in step S1 of FIG. 1, proceed to step S2. (1) To verify the wafers, a total of five sample chips are selected, one chip from the top, bottom, left, right, and center portions of the wafer. At the same time, it is indicated by X and Y coordinates. And, (2) the verification of the package is selected by selecting five sample packages in a certain lot and then displaying the number to distinguish.

After 50 repeated tests (100p Test) for one of the five samples selected in step S2, the average value (M), Cp, σ are obtained in step S3 and used as data for data analysis before and after verification. .

By comparing the Cp of the repeatability data before and after verification using the data obtained in step S3 as in step S4, each Cp should be 5.0 or more, and the relationship of Cp is verified by performing the following verification to verify the data for repeatability. Completes.

(1) If Cp1 and Cp2 30, there is no significant difference

(2) If Cp1 Cp2, judge by applying Cp1 x 0.79 Cp2

(3) In the case of Cp1 Cp2, it is determined that there is no significant difference since the repeatability distribution of the verification data is reduced.

Here, Cp1 is reference measurement data Cp, and Cp2 is verification measurement data Cp.

The above equation is obtained from the F-test for the identity of two population variances.

If the population variances (variances of the repeatability data) of the two populations are not the same, cause analysis is performed to satisfy the above judgment.

Data verification for the equality of the mean values before and after the verification is performed after obtaining the verification statistic T (x).

In other words, at the 90% confidence level, the following equation should be satisfied as a criterion that the two population means are equal.

Since we know the test statistic and distribution, we set the critical region (which represents the observed value region of the test statistic that rejects the null hypothesis in statistics) according to the significance level σ, and then the null hypothesis (Ho, 歸 無). 귀: null hypothesis if the value of the test statistic under the Null Hypothesis (the hypothesis that there is no difference or no effect on the mean value of the irregular samples from the same population) is the opposite of the alternative hypothesis (H1) (Ho) is rejected and the null hypothesis (Ho) is adopted if it does not belong If the significance level σ = 0.05 in both tests, the range of statistics not included in the rejection range is -3.4T (X) 3.4 It is

The significance level σ is the magnitude of the probability of rejecting the null hypothesis even though it is correct.The significance level σ = 0.01 indicates that the mean of the two populations is the same at the 99% confidence level, and the confidence in the equality test of the mean value of the data test. The level is 90% applied.

If it is judged that the average of the two populations (the average of the five samples of data) is not the same, the process must be taken after determining the cause by going to step S5.

The procedure for verifying the yield change can be divided into the yield change verification for the wafer and the yield change verification for the package. The repeatability measurement data, the repeatability verification table, and the equality verification table of the average values are shown in FIGS. 2, 3, and 4. .

(1) Verification of yield change for wafer

When verifying the change in yield through the wafer test between tests, test the same wafer on the existing tester and the tester for the same wafer, collect bin summary and histogram data of 100 or more samples, and compare and compare mutual bins. Select surrender with difference and establish cause analysis and countermeasure using Histogram Data.

The criterion that there is a significant difference is when the yield difference occurs more than 3%, and when it is less than that, the verification of the yield change is completed.

(2) Verification of yield change for package

When verifying the change in yield through the package test between testers, test the 200 test samples of the same package in the existing tester and the tester, collect the bin summary and more than 100 Histogram data, and compare the mutual bin summary. Select items with significant differences and establish cause analysis and countermeasure using Histogram Data. The criteria for determining that there is a significant difference are the same as those of the wafer.

According to the present invention described above, the statistical test theory is introduced into the test data analysis and verification that the test data changes due to the change of the program and the circuit components in the automated tester, thereby establishing an accurate and reliable data verification system. There is an effect that the production yield in the process of manufacturing the device and the quality of the semiconductor device can be made uniform.

Claims (1)

A sample chip selection step of selecting a plurality of sample chips one by one from the top, bottom, left, right, and center portions on the wafer after determining the test items for verification, and dividing them by X and Y coordinates; A calculation step of repeatedly testing at least 30 to 60 times one of a plurality of chips selected in the sample chip selection step to calculate a ratio (CP) of an actual process spread to an average value and a dispersion allowed by the process; Using the data calculated in the above calculation step, it is determined that (1) there is no significant difference if Cp1 and Cp2 30, (2) if Cp1 Cp2 is determined by applying Cp1 x 0.79 Cp2, and (3) if Cp1 Cp2 (Cp1: reference measurement data, Cp, Cp2: verification measurement data Cp) Since the repeatability distribution of the verification data is reduced, the absolute value of the difference between the repeatability data before and after the verification of the repeatability data, which is determined to have no significant difference, After obtaining the verification statistic T (X), T (X) is Based on the criteria that the two population means are considered equal at the 90% confidence level, the equation is -3.4T (X) 3.4, A determination step of determining the cause of the significant difference item by obtaining the absolute values of the difference of the average values after the identity verification, which should satisfy? And if the cause of the significant difference item is not found in the determination step, verifying data for repeatability.