KR0178249B1 - Tone transmission apparatus of switching system - Google Patents

Abstract

The present invention relates to an apparatus for causing a switch to hardwareally control an interruption ratio of an audible tone to be transmitted to a subscriber to inform the subscriber of the progress of a call. In the prior art, since the audio tone control ratio control of the all-electronic exchanger is executed in software through a CPU program such as a digital signal processor (DSP) or a microcontroller, the cost increases. have. Therefore, in the present invention, a specific tone is transmitted to the subscriber by controlling the interruption ratio of the tone in hardware without using an expensive CPU. Therefore, the cost can be reduced.

Description

Tone transmitting device of exchange

1 is a block diagram showing an embodiment of a tone transmitting apparatus of an electronic switching system according to the prior art;

2 is a block diagram showing an embodiment of a tone transmitting apparatus of an exchange according to the present invention;

FIG. 3 is a schematic diagram showing an embodiment of an audio tone control ratio control data format for each channel according to FIG. 2; FIG.

* Explanation of symbols for main parts of the drawings

20, 25: 1st, 2nd memory element 21, 26: 1st, 2nd counter

22, 29: 1st, 2nd bottle / series conversion circuit 27, 28, 24: 1st, 2nd, 3rd buffer

The present invention relates to an apparatus for transmitting a tone of an exchange, and more particularly, to an apparatus for allowing the exchange to control the interruption ratio of an audible tone to be transmitted to a subscriber in order to inform the subscriber of the progress of a call.

1 is a block diagram showing an embodiment of a tone transmitting apparatus of an all-electronic exchange according to the prior art, and includes a storage element 11, a counter 12, a plurality of buffers (first to sixteenth buffers), and a TS. (Time Slot) A control circuit 13, a CPU (Central Processing Unit) 14, and a parallel / vertical conversion circuit 15 are included.

In the figure, first, 10 or 16 kinds of audible tones that inform the general subscriber of the call progress status in the electronic switchboard are usually used.

The memory element 11 stores in advance pulse code modulation (PCM) data corresponding to a plurality of audible tones, and addresses the high address and the low address separately. At this time, the counter 12 addresses the row address of the memory element 11. The TS control circuit 13 also controls a plurality of buffers (first buffer to sixteenth buffer) to address the high address of the memory element 11.

The CPU 14 controls a plurality of buffers (first buffer to sixteenth buffer) for each TS so that the plurality of buffers (first buffer to sixteenth buffer) address the high address of the memory element 11. At this time, the pulse code modulation data stored in the memory element 11 have the same frequency and magnitude. That is, the same data is used in the memory element 11, but only the interruption ratio controlled by the CPU 14 may be programmed differently in order to obtain different audio tones.

The parallel / serial conversion circuit 15 converts the audible tone pulse code modulation data, which are divided into a plurality of TSs and output in parallel by the high addressing and the low addressing of the memory element 11, to be serially outputted.

At this time, the control of the interruption ratio causes the storage element 11 to store null data (usually FFH) having no content in advance. Thereafter, the CPU 14 controls the speed and stage of the tone by alternately addressing the tone area and the null data area for a desired time.

The CPU 14 uses an algorithm that repeats a control routine in which periodic interruptions occur every predetermined time for tone transmission and interruption ratio control.

However, in the conventional technology, the cost is increased because the audible tone control ratio of the electronic switch is executed in software through a CPU program such as a digital signal processor (DSP) or a micro controller. There is a flaw done.

SUMMARY OF THE INVENTION The present invention has been made to solve such drawbacks of the prior art, and provides a tone transmitting apparatus of an exchange which transmits a specific tone to a subscriber by controlling the interruption ratio of the tone in hardware without using an expensive CPU. Its purpose is to.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention for achieving the above object is as follows.

FIG. 2 is a block diagram showing an embodiment of a tone transmitting apparatus of an exchange according to the present invention. The first memory device 20 stores a plurality of pulse code modulated 8-bit audible tone data in time slot order. And pulse-code modulated 8-bit audible tone data of the first counter 21 for addressing the first memory element 20 and the first memory element 20 output in parallel by the addressing of the first counter 21. Is applied to convert the first bottle / series conversion circuit 22 and output in series, and the third buffer for outputting the output of the first bottle / series conversion circuit 22 to the outside under the control of the control ratio control signal ( 24, the second memory element 25 storing the interruption ratio control data, the second counter 26 for addressing the second memory element 25, and the addressing of the second counter 26. The bit rate control data of the second memory device 25 outputted in parallel bits is divided by 8 bits, respectively. The parallel outputs of the first and second buffers 27 and 28 for inputting / outputting the columns and the parallel outputs of the first and second buffers 27 and 28 are serially converted in accordance with the time slots and intermittent to the third buffer 24. And a second bottle / serial conversion circuit 29 which is applied as a control signal.

In the figure, the first storage element 20 stores a plurality of pulse code modulated 8-bit audible tone data in time slot order. At this time, 160 bytes of audible tone data and 96 bytes of null data are stored for each type.

Next, the first counter 21 addresses the first memory element 20. At this time, the row address of the first memory element 20 is assigned A0 to A7 and counted every 1FS, that is, 125usec. Thereafter, the row address of the first memory element 20 is configured to be reset when counted up to 160. Further, the high address of the first memory element 20 is configured to be counted for each time slot, i.e., 3.90625usec, from 0 to 31 by allocating A8 to A12.

The first bottle / serial conversion circuit 22 receives an 8-bit serial by applying pulse-code modulated 8-bit audible tone data of the first memory device 20 that is output 8-bit in parallel by the addressing of the first counter 21. Convert to and print it out. Next, the third buffer 24 outputs the output of the first bottle / serial conversion circuit 22 to the outside by controlling the control ratio control signal, that is, the corresponding audible tone is turned on / off according to the standard time for each time slot. Is output to the outside.

In view of the generation of the interruption ratio control signal, firstly, the second memory element 25 stores the interruption ratio control data. At this time, the second memory element 25 uses an element of several n bits or more of audible tones. In addition, since the number of audible tones is usually 16, 64 Kbyte x 16-bit memory elements are used.

In addition, intermittent ratio data is data of one time slot per bit, and 1 is on, and 0 is off. Therefore, in consideration of the interruption ratio specification of all kinds of tones, data of 1 and 0 are input to each of the time slots for a desired time in the second storage element 25.

Such control ratio control data is generated through a separate program, and the total number of data is made as follows.

Assuming the maximum common divisor of all the tones of the tones and the duration of time is X, the sum of the tones of the tones and the duration of each tone, i.e. 1 cycle, is divided by X to find all the tones. This minimum common multiple is the total number of data, and the maximum common divisor obtained above is the time counted by the second counter 26. The intermittent ratio data is sequentially addressed through the second counter 26, and after 16 kinds of intermittent ratio data (on 1 when ON and 0 when OFF) as shown in FIG. Reset and repeat operation.

The first and second buffers 27 and 28 divide the intermittent ratio control data of the second memory device 25 outputted in parallel by 16 bits by the addressing of the second counter 26, and divide the control ratio data by 8 bits in parallel to each other. do. Next, the second bottle / serial conversion circuit 29 converts the parallel output of the first and second buffers 27 and 28 in series according to the time slots, and applies the control ratio control signal to the third buffer 24. do.

As described above, the present invention allows to control the interruption ratio of the tone in hardware without using an expensive CPU and transmit a specific tone to the subscriber. Therefore, the cost can be reduced.

Claims (1)

A first memory element 20 for storing a plurality of audio tone data in time slot order; A first counter (21) for addressing the first memory element (20); A first bottle / serial conversion circuit (22) which receives audible tone data of the first memory element (20) output in parallel by addressing the first counter (21), converts it in series, and outputs the serial tone; A third buffer 24 for outputting the output of the first bottle / direct conversion circuit 22 to the outside by the intermittent ratio control signal; A second memory element 25 for storing interruption ratio control data; A second counter (26) for addressing said second memory element (25); First and second buffers 27 and 28 for inputting / outputting the control ratio of the second storage element 25 parallelly outputted in parallel by addressing the second counter 26 in parallel; A second parallel / serial conversion circuit 29 for converting the parallel outputs of the first and second buffers 27 and 28 serially in time slots and applying the intermittent ratio control signal to the third buffer 24. Tone transmitting device of exchange.