KR0176613B1 - Apparatus for communication for fault detecting change of transmission data - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication apparatus capable of detecting abnormality of transmission data for continuously monitoring an output level of transmission data to initialize a transmission system and stopping transmission of an error signal when an abnormality occurs. A microprocessor having a port and a serial data receiving port for receiving data; And detecting a data level output through the transmission port of the microprocessor for a predetermined time, initializing the processor to the micro when an abnormal level is detected for a predetermined time, and adjusting a predetermined signal for driving the modulator / demodulator. And a transmission data abnormality detection unit for preventing the abnormal modulation signal from being output. Therefore, as described above, the apparatus for detecting abnormality of the transmission data according to the present invention detects an abnormal state of the transmission data in hardware, resets each circuit part when an error occurs, and prevents the abnormal signal from being output to the data line. Communication between other communication devices in a state can be performed to increase the reliability of the communication and have the effect of convenience in maintenance.

Description

Communication device capable of detecting abnormality of transmission data.

The present invention relates to a communication apparatus capable of detecting an abnormality of transmission data. More particularly, the present invention relates to a communication apparatus capable of continuously monitoring an output level of transmission data to initialize a transmission system when an error occurs and to stop transmission of an abnormal signal. It relates to a communication device capable of detecting the presence.

1 is a view showing the configuration of a conventional communication apparatus for transmitting / receiving data. Reference numerals 100, 120, and 130 denote communication apparatuses for transmitting / receiving data. Data is transmitted / received via data lines. Reference numerals 120 and 130 denote communication devices having the same internal configuration as the reference numeral 100. Here, each communication device includes a microprocessor 10 and a modulator / demodulator 12 for demodulating data for transmitting data output from the microprocessor 10 to another communication device connected to the data line 110. do.

The microprocessor 10 of each communication device has a serial data transmission port TXD for transmitting data and a serial data reception port RXD for receiving data.

In the conventional communication apparatus configured as described above, when a plurality of communication devices communicate with each other through a data line, even when a transmission port of a communication device to be transmitted malfunctions due to a defective contact or a short circuit, the data line 110 continues to operate. When the abnormal signal is transmitted, other communication devices connected to the data line 110 may be in a communication incapable state.

SUMMARY OF THE INVENTION The present invention has been made to solve at least some of the above-described problems. The present invention provides a signal for initializing a microprocessor when an abnormality is detected by detecting a presence or absence of an abnormality in transmission at a communication device to be transmitted, It is an object of the present invention to provide a communication device capable of detecting abnormality of transmission data for preventing output.

1 is a view showing the configuration of a communication device for transmitting and receiving data in the related art.

2 is a diagram illustrating a configuration of a communication device capable of detecting an abnormality of transmission data according to the present invention.

3 is a diagram illustrating a detailed configuration of a transmission data abnormality detection unit illustrated in FIG. 2.

4 is a view showing a preferred embodiment according to the present invention.

5 is a timing diagram showing an operating waveform according to the present invention.

A communication apparatus capable of detecting abnormality of transmission data between communication devices including a modulation / demodulation unit connected to a data line and demodulating / demodulating predetermined data transmitted / received according to the present invention achieves the above object. A microprocessor having a serial data transmission port and a serial data reception port for receiving data; And detecting a data level output through the transmission port of the microprocessor for a predetermined time, initializing the processor to the micro when an abnormal level is detected for a predetermined time, and adjusting a predetermined signal for driving the modulator / demodulator. Therefore, it is preferable to include a transmission data abnormality detection unit for preventing the abnormal modulation signal is output.

In the present invention, the abnormality detection unit of the transmission data detection unit for generating a clock signal; A first logic sum gate configured to perform a logical sum of the frequency output from the clock generator and a first reset signal; A second logic sum gate configured to input and OR the frequency output from the first logic sum gate and data output from the microprocessor; A counter for counting data output through a transmission port to the microprocessor using a frequency output from the second logical sum gate as a clock signal; A level detector which detects a predetermined level of the count signal output from the counter and outputs a signal for initializing the microprocessor when the deactivation signal is detected; It is preferable to include a side / demodulator driving unit for driving the modulation / demodulation unit by inputting the signal output from the microprocessor and the signal output from the level detector.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

2 is a diagram showing the configuration of a communication apparatus capable of detecting abnormality of transmission data according to the present invention, wherein reference numerals 200, 220, and 230 denote communication apparatuses for transmitting / receiving data. Data is transmitted / received through the 210 data line. Reference numerals 220 and 230 denote communication devices having the same internal configuration as reference numeral 200.

Here, each communication device is connected to the microprocessor 20, the transmission data abnormality detection unit 22 and the data line 210 to detect the abnormality of data output through the transmission port TXD of the microprocessor 20. And a demodulation / demodulation unit 12 for demodulating and demodulating transmission data between other connected communication devices.

The microprocessor 10 of each communication device has a serial data transmission port TXD for transmitting data and a serial data reception port RXD for receiving data.

The communication device capable of detecting an abnormality in the transmission data of the present invention configured as described above detects a level of a signal output from the microprocessor 20 for a predetermined time and automatically initializes the microprocessor 20 when an abnormality occurs. The predetermined signal S (t) for providing a signal and driving the modulator / demodulator 12 is adjusted to prevent the abnormal modulation signal from being output to the data line.

3 is a diagram showing a detailed configuration of the transmission data abnormality detection unit 22 shown in FIG. 2, the configuration of which is a frequency output from the clock generator 31 and the clock generator 31 that generate the reference clock signal ( a first logic sum gate 32 for inputting and ORing f1) and a first reset signal, and a frequency f2 output from the first logic sum gate 32 and data output from the microprocessor 20 for logic OR; The counter 34 and the counter 34 outputting the data output from the microprocessor 20 using a frequency signal f3 output from the second logic gate 33 and the second logic gate 33 as a clock signal. When the deactivation signal is detected for a predetermined time by inputting a signal, the level detection unit 35 outputting an initialization signal RESET for initializing the microprocessor 20 and the inversion signal output from the level detection unit 35 are inverted. The input / output signal from the inverter 36 and the microprocessor 20 and the initialization signal RESET f4 output from the level detector 35 are inputted to change / demodulate the drive of the modulator / demodulator 12. It consists of a roughness drive part 37.

4 is a view showing a preferred embodiment according to the present invention,

Reference numeral 420 denotes a clock generator for generating a reference clock signal, and reference numeral 430 denotes a reset signal for initializing the microprocessor 410 when an error occurs in the frequency f1 outputted from the clock generator 430 and transmission data. Denotes a first logical sum gate 430 to be ORed, and reference numeral 440 denotes a frequency f2 output from the first logical sum gate 430 and data output through the data transmission port to the microprocessor 410. To represent the second logical sum gate.

Reference numeral 450 denotes a counter that inputs a frequency f3 output from the second logic gate 440 as a clock signal to count and output data output through the transmission port of the microprocessor 410.

Reference numeral 460 denotes a level detection unit for inputting the count signals Q1 to Q6 output from the counter circuit unit 450 and outputting a reset signal for initializing the microprocessor 410 when a predetermined level is detected. Implement with

Reference numeral 470 denotes an inverter for inverting the reset signal output from the level detector 460, and outputs a signal for resetting another circuit which is a low activation signal.

Reference numeral 480 denotes a modulator / demodulator driver for driving the modulator / demodulator 490 by inputting data output through the transmission port of the microprocessor 410 and a reset signal f4 output from the level detector 460. As shown, it is implemented as a logical sum gate.

Reference numeral 490 denotes a modulator / demodulator that is driven by inputting an output signal f5 of the modulator / demodulator driver 480 and modulates / demodulates the transmit / receive data to a data line.

Looking at the operation of the device shown in Figure 4 configured as described above are as follows.

First, when data is not transmitted from the microprocessor 410 to the data line, since the data output through the transmission port is at the high level, the counter 450 is reset by the input high level so that all outputs are at the low level. Therefore, since the level of data output through the transmission port of the microprocessor 410 is always high level, the output signal f4 of the level detection unit 35 becomes low level, and thus the output signal of the modulation / demodulator driving unit 480. (f5) becomes high. Therefore, since the activation level of the modulator / demodulator 490 is low level, the modulated signal is not output to the data line.

In addition, in the case where the microprocessor 410 normally transmits data, the data output through the transmission port is continuously outputted at a high or low level, and then returned to a high state when data transmission is terminated. In this case, since the stop bit at the high level is periodically displayed, the counter 450 is continuously reset. Therefore, the output of the level detector 450 is kept at a low level, and the transmission data is output as it is to the output signal f5 of the modulation / demodulator driving unit 480.

On the other hand, when a low level is continuously outputted due to a malfunction of the microprocessor 410 or a short circuit of a contact point, a method of detecting an abnormal state will be described below.

When the reference clock signal f1 generated by the clock generator 420 shown in FIG. 4 is 50, the microprocessor 410 is reset by detecting an abnormal state and setting the output of the counter 450 to a high level. The output signal f5 of the modulator / demodulator driver 480 is forced to a high level so that the modulation signal is not output to the data line.

That is, if the output signal f1 of the clock generator 420 has a period of 1 msec (1KHZ), the low level is continuously output for the transmission data for 50 msec. Therefore, the output of the level detector 460 goes high.

5 is a diagram showing the timing of the operation in this case, (A) is a waveform diagram showing a reference clock signal output from the clock generator 420, (B) is the data output through the transmission port of the microprocessor (D) is a waveform diagram showing the level of, where (D) is a waveform diagram in which a high level is generated every one cycle of the reference clock signal, and (E) is another output signal of the counter. (B) is another waveform output signal of the counter, and is a waveform diagram of generating a high level every 32 cycles of the reference clock signal, and (g) from the level detection unit 460. The waveform diagram showing the output signal is a high level only when the signals (C) to (E) are high. That is, referring to FIG. 5, when the reset signal f4 of the microprocessor 410 becomes high, the outputs of the first logic gate 430 and the second logic gate 440 become high, and thus the counter ( Since the clock is not applied to 450, the reset signal f4 of the microprocessor 410 remains high unless the transmission data returns to the high state. Therefore, as shown in (a), the abnormal modulation signal does not exist in the normal state of the data line.

As described above, the apparatus for detecting abnormality of the transmission data according to the present invention detects an abnormal state of the transmission data in hardware, resets each circuit part when an error occurs, and prevents the abnormal signal from being output to the data line. Communication between other communication devices can be performed to increase the reliability of the communication and have convenience in maintenance.

Claims (5)

A communication apparatus capable of detecting an abnormality of transmission data between communication devices including a modulation / demodulation unit connected to a data line and modulating / demodulating predetermined data transmitted / received, A microprocessor having a serial data transmission port for transmitting data and a serial data receiving port for receiving data; And After detecting the data level output through the transmission port of the microprocessor for a predetermined time, when the abnormal level is detected for a predetermined time, the processor is initialized to the micro, and the predetermined signal for driving the modulation / demodulator is adjusted to the data line. And a transmission data abnormality detection unit for preventing abnormal modulation signals from being output. The method of claim 1, wherein the abnormality detection unit of the transmission data A clock generator for generating a clock signal; A first logic sum gate configured to perform a logical sum of the frequency output from the clock generator and a first reset signal; A second logic sum gate configured to input and OR the frequency output from the first logic sum gate and data output from the microprocessor; A counter for counting data output through a transmission port to the microprocessor using a frequency output from the second logical sum gate as a clock signal; A level detector which detects a predetermined level of the count signal output from the counter and outputs a signal for initializing the microprocessor when the deactivation signal is detected; And a modulator / demodulator driver for driving the modulator / demodulator by inputting a signal output from the microprocessor and a signal output from the level detector. The communication device according to claim 2, further comprising an inverter for inverting the signal output from the level detector and supplying it to another circuit. The communication device according to claim 2, wherein the modulation / demodulation driving unit is a logic sum gate. The communication device according to claim 2, wherein the level detection unit is an AND gate.