KR0172506B1 - Method of forming via hole - Google Patents
Method of forming via hole Download PDFInfo
- Publication number
- KR0172506B1 KR0172506B1 KR1019950042468A KR19950042468A KR0172506B1 KR 0172506 B1 KR0172506 B1 KR 0172506B1 KR 1019950042468 A KR1019950042468 A KR 1019950042468A KR 19950042468 A KR19950042468 A KR 19950042468A KR 0172506 B1 KR0172506 B1 KR 0172506B1
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- Prior art keywords
- film
- via hole
- sog
- exposed
- lower metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
Abstract
본 발명은 SOG막을 구비하는 절연막을 금속층간절연막으로 사용하는 반도체 소자의 다층 금속배선 형성에 있어서; 금속층간절연막의 소정 부위를 식각하여 비아 홀을 형성하고, NF3플라즈마를 이용하여 노출된 SOG막의 수분을 제거하고 노출된 하부금속막 상의 자연산화막을 제거하여 비아 홀 내부를 세정하는 것을 특징으로 하는 비아 홀 형성 방법에 관한 것으로, 비아 홀 형성 후 노출된 SOG의 수분을 제거하고, 하부금속막 상의 자연산화막 제거시 SOG의 재증착이 이루어지지 않도록 하여 비아 홀 내부를 깨끗이 세정하여 줌으로써 DLM 구조에서의 상부 금속막과 하부금속막의 접촉 저항을 낮추어 소자의 특성을 향상시키는 효과가 있다.The present invention provides a multilayer metal wiring formation of a semiconductor device using an insulating film having an SOG film as the interlayer insulating film; Etching a predetermined portion of the interlayer dielectric film to form a via hole, removing water from the exposed SOG film using NF 3 plasma, and cleaning the inside of the via hole by removing a natural oxide film on the exposed lower metal film. A method of forming a via hole, which removes moisture from SOG exposed after via hole formation, and cleans the inside of the via hole by preventing redeposition of SOG upon removal of the native oxide film on the lower metal layer. The contact resistance of the upper metal film and the lower metal film is lowered, thereby improving the characteristics of the device.
Description
제1도는 종래기술에 따라 비아 홀이 형성된 상태의 단면도.1 is a cross-sectional view of the via hole is formed according to the prior art.
제2도는 본 발명에 따라 비아 홀이 형성된 상태의 단면도.2 is a cross-sectional view of the via hole is formed in accordance with the present invention.
제3도는 SOG의 분자 결합 구조.3 is the molecular binding structure of SOG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 하부금속막 22 : 제1산화막21: lower metal film 22: first oxide film
23 : SOG 24 : 제2산화막23: SOG 24: the second oxide film
25 : 비아 홀 26 : 경화된 SOG25: via hole 26: hardened SOG
본 발명은 반도체 소자 제조 공정중 비아 홀 형성 방법에 관한 것이다.The present invention relates to a method of forming via holes in a semiconductor device manufacturing process.
반도체 소자의 고집적화를 위한 스케링 다운(Scaling Down)이 가속되면서 DLM(Double Level Metal)을 비롯한 다층 금속배선 공정이 일반화되어가고 있는 추세이다. 이러한 다층 금속배선 구조에서 금속라인 사이의 평탄화 기능을 겸한 절연막 형성 기술은 소자의 수율 및 신뢰성을 결정하는 중요한 인자이다.As scaling down for high integration of semiconductor devices is accelerated, multilayer metallization processes including DLM (Double Level Metal) are becoming more common. In this multi-layered metallization structure, the insulating film formation technique that combines the planarization function between the metal lines is an important factor in determining the yield and reliability of the device.
지금까지의 DLM 체계에서는 낮은 온도에서 증착을 실시하는 PECVD에 의한 층간산화막(SiH4, TEOS계)이 상·하 금속 사이에서의 절연체로 사용되어 왔으나, 금속라인의 피치(pitch)가 더욱 좁아지면서 하부 금속의 라인 피치를 채워 상부 금속 증착을 위한 평탄화 효과를 얻는데는 불충분한 한계를 보이고 있다.In the DLM system up to now, the interlayer oxide film (SiH 4 , TEOS type) by PECVD which deposits at a low temperature has been used as an insulator between the upper and lower metals, but the pitch of the metal line becomes narrower. Filling the line pitch of the bottom metal shows insufficient limits to achieve planarization effects for the top metal deposition.
따라서, 이러한 높은 에스펙트 비(aspect ratio)를 갖는 좁은 피치를 보이드(void)없이 만족스럽게 채워 상부 금속배선을 위한 평탄화 효과를 얻을 수 있는 물질로 SOG(spin on glass)가 사용되고 있다.Accordingly, spin on glass (SOG) has been used as a material capable of satisfactorily filling a narrow pitch having such a high aspect ratio without voids and obtaining a planarization effect for upper metal wiring.
그러나, SOG 고유의 특성만으로는 층간절연의 기능을 하기에는 열악한 절연 특성, 대기 노출시 흡습성 및 필름(film)이 가지고 있는 카본(cabon)의 폴리머 형성 가능성 때문에 한계를 갖고 있어 상·하 금속 사이에서의 절연체로는 산화막/SOG/산화막 구조가 사용되고 있다.However, SOG's inherent properties have limitations due to poor insulation properties, hygroscopicity when exposed to the air, and the possibility of forming a polymer of carbon in the film, which is difficult to function as an interlayer insulation. As the furnace, an oxide film / SOG / oxide film structure is used.
제1도는 이러한 산화막/SOG/산화막 구조를 금속층간절연막으로 사용하여 비아 홀을 형성한 상태의 단면도를 나타내며, 도면에서 11은 하부금속막, 12는 제1산화막, 13은 SOG막, 14는 제2산화막, 15는 비아 홀을 각각 나타낸다.FIG. 1 is a cross-sectional view of a via hole formed using the oxide / SOG / oxide structure as the interlayer insulating film, in which 11 is a lower metal film, 12 is a first oxide film, 13 is an SOG film, and 14 is a first oxide film. The oxide film 15 represents a via hole, respectively.
앞서 설명한 바와 같이 DLM 구조 적용 소자에서 산화막/SOG/산화막을 금속층간절연막으로 사용하여 평탄화를 높인다는 장점이 있는 반면에, 비아 홀 형성 후 비아 홀(15)을 측벽에 노출된 SOG(13)는 물질 특성상 수분(-OH)을 다량 함유하고 있어 비아 홀 내에 상부 금속층이 증착될 경우 금속막이 부식되어 하부금속막(11)과의 접속 불량이 발생하는 문제점이 발생하게 된다.As described above, in the DLM structure-applied device, the planarization is increased by using an oxide film / SOG / oxide film as an interlayer insulating film. On the other hand, after the via hole is formed, the SOG 13 exposing the via hole 15 to the sidewall is formed. Due to the material property, since a large amount of water (-OH) is contained, when the upper metal layer is deposited in the via hole, the metal film may be corroded, resulting in a poor connection with the lower metal film 11.
또한, 상부 금속막 증착 이전에 Ar 가스를 사용한 물리적 방식으로 하부 금속막 표면에 성장해 있는 자연 산화막(native oxide)를 제거시켜 주는 공정을 실시하고 있는데, 이때, 비아 홀 측벽에 노출된 SOG막이 하부금속막 상에 재증착되어(도면부호 16) 하부금속막 표면을 오염시키는 문제점이 발생된다.In addition, prior to the deposition of the upper metal layer, a process of removing a native oxide grown on the surface of the lower metal layer by using an Ar gas is performed. In this case, the SOG film exposed on the sidewall of the via hole is a lower metal. Re-deposition on the membrane (reference numeral 16) creates a problem of contaminating the lower metal film surface.
본 발명은 비아 홀 형성 후 노출된 SOG의 수분을 제거하고, 하부금속막 상의 자연산화막 제거시 SOG의 재증착이 이루어지지 않도록 하는 비아 홀 형성 방법을 제공함을 그 목적으로 한다.An object of the present invention is to provide a method of forming a via hole to remove moisture of SOG exposed after via hole formation and to prevent redeposition of SOG upon removal of the native oxide film on the lower metal layer.
상기 목적을 달성하기 위하여 본 발명의 비아 홀 형성 방법은 SOG막을 구비하는 절연막을 금속층간절연막으로 사용하는 반도체 소자의 다층 금속 배선 형성에 있어서; 금속층간절연막의 소정 부위를 식각하여 비아 홀을 형성하고, NF3플라즈마를 이용하여 노출된 SOG막의 수분을 제거하고 노출된 하부금속막 상의 자연산화막을 제거하여 비아 홀 내부를 세정하는 것을 특징으로 한다.In order to achieve the above object, the method of forming a via hole of the present invention includes forming a multilayer metal wiring of a semiconductor device using an insulating film having an SOG film as the interlayer insulating film; Etching a predetermined portion of the interlayer dielectric film to form a via hole, removing water from the exposed SOG film using NF 3 plasma, and cleaning the inside of the via hole by removing a natural oxide film on the exposed lower metal film. .
이하, 첨부된 도면 제2도 제3도를 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.
본 발명은 비아 홀 형성 후, 상부 금속막이 증착되기 이전에 비아 콘택 홀 측벽에 노출된 SOG를 경화시켜 주는 효과를 주면서 하부 금속막 상의 자연산화막을 제거시키고자 NF3가스를 사용한 프리 하부금속 식각(Pre Metal Etch)을 실시하는 방법이다.The present invention after forming the via-holes, while the effect that by curing the SOG exposed before the upper metal film is deposited in the via contact hole sidewall removing a natural oxide film on the lower metal film and chairs free lower metal etching using NF 3 gas ( Pre Metal Etch).
NF3가스는 플라즈마가 발생된 상태에서 물리적으로 하부금속막 상의 상의 자연산화막을 제거하며, 또한, 이온화된 F 이온은 홀 측벽에 노출된 SOG내로 침투하여 SOG내의 수분(-OH)을 제거시키면서 SOG를 경화시켜준다. 따라서, 비아 홀 내부의 오염을 말끔히 제거함으로써 비아 홀 내에서의 금속부식 등에 의한 접속불량을 방지한다.NF 3 gas physically removes the native oxide film on the lower metal film while the plasma is generated, and ionized F ions penetrate into the SOG exposed on the sidewall of the hole to remove moisture (-OH) in the SOG. Hardens. Therefore, the contamination of the inside of the via hole is eliminated neatly, thereby preventing connection failure due to metal corrosion or the like in the via hole.
제2도는 본 발명에 따라 비아 홀이 형성된 상태의 단면도로서, 도면에서 21은 하부금속막, 22는 제1산화막, 23은 SOG막, 24는 제2산화막, 25는 비아 홀을 나타내며, 도면부호 26은 비아 홀 형성후 NF3플라즈마로 프리 하부금속 식각(Pre Metal Etch)을 실시하므로써 노출된 SOG막이 경화된 것을 나타낸다.2 is a cross-sectional view of a via hole formed according to the present invention, in which 21 is a lower metal film, 22 is a first oxide film, 23 is an SOG film, 24 is a second oxide film, and 25 is a via hole. 26 shows that the exposed SOG film was cured by performing pre-metal etching with NF 3 plasma after via hole formation.
그리고, NF3플라즈마로 프리 하부금속 식각(Pre Metal Etch)시 SOG막은 하부금속막 상에 재증착되지 않는다.In addition, during pre-metal etching with NF 3 plasma, the SOG film is not redeposited on the lower metal film.
제3도는 SOG의 분자 결합 구조를 나타낸다.3 shows the molecular binding structure of SOG.
제3도(a)는 NF3플라즈마로 프리 하부금속 식각(Pre Metal Etch)을 실시하기 이전 상태로서, 수분(-OH)이 다량 함유되어 있음을 알 수 있고, R은 CH3(methyl) 또는 C6H5(phenyl)을 나타낸다.Figure 3 (a) is a state before the pre-metal etching (Pre Metal Etch) to the NF 3 plasma, it can be seen that contains a large amount of water (-OH), R is CH 3 (methyl) or C 6 H 5 (phenyl).
제3도(b)는 NF3플라즈마로 프리 하부금속 식각(Pre Metal Etch)을 실시한 이후의 상태로서, 수분(-OH)이 F로 치환되어 SOG가 수분성분을 잃어버리면서 경화됨을 알 수 있다.FIG. 3 (b) shows a state after performing pre-metal etching with NF 3 plasma, and it can be seen that SOG is cured as the moisture (-OH) is replaced with F and the SOG loses its moisture content. .
이상, 상기 설명한 바와 같은 본 발명은 비아 홀 형성 후 노출된 SOG의 수분을 제거하고, 하부금속막 상의 자연산화막 제거시 SOG의 재증착이 이루어지지 않도록 하여 비아 홀 내부를 깨끗이 세정하여 줌으로써 DLM 구조에서의 상부 금속막과 하부금속막의 접촉 저항을 낮추어 소자의 특성을 향상시키는 효과가 있다.As described above, the present invention removes moisture from SOG exposed after via hole formation, and cleans the inside of the via hole by preventing redeposition of SOG upon removal of the native oxide film on the lower metal layer. Lowering the contact resistance of the upper metal film and the lower metal film of the has the effect of improving the characteristics of the device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950042468A KR0172506B1 (en) | 1995-11-21 | 1995-11-21 | Method of forming via hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950042468A KR0172506B1 (en) | 1995-11-21 | 1995-11-21 | Method of forming via hole |
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| Publication Number | Publication Date |
|---|---|
| KR970030350A KR970030350A (en) | 1997-06-26 |
| KR0172506B1 true KR0172506B1 (en) | 1999-03-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950042468A KR0172506B1 (en) | 1995-11-21 | 1995-11-21 | Method of forming via hole |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100347083B1 (en) * | 1998-10-05 | 2002-08-03 | 닛본 덴기 가부시끼가이샤 | Method of manufacturing a semiconductor device |
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1995
- 1995-11-21 KR KR1019950042468A patent/KR0172506B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100347083B1 (en) * | 1998-10-05 | 2002-08-03 | 닛본 덴기 가부시끼가이샤 | Method of manufacturing a semiconductor device |
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| KR970030350A (en) | 1997-06-26 |
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