KR0172355B1 - Non-volatile semiconductor memory device - Google Patents

Abstract

[Technical field to which the invention described in the claims belongs]

A nonvolatile semiconductor memory device that is temporarily electrically erasable and programmable.

[Technical Challenges to Invent]

The present invention provides a nonvolatile semiconductor memory device and a method of manufacturing the same for minimizing the elongation of the N-type buried diffusion layer which extends in the longitudinal direction to reduce the direction of the cell and increase the lead and program operation speed of the cell.

[Summary of the solution of the invention]

A unit cell having a stacked gate structure stacked with a floating gate and a control gate exists in a region where bit lines and word lines cross each other to form a cell array. A third polysilicon is formed on the top of the cell array in the longitudinal direction of each odd-numbered string, and a third polysilicon is formed on the first field oxide film in the longitudinal direction of the even-numbered string in the lower part of the cell array. A selection transistor section which is applied in the horizontal direction to select a block; A second field oxide apothecary which is elongated in the transverse direction between the first field oxide films and double heat-grown to separate channels; An N-type buried diffusion layer which is extended in the longitudinal direction under the second field oxide film and ion-implanted to form source and drain regions; A contact region located below the odd-numbered string and above the even-numbered string, respectively, to reduce resistance of the N-type buried diffusion layer; A first polysilicon coating a portion of the channel on the channel insulated with the tunnel oxide film and an upper portion of the second field oxide film, a second polysilicon coating a portion of the upper portion of the first polysilicon and an upper portion of the second field oxide film; A floating gate part formed of the first and second polysilicon; An interlayer insulator that coats all the upper portions of the floating gate portion; An upper portion of the interlayer insulator, an upper portion of the first field oxide film not partially coated, and the third polysilicon coated with the upper portion of the first field oxide film to form the selection transistor, respectively.

[Important Uses of the Invention]

It is suitably used for electrically erasing and programmable nonvolatile semiconductor memory devices.

Description

Nonvolatile Semiconductor Memory Device

1 is a plan view of a nonvolatile semiconductor memory device according to the prior art.

2 is a plan view according to another prior art for improving the problems according to the configuration of FIG.

3 shows an equivalent circuit to FIG.

4 is a cross-sectional view of the X-X 'axis of the configuration of FIG.

5A, 5B, 5C, 5D, and 5E show a manufacturing process according to the configuration of FIG.

6 is a plan view of a nonvolatile memory device in accordance with the teachings of the present invention.

7 shows an equivalent circuit of FIG. 6. FIG.

8 (a), (8b), (8c), (8d), and (8e) show a manufacturing process according to the configuration of FIG.

9 is a view showing a reduced extent of the cell area according to the technique of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to flash nonvolatile semiconductor memory devices, and more particularly to a flash type nonvolatile semiconductor memory device having cells of a noah structure and temporarily erasing and programmable data.

In general, a nonvolatile semiconductor memory device has a usability that does not lose stored information even when a power supply is cut off. Thus, many devices controlled by modern computers and microprocessors have been replaced by high density nonvolatile semiconductor memory devices. Moreover, the use of hard disk devices with rotating magnetic disks as secondary memory devices in portable computer or notebook-sized battery powered computer systems occupies a relatively large area, so designers of such systems have high density, There is a great interest in the development of the above-mentioned temporarily electrically erasable and programmable NOR flash nonvolatile semiconductor memory device.

1 shows a plan view of a nonvolatile semiconductor memory device according to the prior art.

Referring to the plan view of FIG. 1, a buried N-type (N +) diffusion layer (hereinafter referred to as an N-type buried diffusion layer) 1 used as a source and drain electrode of a cell under a thick oxide film extends the entire cell array in a vertical direction. The control gate 2 constituting the word line of the cell extends in the horizontal direction.

Under the control gate 2 is a structure in which a floating gate 3 electrically insulated to conserve charge covers a portion of the channel and a portion of the thick oxide film just above the enamel buried diffusion layer 1.

In the above structure, the resistance increases as the elongation length of the N-type buried diffusion layer 1 increases, thereby reducing the read and program speed of the cell, and the capacitance between the substrate 100 increases, thereby charging the bit line. Another problem occurs that slows down the speed of reading the state of the cell.

FIG. 2 is a plan view according to the prior art for improving the above problems according to the configuration of FIG.

Referring to the drawings, in order to reduce the increasing resistance which is a problem of FIG. 1, the elongation length of the N-type buried diffusion layer 1 is minimized by forming the contact hole 4 as shown in the drawing. That is, a method of reducing the resistance by connecting the metal buried buried diffusion layer 1 and the contact hole 4 through the metal wiring 5 to reduce the elongation length of the buried buried diffusion layer 1 is used. However, such a structure encounters a new problem of increasing the area of the horizontal axis according to the formation of the contact hole 4. In particular, when the contact holes 4 which are to be formed in the line of the N-type buried diffusion layer 1 are formed side by side, the minimum distance 6 between the contact hole and the other contact hole, and the minimum between the contact hole and the activation region. In order to secure an area such as the distance 7 and the minimum distance 8 between the active areas, an increase in the area of the memory cell array on the horizontal axis is an inevitable problem.

In addition, although the resistance can be reduced to some extent in the above-described structure, the problem of increased capacitance between the substrates cannot be solved.

FIG. 3 is a diagram showing an equivalent circuit of FIG. 1 and illustrates the schematic operating conditions of the cell with reference to Table 1 below.

Referring to FIG. 3 and Table 1, if cell A is selected, the program operation is applied with 6-7V to bit line B / LK, 12V to word line W / L 3, and bit line B / L. 0V is applied to K-1 to inject channel hot electrons into the floating gate. At this time, since the ground voltage is applied to the unselected word lines W1, W2, W3, W4, and W5, the unselected word line W / L cells connected to the bit line B / LK are connected to the voltage applied to the drain terminal and the word line. Due to the difference in the applied voltage, a problem arises in that charge is lost from the floating gate to the drain terminal. This phenomenon is called a drain interference phenomenon, and the number of interference is affected by N-1 times when the number of cells connected to the bit line B / L is N.

The erase operation is a Fowler-Nordheim tunneling current generated by applying a negative voltage to the selected word line W / L3 and a power supply voltage to the bit line B / LK. The injected electrons of the floating gate 3 are transferred onto the substrate. It occurs when discharged.

In the read operation, 1.5V is applied to the bit line B / LK, a power supply voltage is applied to the selected word line W / L3, and a ground voltage is applied to the unselected word line W / L, so that there is a current according to the potential of the bit line. To determine the state of the cell.

4 is a cross-sectional view taken along the line X-X 'of the configuration of FIG.

Referring to FIG. 4, regions of the N-type buried diffusion layer 1 constituting the source and drain of the cell are spaced apart from each other by the channel under the thick oxide film 9.

The floating gate 3 separated from the channel by the gate oxide film 15 covers a portion of the channel and a portion of the oxide film 9 directly above the region of the N-type buried diffusion layer 1, and the control gate 2 The floating gate 3 covers an area not covered by the floating gate 3.

5A, 5B, 5C, 5D, and 5E show a manufacturing process according to the configuration of FIG.

FIG. 5A sequentially deposits the pad oxide film 15a and the silicon nitride film 11 on the substrate. Subsequently, arsenic ions for forming the N-type buried diffusion layer 1 are injected into the openings formed through the photolithography process using the photosensitive film. Thereafter, the thermally oxidized thick thermal oxide film 9 is grown in a 900 占 폚 or more atmosphere for about 10 hours.

FIG. 5B shows the floating gate 3 after growing the tunnel oxide film 10 to be used as the gate insulating film of the floating gate 3 while the silicon nitride film 11 and the pad oxide film 15a are etched. After the deposition of the polysilicon to be used as a photolithography film 12 using a conventional photolithography process, the floating gate 3 and the tunnel oxide film 10 of the polysilicon is etched to form an opening. During the formation of the tunnel oxide film 10 of the cell during the process, the region of the channel adjacent to the N-type buried oxide layer 1 is affected by the side diffusion due to the side diffusion effect of the ion implanted element to form the N-type buried layer. It grows thicker than the oxide film on the upper channel region. In addition, as the concentration of the element is increased in order to reduce the resistance of the source, the difference in the thickness of the grown oxide film is deepened, resulting in a nonuniformity of cell characteristics. That is, in the program operation of injecting electrons into the floating gate 3 as the channel hot-electron or Fowler-Nordheim current described above according to the above cell characteristics, the nonuniformity of the oxide thickness is nonuniform in the threshold voltage of the cell. Generates. In addition, the above problem is the same when the erasing operation is performed, and in particular, when the erasing is performed using the Fowler-Nordheim current from the floating gate to the source or the drain, the characteristic unevenness of the cell is further intensified.

5C, the interlayer insulating film is simultaneously covered on the floating gate 3 over the channel region which is not covered by the floating gate when the interlayer insulating film 13 is grown by using a thermal oxidation process. Thereafter, the control gate 2 is deposited and the control gate 2, the interlayer insulating film 13, and the floating gate 3 are etched through the photolithography process. Problems in the etching process will be described with reference to FIGS. 5D and 5E.

5d and 5e respectively show a cross-sectional view of the activation region in which the floating gate 3 is covered in FIG. 5c and a cross-sectional view of the activation region in which the floating gate 3 is not covered, respectively. . That is, in the process of etching the control gate 2, the interlayer insulating film 13, and the floating gate 3 by the photolithography process (5d), there is no problem in the control gate 2 (5e). When the interlayer dielectric layer is etched after the polysilicon is etched due to the structure of the polysilicon and the oxide layer 13a to be formed, the oxide layer 13 of the cell is etched to expose the surface of the substrate 100. The exposed portion of the substrate is damaged during etching to form the floating gate, and thus, a problem in that normal bonding characteristics such as leakage current at reverse voltage is not obtained during operation of the cell is generated.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device and a method of manufacturing the same for reducing the resistance and increasing the lead and program operation speed of the cell by minimizing the elongation length of the N-type buried diffusion layer 1 extending in the longitudinal direction. Is in.

Another object of the present invention is to reduce the capacitance between the bit line and the substrate 100 by minimizing the length of the N-type buried diffusion layer 1 extending in the vertical direction to reduce the charging speed of the bit line. And to provide a method for producing the same.

It is still another object of the present invention to minimize drain interference in which charge is lost from the floating gate to the drain terminal due to the difference between the applied voltage of the drain terminal and the word line during the program operation. A memory device and a method of manufacturing the same are provided.

Another object of the present invention is to remove the growth of the region adjacent to the N-type buried oxide film due to the side diffusion effect of the ion implanted element thicker than the oxide layer on the upper channel region without the effect of the side diffusion effect and uniform oxide film thickness The present invention provides a nonvolatile semiconductor memory device and a method of manufacturing the same.

It is still another object of the present invention to provide a nonvolatile semiconductor memory device and a method of manufacturing the same to remove the exposure of the substrate surface generated during the photolithography process.

Another object of the present invention is to provide a nonvolatile semiconductor memory device and a method of manufacturing the same for reducing the area of a cell.

In order to achieve the above objects, in the present invention, a unit cell having a stacked gate structure in which a floating gate and a control gate are stacked is present in each region where a bit line and a word line intersect to form a cell array. Or in a programmable nonvolatile semiconductor memory device; A third polysilicon, which functions as a control gate, is disposed on the upper part of the cell array in the vertical direction for each odd-numbered string, and in the lower part of the cell array, respectively in the longitudinal direction for the even-numbered string. A selection transistor section which is applied in each direction to select a block; A second field oxide film, which is respectively extended in the horizontal direction between the first field oxide films and double heat-grown to separate channels; An en-type buried diffusion layer which is extended in the longitudinal direction under the second field oxide film and implanted with ions to form source and drain regions; A contact region located below the odd-numbered string and above the even-numbered string, respectively, for reducing resistance of the N-type buried diffusion layer; A first polysilicon coating a portion on the channel insulated with the tunnel oxide film and a portion of the upper portion of the second field oxide film, a second polysilicon coating a portion of the upper portion of the first polysilicon and an upper portion of the second field oxide film; A floating gate part formed of the first and second polysilicon; An interlayer insulator covering all upper portions of the floating gate portion; And an upper portion of the interlayer insulator, an upper portion of the second field oxide film not partially coated, and the third polysilicon coated with the upper portion of the first field oxide film to form the selection transistor. A volatile semiconductor memory device is provided.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail. First of all, it should be noted that the same elements in the drawings represent the same reference numerals or reference numerals wherever possible. In the following description, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention.

6 shows a top view of an electrically erasable and programmable nonvolatile memory device in accordance with the techniques of this disclosure.

Referring to FIG. 6, a third polysilicon is formed on the first field oxide film 9a for dividing the blocks in the horizontal axis to extend the selection transistors 14 for selecting the blocks in the horizontal direction above and below the cell array. A second field oxide film is stretched in the horizontal direction between the first field oxide film 9a, and a buried N-type diffusion layer 1 used as a source and drain electrode of the cell is vertically below the second field oxide film. Direction extends, and the control gate 2 constituting the word line of the cell extends in the horizontal direction. Underneath the control gate 2, a floating gate 3 electrically insulated to conserve charge covers a portion of the channel and portions of the source and drain and a portion of the thick oxide film just above the enamel buried diffusion layer 1. It is a structure. At this time, a contact 4 made to reduce the resistance of the bit line is arranged in an intersection arrangement between the first field oxide film 9a.

FIG. 7 is a diagram showing an equivalent circuit of FIG. 6 and shows schematic operating conditions of a cell according to the present invention with reference to Tables 3a and 3b below.

In Table 3a, the erase operation does not apply the program voltage to the selected word line W / L3 and applies 0 V to the unselected word line, under the condition that the cell is operated by the F-N tunnel current in the erase and program operation of the cell. In addition, all bit lines are set to 0 V and power voltages are applied to the selection transistors Sel 1 and 2 so that all bit line voltages are temporarily applied to the drain of each cell, thereby FN tunneling from the bulk or the drain to the floating gate. .

The program operation applies -Vg to the selected W / L3 and 0V to the unselected word line to program the selected cell A. Then, the power supply voltage VCC is applied to the selected B / LK, and 0 V is applied to the non-selected B / L including B / L K + 1 and B / L K-1 so that the bit line voltage is applied to the cell drain and floated. FN tunnels electrons from the gate to the drain.

Table 3b shows another cell operation method wherein the program operation is a channel hot electronic method and the erasing operation is to erase electrons from the floating gate to the drain. In the above program operation, a supply voltage is applied to the selection transistors Sel 1,2, a supply voltage VCC is applied to the selected bit line B / LK, and 18 V is applied to the selection word line to inject hot electrons generated in the channel into the floating gate. It is.

The operation of erasing is to apply the power supply voltage VCC to the drain, and then apply -12V to the selected word line to erase electrons from the floating gate to the drain.

The read operation applies a power supply voltage to the cell selection transistors Sel 1 and 2, applies a power supply voltage to the selected word line, applies a ground voltage to the unselected word line, applies a power supply voltage to the drain of the cell, and applies a ground voltage to the source. Read data as to whether it is off or off.

8 (a), (8b), (8c), (8d), and (8e) sequentially illustrate a manufacturing process according to the configuration of FIG.

First, FIG. 8A is a view showing a common cut plane in the X-X 'or Y-Y' direction of FIG. 6, and a first field for insulating the active regions on the silicon substrate 100 from each other. The pad oxide film 15, the first polysilicon 16, and the silicon nitride film 11 were formed in the form of 300 mV, 100 mV and 1000 mV respectively to form the oxide film and the second field oxide film.

8B is a cross-sectional view taken along the line Y-Y 'of FIG. 6, in which the second field is formed through a conventional photolithography process and an oxidation process in a state where the silicon nitride film 11 for separating the channel is etched. The oxide film 9b is formed. At this time, the second field oxide film 9b is not shown in FIG.

8C is a cross section taken along the line X-X 'of FIG. 6, and the silicon nitride film 11, the first polysilicon 16 and the pad oxide film (used to grow the second field oxide film 9b) After the 15) is etched, the tunnel oxide film 10 of the cell is grown, and the first polysilicon 16 and the nitride film 11 are sequentially deposited thereon. Thereafter, the first polysilicon 16 and the silicon nitride film 11 are partially etched to form the enamel buried diffusion layer 1 by ion implantation, and thereafter, the second field oxide film 9 is grown to about 2000 microseconds. The second field oxide film 9 is shown.

During this process, the tunnel oxide film 10 is formed prior to the conventional ion implantation process for forming the N-type buried diffusion layer 1, and thus, when the tunnel oxide film of the ion-implanted element is formed to form the N-type buried diffusion layer, which has been a problem in the prior art. The nonuniform problem of the tunnel oxide film 10 due to side diffusion can be eliminated.

FIG. 8D is a cross-sectional view taken along the line X-X 'of FIG. 6, and after removing the silicon nitride film 11, the first polysilicon 17 is deposited on the first polysilicon 16 and then source resistance is obtained. In order to control the impurity implantation is performed. When the first polysilicon 16 and the second polysilicon 17 become the polishing gate 3, an interlayer insulating layer 13 is formed on the second polysilicon 17. In the interlayer insulating film 13, a first interlayer oxide film is grown by about 130 kV by a dry thermal oxidation process at 950 ° C, and 150 kW of the interlayer nitride film is deposited. After that, the second interlayer oxide film was grown on the silicon nitride film through a wet thermal oxidation process. In this state, through the photolithography process using the photosensitive film 12, the interlayer insulating film 13, the polishing gate (first and second polysilicon, consisting of 16 and 17; 3) and the tunnel oxide film 10 are sequentially etched. It is a state.

FIG. 8E is a cross section taken along the line X-X 'of FIG. 6, in which a silicon oxide film is formed in a channel region not covered with the following floating gate by a thermal oxidation process, and the control gate 2 is formed. The third polysilicon 14, the interlayer insulating film 13, and the first and second polysilicon 16 and 17 are simultaneously etched through the conventional photolithography process in which the tripolysilicon 14 is deposited. During the etching process, when the third polysilicon 14, the interlayer insulating layer 13, and the first and second polysilicon 16 and 17 are etched, a field oxide film exists in a region where the first and second polysilicon do not exist. Since the oxide film remains after the interlayer insulating layer 13 is etched, the silicon substrate 100 may be protected during the etching of the first and second polysilicon.

9 is a view showing the extent of reducing the cell area according to the prior art and the present invention.

Referring to the drawings, the cell area is reduced compared to the conventional technology when using a 0.6 µm design rule according to the number of field oxide films formed per string and the number of word lines existing in the block. That is, when one field oxide film exists in one string, one field oxide film exists in two strings, and a field oxide film does not exist between strings, respectively. This case is compared with the case where 32 word lines exist in the block.

Therefore, in the conventional cell arrangement, if the number of cells connected to one bit line is N, the conventional drain interference number is N-1 (n: number of transverse directions in the block), but according to the present invention, The capacitance between the diffusion layer and the substrate can also be reduced to conventional 1 / m (m: number of blocks). In more detail, the area of the contact is calculated by dividing the length of the X-axis by the length of the Y-axis. In the conventional case where the length of the X axis is 5 and the length of the Y axis is 1.33, the contact area is 6.65 µm. In the present invention, the length of the X-axis is 3.2 and the length of the Y-axis is 1.425. The contact area of is obtained. Therefore, the contact area reduction of about 68% can be achieved.

As described above, according to the present invention, the resistance of the bit line is reduced, the cell area due to the reduction of the contact hole is reduced, the capacitance between the N-type buried diffusion layer and the substrate, and the effect of minimizing drain interference. There is.

Therefore, according to the present invention as described above, it is possible to solve the problem of the increase of the cell area due to the bit line contact due to the cross arrangement of the contact holes of the bit line, and the bit line by dividing the cell in the longitudinal direction by the block selection transistor. The capacitance between the substrate and the substrate can be reduced and the interference of the drain can be improved. In addition, it is possible to solve the problem of etching the silicon substrate during the control gate patterning by growing the field oxide film between the word line and the word line.

In addition, the tunnel coral film is formed before the N-type buried layer region is formed so that the thickness of the tunnel oxide film grows unevenly by lateral diffusion of ions used to form the N-type buried layer. I can solve it.

Claims (8)

A nonvolatile semiconductor memory device having a unit cell having a stacked gate structure in which floating gates and control gates are stacked to form a cell array in a region where bit lines and word lines cross each other. A third polysilicon, which functions as a control gate, is disposed on the upper part of the first field oxide film which extends in the longitudinal direction for each of the odd-numbered strings and extends in the longitudinal direction for the even-numbered strings in the lower part of the cell array. A selection transistor section which is applied in each direction to select a block; A second field oxide film, which is respectively extended in the horizontal direction between the first field oxide films and double heat-grown to separate channels; An N-type buried diffusion layer which is extended in the longitudinal direction under the second field oxide film and ion-implanted to form source and drain regions; A contact region located below the odd-numbered string and above the even-numbered string, respectively, to reduce resistance of the N-type buried diffusion layer; A first polysilicon coating a portion on the channel insulated with the tunnel oxide film and a portion on the second field oxide film, a second polysilicon coating a portion of the upper portion of the first polysilicon and an upper portion of the second field oxide film; A floating gate part formed of the first and second polysilicon; An interlayer insulator that coats all the upper portions of the floating gate portion; And an upper portion of the interlayer insulator, an upper portion of the second field oxide film not partially coated, and the third polysilicon coated with the upper portion of the first field oxide film to form the selection transistor. Volatile semiconductor memory device. The nonvolatile semiconductor memory device of claim 1, wherein the interlayer insulating material is formed of a silicon oxide film layer, a silicon nitride film layer, and a silicon oxide film layer from above. The nonvolatile semiconductor memory device of claim 1, wherein the first and second field oxide layers are about 6000 mV and about 3000 mV, respectively. The nonvolatile semiconductor memory device of claim 1, wherein the N-type buried diffusion layer is an ion. A manufacturing method of a nonvolatile semiconductor memory device having a floating gate and a control gate on a substrate; Forming a first field oxide film on the substrate to separate the cell array region; A second step of forming a second field oxide film for separating a channel between the upper portion of the substrate and the first field oxide film; After the tunnel oxide film was grown on the channel and the second field oxide film, the first polysilicon and the nitride film were sequentially deposited thereon, and the first polysilicon and the nitride film were partially etched to form a substrate under the second field oxide film. A third step of forming an en-type buried diffusion layer by injecting ions of a conductive type which are semi-reflected; A fourth step of double growing the second field oxide film to a predetermined thickness; A fifth process of removing the nitride film and applying a second polysilicon on the first polysilicon, and applying an interlayer insulator on the first polysilicon; And forming a third polysilicon on the upper surface of the interlayer insulator, the tunnel oxide film and the first and second field oxide films, and performing photolithography. . The method of claim 5, wherein the fifth step; A first step of growing a first interlayer oxide film of about 130 GPa on all exposed surfaces of the first polysilicon and the second polysilicon, and a second step of depositing an interlayer silicon nitride film on the first interlayer oxide film; And a third step of growing the second interlayer oxide film by wet thermal oxidation on the interlayer silicon nitride film. A unit cell having a stacked gate structure in which floating gates and control gates are stacked is present in each of regions where bit lines and word lines cross each other to form a cell array, and temporarily erases or erases a nonvolatile semiconductor memory device that can be electrically erased or programmed. In the program method; In the erase operation, a program voltage is applied to a word line of a selected cell, a ground level voltage is applied to a word line of an unselected cell and a bit line of all cells, and is applied to each gate of a selection transistor for selecting a string. The bit line voltage of the selected cell is applied to a drain by applying a power supply voltage to effect a Paul Nord Nordheim tunneling of electrons from the drain to the floating gate, wherein the program operation is performed by the selected cell to program the selected cell. A negative voltage is applied to the word line of the cell, a ground level voltage is applied to the word line of the unselected cell, a power supply voltage is applied to the bit line of the selected cell, and a ground level voltage is applied to the bit line of the unselected cell. The bit line voltage of the selected cell is applied to the drain to Erasing or programming a non-volatile semiconductor memory device by conducting Paul Nord Nordheim tunneling electrons from the gate to the drain. A unit cell having a stacked gate structure in which a floating gate and a control gate are stacked is present in each of the regions where a bit line and a word line intersect to form a cell array, and may be temporarily erased or erased of a programmable nonvolatile semiconductor memory device. Or in a program method: applying a power supply voltage to a selection transistor for selecting a string, applying a power supply voltage and a program voltage to bit lines and word lines of a selected cell, and applying bit voltages and word lines of a non-selected cell, respectively. A program operation for injecting hot electrons generated in a channel into a floating gate of the selected cell by applying a ground level voltage; A power supply voltage is applied to the selection transistor, a power supply voltage and a ground level voltage are applied to bit lines and word lines of a selected cell, and ground level voltages are applied to bit lines and word lines of a non-selected cell. And an erase operation for tunneling electrons to the Paul Nord Nordheim tunnel from the selected floating gate to the drain of the selected cell.