KR0171987B1 - Gate electrode forming method of semiconductor device - Google Patents
Gate electrode forming method of semiconductor device Download PDFInfo
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- KR0171987B1 KR0171987B1 KR1019950054623A KR19950054623A KR0171987B1 KR 0171987 B1 KR0171987 B1 KR 0171987B1 KR 1019950054623 A KR1019950054623 A KR 1019950054623A KR 19950054623 A KR19950054623 A KR 19950054623A KR 0171987 B1 KR0171987 B1 KR 0171987B1
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- oxide film
- thermal oxide
- gate electrode
- silicon substrate
- etching
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 10
- 150000003624 transition metals Chemical class 0.000 claims abstract description 10
- 238000001020 plasma etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 원은 반도체 소자의 게이트 전극 형성방법을 개시한다. 개시된 본원은 실리콘 기판상에 후막의 열산화막을 형성하고, 소정 부분 식각하여 열산화막 패턴을 형성한다음, 이를 이용하여 실리콘 기판을 고정 깊이만큼 식각하여 요홈을 형성한다. 그리고, 상기 열산화막 패턴을 제거하고, 실리콘 기판상에 게이트 산화막을 형성한다음, 게이트 산화막 상부에 도핑된 폴리실리콘층을 형성한다. 이어서, 도핑된 폴리실리콘층을 요홈의 측벽부에만 존재하도록 식각하고, 이 도핑된 폴리실리콘층을 감싸안도록 전이금속층을 형성하여 게이트 전극을 형성한다.The present application discloses a method for forming a gate electrode of a semiconductor device. The disclosed application forms a thermal oxide film of a thick film on a silicon substrate, forms a thermal oxide film pattern by etching a predetermined portion, and then forms a groove by etching the silicon substrate by a fixed depth using the thermal oxide film pattern. The thermal oxide pattern is removed, a gate oxide film is formed on a silicon substrate, and then a doped polysilicon layer is formed on the gate oxide film. Subsequently, the doped polysilicon layer is etched to exist only in the sidewall portion of the groove, and the transition metal layer is formed to surround the doped polysilicon layer to form a gate electrode.
Description
제1도는 종래의 방법에 따라 형성된 반도체 소자의 게이트 전극을 나타낸 단면도.1 is a cross-sectional view showing a gate electrode of a semiconductor device formed according to a conventional method.
제2도는 (a)내지 (d)는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 공정 순서도.2 is a process flowchart for explaining a method of forming a gate electrode of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12 : 열산화막11 silicon substrate 12 thermal oxide film
13 : 요홈 14 : 게이트 산화막13: groove 14: gate oxide film
15 : 폴리실리콘 16 : 전이 금속막15 polysilicon 16 transition metal film
17 : 열산화막17: thermal oxide film
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로, 보다 구체적으로는 게이트 전극의 전도 특성을 증대시킬 수 있는 반도체 소자의 게이트 전극 형성방법에 관한 것이다.The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly to a method of forming a gate electrode of a semiconductor device capable of increasing the conductive characteristics of the gate electrode.
일반적인 반도체 소자의 구성은, 실리콘 기판상에 박막의 게이트 산화막을 형성하고, 그 상부에 도핑된 폴리실리콘층을 형성한다음, 소정 크기로 식각하여, 소자의 게이트 전극을 형성하였다. 그러나, 이렇게 형성된 게이트 전극은 미세 배선폭을 요구하는 현재의 고집적 대용량 반도체 소자에는 이용되기 어려워 종래에는 제1도에 도시된 바와 같은 구조의 게이트 전극이 제안되었다.In a general semiconductor device, a thin gate oxide film is formed on a silicon substrate, a doped polysilicon layer is formed on the silicon substrate, and then etched to a predetermined size to form a gate electrode of the device. However, the gate electrode thus formed is difficult to be used in the current high-density large-capacity semiconductor device requiring a fine wiring width, and therefore, a gate electrode having a structure as shown in FIG. 1 has been proposed.
이에 대하여 좀더 구체적을 살펴보면, 도시된 바와 같이, 실리콘 기판(1)을 식각 공정에 의하여 소정 깊이의 요홈(1A) 즉, 게이트 전극의 예정 영역을 식각하여 홈을 형성하고, 실리콘 기판 상부에 50 내지 200Å 두께로 게이트 산화막(2)을 형성한다. 그런다음, 상기 게이트 산화막(2) 상부에 게이트 전극용 폴리실리콘(3)을 소정 두께로 형성하고, 그 상부에 전이 금속층(4)을 형성한다음, 상기 전이 금속층 상부에 상기 요홈의 폭보다 큰 마스크 패턴을 형성하고 그의 형태로 식각하여 게이트 전극을 형성한다.In more detail, as illustrated, the grooves 1A having a predetermined depth, that is, predetermined regions of the gate electrodes are etched by the etching process of the silicon substrate 1, and grooves are formed on the silicon substrate 1, and 50 to 50 are formed on the silicon substrate. A gate oxide film 2 is formed to a thickness of 200 microseconds. Then, a gate electrode polysilicon 3 is formed on the gate oxide layer 2 to a predetermined thickness, and a transition metal layer 4 is formed on the gate oxide layer 2, and then the width of the groove is greater than the width of the groove on the transition metal layer. A mask pattern is formed and etched in its form to form a gate electrode.
그러나, 상기의 방법에 따라 형성된 종래의 게이트 전극은, 게이트 전극의 전도성을 개선하기 위하여 도핑된 폴리실리콘층상에 전이 금속층을 증착하여도, 현재의 고집적 소자가 요구하는 게이트 전극의 전도 특성을 구비하기에는 다소 어려움이 존재하였다.However, the conventional gate electrode formed according to the above method, even if the transition metal layer is deposited on the doped polysilicon layer in order to improve the conductivity of the gate electrode, it is not possible to have the conductive characteristics of the gate electrode required by the current high integration device Some difficulties existed.
따라서, 본 발명은 반도체 소자의 게이트 전극의 전도 특성을 개선하여 소자의 질을 향상시킬 수 있는 반도체 소자의 게이트 전극 형성방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of improving the conduction characteristics of the gate electrode of the semiconductor device and improving the quality of the device.
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은 실리콘 기판상에 후막의 열산화막을 형성하는 단계; 상기 열산화막을 소정 부분 식각하여 열산화막 패턴을 형성하는 단계; 상기 열산화막 패턴에 의하여 실리콘 기판을 소정 깊이만큼 식각하여 요홈을 형성하는 단계; 상기 열산화막 패턴을 제거하는 단계; 상기 요홈을 구비한 실리콘 기판상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상부에 도핑된 폴리실리콘층을 형성하는 단계; 상기 도핑된 폴리실리콘층을 요홈의 측벽부에만 존재하도록 식각하는 단계; 상기 식각이 이루어진 도핑된 폴리실리콘층을 감싸안도록 전이 금속층을 형성하여 게이트 전극을 형성하는 단계를 포함한다.In order to achieve the above object of the present invention, the present invention comprises the steps of forming a thermal oxide film of a thick film on a silicon substrate; Etching a portion of the thermal oxide layer to form a thermal oxide pattern; Etching the silicon substrate by a predetermined depth by the thermal oxide film pattern to form grooves; Removing the thermal oxide pattern; Forming a gate oxide film on the silicon substrate having the recess; Forming a doped polysilicon layer on the gate oxide layer; Etching the doped polysilicon layer to exist only in the sidewall portions of the grooves; Forming a gate electrode by forming a transition metal layer to surround the etched doped polysilicon layer.
상기 열산화막의 두께는 1000 내지 3000Å이고, 상기 요홈을 형성하는 단계에서, 실리콘 기판이 식각되는 깊이는 1000 내지 5000Å인 것을 특징으로 한다.The thermal oxide film has a thickness of 1000 to 3000 kPa, and in the forming of the recess, the silicon substrate is etched to have a depth of 1000 to 5000 kPa.
또한, 상기 열산화막 패턴은 HF를 포함한 화학 용액으로 식각하고, 상기 요홈을 형성하기 위한 식각시, 플라즈마 식각에 의하여 요홈의 측벽부가 20 내지 40°정도 경사가 지도록 식각하는 것을 특징으로 한다.In addition, the thermal oxide film pattern is etched with a chemical solution containing HF, and when etching to form the groove, the sidewall portion of the groove is etched to be inclined by about 20 to 40 ° by plasma etching.
그리고, 본 발명의 상기 폴리실리콘층은 면저항이 20 내지 40Ω/정도만큼 도핑하는 것을 특징으로 한다.And, the polysilicon layer of the present invention has a sheet resistance of 20 to 40 mA / It is characterized in that the doping as much as.
이하, 첨부한 도면에 의거하여 본 발명을 자세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 제2도(a)내지 (d)는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 공정 순서도이다.2 (a) to (d) of the accompanying drawings are process flowcharts for explaining a method of forming a gate electrode of a semiconductor device according to the present invention.
먼저, 제2도(a)에 도시된 바와 같이, 실리콘 기판(11)상에 공지된 열산화막 형성방법에 따라 1000 내지 3000Å 두께의 제1 열산화막(12)를 형성한다음, 사진 식각 방식에 따라 요홈 예정 영역이 노출되도록 마스크 패턴(도시되지 않음)을 형성하고, 그 마스크 패턴의 형태로 상기 제1열산화막(12)를 식각한다. 그런다음, 상기 식각이 이루어진 제1열산화막(12)을 식각 마스크로 하여 실리콘 기판(11)을 소정 깊이 약 1000 내지 5000Å로 식각하여 요홈(13)을 형성한다. 이때, 상기 실리콘 기판의 식각은 일반적인 플라즈마 식각가스에 의하여 식각하고, 이 식각방법에 의하여 식각하면, 요홈의 측벽부가 20 내지 40°정도 경사를 갖게 된다. 그리고, 상기 요홈의 식각시, 직접 마스크 패턴에 의하여 기판을 식각하지 않고, 후막의 열산화막을 마스크로 하여 식각하는 것은 기판에 가해지는 스트레스를 최소화하기 위함이다.First, as shown in FIG. 2A, a first thermal oxide film 12 having a thickness of 1000 to 3000 kPa is formed on the silicon substrate 11 according to a known thermal oxide film formation method. Accordingly, a mask pattern (not shown) is formed to expose the recessed area, and the first thermal oxide film 12 is etched in the form of the mask pattern. Then, the recess 13 is formed by etching the silicon substrate 11 at a predetermined depth of about 1000 to 5000 microns using the first thermal oxide film 12 having the etching as an etching mask. In this case, the silicon substrate is etched by a general plasma etching gas, and when etched by this etching method, the sidewall portion of the groove has an inclination of about 20 to 40 °. When etching the grooves, etching the substrate using the thermal oxide film of the thick film as a mask without directly etching the substrate by the mask pattern is to minimize stress applied to the substrate.
그런다음, 제2도(b)에 도시된 바와 같이, 실리콘 기판(11) 상부에 존재하는 제1열산화막(12)을 HF를 포함한 화학 용액으로 제거한 다음, 노출된 기판 표면에 50 내지 150Å정도의 게이트 산화막(14)을 형성한다.Then, as shown in FIG. 2 (b), the first thermal oxide film 12 on the silicon substrate 11 is removed with a chemical solution containing HF, and then, on the exposed substrate surface, about 50 to 150 kPa. A gate oxide film 14 is formed.
이어서, 게이트 산화막(14) 상부에 불순물이 도핑되어 면저항이 20 내지 40Ω/정도인 도핑된 폴리실리콘층(15)을 1000 내지 2000Å 정도 증착한다.Subsequently, an impurity is doped over the gate oxide film 14 so that the sheet resistance is 20 to 40 mA /. The doped polysilicon layer 15 is deposited at about 1000 to 2000 microns.
그런다음, 제2도(c)에 도시된 바와 같이, 상기 도핑이 이루어진 폴리실리콘막(15) 상부에 게이트 전극의 형태를 한정하기 위한 마스크 패턴(도시되지 않음)을 형성하고, 이의 형태로 식각하여 게이트 산화막(14)의 일부를 노출시킨다. 이때 식각이 이루어진 폴리실리콘층은 상기 요홈(13)의 내측벽에 존재하도록 식각함이 바람직하다.Then, as shown in FIG. 2C, a mask pattern (not shown) is formed on the doped polysilicon layer 15 to limit the shape of the gate electrode, and is etched in the form thereof. A portion of the gate oxide film 14 is thereby exposed. At this time, the polysilicon layer etched is preferably etched to exist on the inner wall of the groove (13).
그리고, 제2도(d)에 도시된 바와 같이, 전체 구조 상부에 전이금속막(16)을 약 2000 내지 4000Å정도 형성하고, 상기 전이 금속막은 하부의 폴리실리콘을 감싸안도록 식각하여 예를들어, 상기 요홈부위 하단 및 기판 상면이 노출되도록 마스크 패턴을 형성하여 이의 형태로 식각하므로써 게이트 전극을 형성한다.As shown in FIG. 2 (d), the transition metal film 16 is formed on the entire structure by about 2000 to 4000 μm, and the transition metal film is etched to enclose the lower polysilicon, for example. In addition, a mask pattern is formed to expose the bottom of the recess portion and the upper surface of the substrate to form a gate electrode by etching the mask pattern.
이어서, 상기 결과물이 형성된 웨이퍼를 수증기가 약 3 내지 8% 함유된 수소분위기 하에서, 900 내지 1000℃ 정도의 온도로 10 내지 60분 동안 열성장하여 상기 소오스, 드레인 영역을 보호하기 위한 열산화막 및 게이트 전극간에 소정 크기의 열산화막(17)을 300 내지 800Å정도 형성한다.Subsequently, the resultant formed wafer is thermally grown for 10 to 60 minutes at a temperature of about 900 to 1000 ° C. under a hydrogen atmosphere containing about 3 to 8% of water vapor so as to protect the source and drain regions. A thermal oxide film 17 having a predetermined size is formed between the electrodes at about 300 to 800 kPa.
이상에서 자세히 설명한 바와 같이, 본 발명에 따르면, 반도체 기판상에 돌출부를 형성하여 게이트 전극을 구성하기 위한 폴리실리콘 패턴을 형성하고, 전도 특성을 개선하기 위하여 폴리실리콘 패턴을 감싸안도록 전이 금속층을 형성하므로써, 전도 특성이 우수한 게이트 전극을 형성할 수 있다.As described above in detail, according to the present invention, a polysilicon pattern for forming a gate electrode is formed by forming a protrusion on a semiconductor substrate, and a transition metal layer is formed to surround the polysilicon pattern to improve conduction characteristics. Thus, a gate electrode excellent in conductive characteristics can be formed.
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