KR0171840B1 - Circuit for separating scale factor - Google Patents

Abstract

[Technical field to which the invention described in the claims belong]

A factor separation circuit of a mini disk system.

[Technical Problem to Solve]

Implement a scale factor separation circuit with reduced size.

[Summary of the solution of the invention]

A scale factor separation circuit that separates each scale factor from a series of scale factors mixed in different sizes in a predetermined unit, the storage means for alternately storing a series of scale factors in the first register and the second register And scale factor selection means for sequentially selecting and outputting each scale factor from a series of scale factors stored alternately in the storage means.

[Important Uses of the Invention]

Using only two registers, scale factors constructed and mixed in 8-bit units can be separated into respective scale factors in 6-bit units.

Description

Scale Factor Separation Circuit

1 is a data structure diagram of a typical mini disk system.

2 shows the operation of scale factor separation according to a conventional method.

3 is a block diagram of a scale factor separation circuit according to the present invention.

4 illustrates the operation of scale factor separation in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

30: control unit 32: storage unit

34: Counter 36: Multiplexer

40: RAM

The present invention relates to scale factor separation circuits, and more particularly to scale factor separation circuits having a reduced size.

In general, a scale factor for minimizing audio signals within a predetermined range is used. This scale factor is contained in a typical data format structured as shown in FIG.

1 shows a data format including a scale factor in a mini-disc system, and typically includes information regions 10 and 18 and information on scale factors (block mode, sub information amount, word length, etc.). Scale factor areas 12 and 16 on which SF0 to SF3 are loaded, and audio data area 14 on which audio data are loaded. At this time, the scale factor region 12 and the scale factor region 16 carry the same scale factors SFO to SF3 in order to prevent damage during data transfer.

Data carried in the above structure is configured in 8-bit units, and each scale factor SF0 to SF3 is configured in 6-bit units. At this time, except for an error flag for each of the scale factors SF0 to SF3, the scale factors SF0 to SF3 are structured as shown in the scale factor regions 12 and 16 of FIG. . In other words, initially, a 6-bit scale factor SF0 and a 2-bit scale factor SF1 form one unit, and then a 4-bit scale factor SF1 and a 4-bit scale factor SF2 form one unit. Finally, a 2-bit scale factor (SF2) and a 6-bit scale factor (SF3) form one unit. In this case, although a plurality of scale factors may be used in the mini disk system, it should be noted that only four scale factors SF0 to SF3 are mentioned in the description of the present invention.

In order to bit allocation from the format shown in FIG. 1, scale factors SF0 to SF3 mixed and structured in 8-bit units must be rearranged into respective scale factors SFO to SF3 in 6-bit units. do.

2 is a conceptual diagram illustrating a conventional separation method of separating scale factors from a data format such as FIG. 1 for bit allocation.

Referring to FIGS. 1 and 2, the six-bit scale factor SF0 and the two-bit scale factor SF1 stored in the initial region of the scale factor region 12 are stored in the first register. Next, the 4-bit scale factor SF1 and 4-bit scale factor SF2 stored in the next area of the scale factor area 12 are stored in the second register, and are stored in the last area of the scale factor area 12. The stored 2-bit scale factor SF2 and the 6-bit scale factor SF3 are stored in the third register.

As described above, the scale factors SF0 to SF3 separately stored in the first register, the second register, and the third register are stored in the scale factor region 22 of the RAM 20 by a predetermined extraction operation. That is, first, the six-bit scale factor SF0 stored in the first register is extracted and stored in the scale factor area 22, and then the two-bit scale factor SF1 and first stored in the first register are first stored. The 4-bit scale factor SF1 stored in the 2 registers is extracted and stored in the next area of the scale factor area 22. Then, the 4-bit scale factor SF2 and the second bit stored in the second register are stored. Extracts the 2-bit scale factor SF2 stored in the 3 register, stores it in the next area of the scale factor area 22, and finally extracts the 6-bit scale factor SF3 stored in the third register. In the last area of the scale factor area 22. At this time, when the scale factors SFO to SF3 are stored in the RAM 20, an error flag corresponding to each scale factor is stored in the error flag area 24.

However, there is a problem that the number of registers required in the conventional scale factor separation method is unnecessarily increased. That is, although the number of registers used to separate the four scale factors is three, the same function can be performed using only two registers.

It is therefore an object of the present invention to provide a scale factor separation circuit having a reduced size.

Another object of the present invention is to provide a circuit for separating four scale factors using two registers.

According to the above object, according to the present invention, a scale factor separation circuit according to the present invention that separates each scale factor of 6 bits from a series of scale factors mixed in different sizes within 8 bits, according to the input of a series of scale factors A control unit for generating a first control signal and a second control signal from the generated state signal; A storage unit having a first register and a second register and alternately storing the series of scale factors in the first register and the second register in response to the first control signal and the second control signal; A counter driven in response to the status signal being generated to count a predetermined value; A multiplexer sequentially selects and outputs each scale factor from a series of scale factors alternately stored in the storage unit according to the value counted by the counter.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

3 is a block diagram of a scale factor separation circuit according to the present invention, and FIG. 4 is a diagram showing respective scale factors stored after being separated according to the present invention.

Initially, when scale factors having different sizes within 8 bits are mixed and data is input to the storage unit 32 of FIG. 3 in the format shown in FIG. 1, data is input to the controller 30. The status signal Sc is inputted accordingly. At this time, the status signal Sc has states 0, 1, and 11 sequentially as one bit of 8 bits in the data is input. That is, when the 6-bit scale factor SF0 and the 2-bit scale factor SF1 are input, the status signal Sc represents a state of 0, and the 4-bit scale factor SF1 and the 4-bit scale factor SF2 are input. Is input, the state signal Sc represents the state of 1, and when the 2-bit scale factor SF2 and the 6-bit scale factor SF3 are input, the state signal Sc represents the state of 11.

The controller 30 repeatedly generates the first enable signal EN1, the second enable signal EN2, and the first enable signal EN1 as the state signals Sc change to 0, 1, and 11. Occurs as Then, the storage unit 32 including the first register and the second register alternately stores the input data Data according to the first enable signal EN1 and the second enable signal EN2. The 6-bit scale factor SF0 and the 2-bit scale factor SF1 are stored in the first register, as shown in FIG. 4, and the 4-bit scale factor SF1 and the 4-bit scale factor SF2. Is stored in the second register, and the 2-bit scale factor SF2 and the 6-bit scale factor SF3 are again stored in the first register. In this case, each of the first register and the second register may store 8 bits of data, and thus the storage unit 32 may store 16 bits of data in total.

On the other hand, the counter 34 is initialized in response to the input of the status signal Sc, and counts the values of 0, 1, 2, and 3 sequentially. Accordingly, when the counter 34 counts a value of 0, the multiplexer 36 selects and outputs the scale factor SF0 stored in the first register of the storage unit 32, and the counter 34 sets the value of 1 to 0. When counting the value, the scale factor SF1 stored separately in the first register and the second register of the storage unit 32 is selected and output, and when the counter 34 counts the value of 2, the storage unit ( The scale factor SF2 stored separately in the second register and the first register of 32) is selected and output, and when the counter 34 counts a value of 3, the scale factor SF2 is stored in the first register of the storage unit 32. Select the scale factor (SF3) to be output.

As described above, the scale factors selected by the multiplexer 36 and sequentially output are sequentially separated and stored in the scale factor region 42 of the RAM 40, as shown in FIG. 4 connected to the multiplexer 36. . In this case, error flags corresponding to each of the scale factors SF0 to SF3 are correspondingly stored in the error flag area 44 of the RAM 40.

As described above, even if only two registers are used, the scale factors mixed and structured in 8-bit units can be separated into respective scale factors in 6-bit units.

Claims (4)

A scale factor separation circuit for separating respective scale factors from a series of scale factors mixed in different sizes in a predetermined unit, the scale factor separation circuit comprising: a first register and the second register; Storage means for alternately storing in one register and the second register; and a scale factor selecting means for sequentially selecting and outputting each scale factor from the series of scale factors alternately stored in the storage means. Scale factor separation circuit, characterized in that configured. The first control signal and the second control signal according to claim 1, wherein the series scale factors are alternately stored in the first register and the second register from a state signal generated as the series scale factors are input. And a control signal generating means for generating a control signal. 3. The scale factor of claim 2, further comprising scale factor determining means for determining scale factors for extracting from said series of scale factors stored in said storage means in response to said status signal being generated. Separation circuit. 4. The method of claim 3, wherein the scale factor determining means is a counter that is initialized in response to the state signal being generated and counts a predetermined value, and the value counted in the counter is the series of scale factors stored in the storage means. And a scale factor separating circuit for extracting from the scale factors.