KR0168223B1 - Device and method of signal terminal with four channel assembly, 1 board vs 4 channel of full electronic switching system - Google Patents

Abstract

The present invention relates to a four-channel signal terminal assembly (STAF) apparatus and method for processing four channels per board in an electronic switch, and the existing signal processing assembly (STCA) is one channel per unit Since it is designed to handle 32 channels, 32 sheets are required to process 32 channels, which is inefficient and inefficient. Therefore, the present invention uses 4 channel signal terminal assemblies instead of 4 to solve the conventional problems. The integrated communication controller chip can be used to process four channels per unit, increasing the efficiency four times.

Description

Apparatus and method of a four channel signal terminal assembly (STFA) that handles four channels per board in an electronic exchange

1 is a block diagram of an implementation of the present invention.

2A to 2F are timing diagrams showing the operation of the present invention.

* Explanation of symbols for main parts of the drawings

1: signal controller 2: bidirectional memory device

3: speed matching unit 4: quadrant integrated communication controller

5: Serial communication controller 6: Memory area

7: program area

The present invention relates to an apparatus and method for processing four channels per board in a four-channel signal terminal assembly (STFA) in an electronic switch, and conventionally, one channel per board. Signal Transmit Circuit Assembly (STCA) boards in electronic switchboards are designed to handle four channels per board, increasing the efficiency of Level 2 processing methods in signal processing assembly boards by more than four times. The present invention relates to an apparatus and method for assembling a four-channel signal terminal assembly in an electronic switch.

In general, the level 2 of the seventh signal processing unit of the electronic exchange currently being used is processed in the signal processing assembly. The reason for accommodating one channel per board of the signal processing assembly is that the signal processing assembly This is because the level 2 processing program, which is implemented in firmware format, is implemented to process only one channel on one board.

That is, when data is transmitted from the other station exchange (or location register) in the seventh signaling manner, the signal processing assembly processes the level 2 after the physical connection (level 1) and reports it to the upper level.

At this time, the comparison of the level 2 processed address and the abnormality of data transmission are determined by a cycle redundancy code (CRC) inspection method, and then only the message portion of the predetermined higher data is transmitted. In the event of signal line congestion and failure in the course of operation, the above status is notified to the superior and opposing powers, and appropriate measures are taken from the superior.

This basic method of transmission follows the recommendations of the Comit Consultat if International Telegraphique et Telephonique (CCITT).

Meanwhile, a technology capable of processing four channels with one signal processing assembly has been proposed by the present applicant.

As an example of this technique, if a level matching device is used, even if the signal processing assembly board does not have an error because the processing of the level 1 and the level 2 is performed separately on a separate board using a programmable component, It solves the problem that the eight channels connected to the speed matching device cannot be used, and implements in the board by processing four channels per speed matching device chip, thereby minimizing the interference between signal lines, and thus more integrated. To provide the old board.

In another technology, a signal processing assembly firmware that performs a level 2 signal link function among the message transfer parts (MPTs) of the seventh signal method is designed to process four channels with one signal processing assembly. By providing a firmware that doubles the effect.

However, they are all designed to be performed in the signal processing assembly in the seventh signal level 2 processing used in the all-electronic exchange. Currently, the signal processing assembly has more than one channel of data processing capability, but since it is not easy to process input / output serial data, it processes one channel per board, so four speed matching devices are needed to handle 32 channels. It requires 32 pieces of signal processing assembly (4 (speed matching chip) * 8 (channel) = 32 (length)), and three back-boards are required to mount it, and it is redundant in hardware. There is a problem of inefficiency, instability, and inequality.

Therefore, in order to solve the above-mentioned problems, the present invention is to communicate with one input / output terminal, using four signal controllers, and to report signal processed data to the upper level. Using a high-speed serial integrated Quad Integrated Communications Controller (QICC), it provides a four-channel signal terminal assembly (STFA) that handles four channels on one board, doubling the efficiency.

FIG. 1 is a block diagram showing a four-channel signal terminal assembly of the present invention, in which a seventh level 2 protocol is processed in a seventh signal block connected to the speed matching section 3, and again the speed matching section 3 and the bidirectional memory device ( A signal controller 1 input to 2) and complementary to the bidirectional memory device 2; A bidirectional memory device (2) in which the signal control unit (1) records signal messages subjected to level 2 protocol processing; A speed matching unit (3) for changing the speed by receiving the signal input from the signal controller (1) and physically connecting the switch switch block and the seventh signal block; A quadrant integrated communication controller 4 responsible for message transmission between the signal control unit 1 and the upper level 3, monitoring of the state of the signal control unit 1, and processing of higher level control messages: the quadrant integrated communication controller 4 A serial communication controller 5 for controlling communication with the upper level 3 when the message is transmitted with the upper level 3; It is composed of a memory area 6 which is a basic storage place of data and an address, and a program area 7 in which a program for executing a message recorded in the memory area 6 is stored.

When the power is turned on for the first time, it operates in the reset driver to supply the basic clock. If one signal control unit 1 processes the seventh signal level 2 protocol and is in charge of one signal link, the processed signal transfers a message from the quadrant integrated communication controller 4 to the serial communication controller 5, and serial The communication controller 5 can report to upper level 3 to communicate.

The signal message received from the outside changes the speed in the speed matching device 30, is transmitted to the signal control unit 1 to process the level 2, and the upper level message of the bidirectional storage device 2 is sent to the program area 7. It transfers to the quadrant integrated communication controller 4 according to the schedule, and processes the upper state monitoring and control message, and the address and data are stored in the memory area 6.

Referring to the timing diagram of FIG. 2, the transmission process of the seventh signal bus data of the present invention operating as described above is as follows.

(a) is the basic clock for communication with the host, and (b) the four channel signal terminal assembly knows its order by the counter signal for communication with the host in order. Is the signal to match.

(c) and (d) are counter internal signals, (e) is a signal to stop communication, and (f) is seventh signal bus data.

In the seventh signal bus, two different seventh signal buses are connected to each of four four-channel signal terminal assembly boards, so that the seventh signal bus is sequentially communicating with an upper level. Therefore, if this is not observed, an error occurs, where (e) indicates that the communication is stopped. (b) By the signal, the count starts at the initial value (address value of the four channel signal terminal assembly) at each initial value and transmits the output data to the upper level as soon as 08. At this time, (c) informs the transmission signal. While (e) is low, (f) is sent upstream.

Therefore, the seventh signal bus is connected so as to communicate with the higher order.

As described above, according to the present invention, since one four-channel signal terminal assembly can perform four channels for the seventh signal level 2 processing, which is the signal matching portion of the all-electronic exchange, the efficiency of the conventional signal transfer circuit is improved. It can be raised more than four times, and the upper reporting system can be reduced to one quarter, effectively implementing the seventh signal bus.

Claims (2)

A four-channel signal terminal assembly for use in an electronic switch, comprising: a signal controller (1) for connecting a bidirectional memory device including an address bus and a data bus and a speed matching unit, and processing a seventh level two protocol; A bidirectional storage device (2) complementary to the signal control section (1), where the processed signal message is recorded; A speed matching unit 3 for receiving a signal input from the signal controller 1 and changing a speed of data; A quadrant integrated communication controller (4) responsible for monitoring the state of the signal controller (1) and processing control messages of a higher level; A serial communication controller (5) which controls the quadrant integrated communication controller (4) to communicate with the upper level 3 when the message is transmitted with the upper level 3; 4 channels for 4 boards per board in an electronic switchgear, characterized by a memory area 6 which is a storage area for basic data and addresses, and a program area 7 which stores a program for executing a recorded message. Four Channel Signal Terminal Assembly (STFA) device. In a method for implementing a four channel signal terminal assembly (STFA) device in an electronic switch, four channels per speed matching device are processed by using a signal controller designed in a four channel signal terminal assembly. All-electronic exchanger characterized in that the speed matching device and the quadrant integrated communication controller for processing channels are installed on one board of each of the four channel signal terminal assemblies to process four channels per board of the four channel signal terminal assembly. 4-channel signal terminal assembly (STFA) method for handling 4 channels per 1 board in my system.