KR0167894B1 - Wide screen signalling circuit in pal plus vtr - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a circuit for processing wide screen signaling in an arm plus broadcast tape recorder according to a video standard in an arm plus video tape recorder.

2. Technical problem to be solved by the invention

Wide-screen signaling on the Arm Plus broadcast signal provides a circuit that can be modified to meet the video specifications of the Arm Plus video tape record.

3. Summary of Solution to Invention

The wide screen signaling included in the arm plus broadcast signal input in the form of the composite video baseband signal is extracted, modified to meet the video standard of the corresponding video tape recorder, and replaced with the widescreen signaling of the original composite video baseband signal. In this case, the wide screen signaling may be modified according to the modification information designated by the user. When an error occurs in the wide screen signaling, the modified data for the previous frame is kept as it is, and the data is corrected to a default value in which the errored frame continues over a preset number.

4. Important uses of the invention

Used for arm plus broadcasting signal processing in the arm plus video tape recorder.

Description

Wide screen signaling processing circuit of ARM plus video tape recorder

1 is a block diagram of a wide screen signaling processing circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

10: micom 12: delay

14 WSS correction circuit 18 multiplexer

The present invention relates to a PALplus type video tape recorder (hereinafter referred to as a VTR), and in particular, a wide screen signaling carried by an arm plus broadcast signal (Wide Screen Signaling: WSS) is a video standard. It relates to a circuit for processing according to.

In general, in a European EDTV broadcasting system, an arm plus broadcast signal includes a WSS having information such as an aspect ratio, an enhanced service, and a subtitle. The WSS is similar to the tele text signal of a conventional TV and is placed on the 23rd line of the arm plus broadcast signal. The WSS basically consists of a preamble and data bits, and is line coded by a bi-phase modulation coding method. The preamble is the start used to determine the run-in code used as the reference signal for the digital phase locked loop (PLL) at the receiver and the sampling point for the data bits following it. Contains the code. The data bits are all 14 bits and contain parity bits. The lower four bits b0 to b3 of the data bits indicate the image format as the screen aspect ratio information, and b3 corresponds to the odd parity bit. The next four bits b4 to b7 of the data bit are additional service information, b4 indicates a camera mode or a film mode, and the remaining b5 to b7 are reserved. The next three bits b8 to b10 of the data bit are subtitle information. The last three bits b11 to b13 of the data bit are reserved.

In the arm plus type VTR for recording / reproducing the arm plus broadcast signal as described above, some of the data bits of the WSS carried in the input arm plus broadcast signal must be modified to conform to the video standard. The data bits to be corrected at this time are b4 of the data bits of the supplementary service information and b8 of the data bits of the subtitle information. The data bit b4 indicates the camera mode when 0 and the film mode when 1. If data bit b8 is 0, it indicates that there is no subtitle in the teletext, and if 1, it indicates that there is a subtitle in the teletext. Therefore, the arm plus type VTR must be processed after forcibly modifying b4 and b8 among the data bits of the WSS contained in the input arm plus broadcast signal to zero.

Accordingly, an object of the present invention is to provide a WSS processing circuit capable of modifying a WSS carried in an arm plus broadcast signal according to a video standard of an arm plus type VTR.

Another object of the present invention is to provide a WSS processing circuit which can modify a WSS carried in an arm plus broadcast signal according to a user's designation.

It is another object of the present invention to provide a WSS processing circuit that can correct a WSS even when an error occurs in the WSS carried in an arm plus broadcast signal.

The present invention for achieving the above object is to extract the WSS included in the arm plus broadcast signal input in the form of a composite video baseband signal (hereinafter referred to as CVBS) modified to meet the video standards of the corresponding VTR It is then characterized by generating a modified CVBS by replacing the original CVBS and WSS again. At this time, if desired by the user, the WSS may be modified according to the modification information designated by the user. When a WSSDP error occurs, the modified data for the previous frame is maintained as it is, and the data is modified to a default value that will continue beyond the preset number of frames in which the error has occurred.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, many specific details are set forth in order to provide a more thorough understanding of the present invention, such as setting specific delay intervals. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted. In the following description, for convenience, the CVBS before the modification, that is, the input CVBS, is called CVBSin, and the modified CVBS, that is, the output CVBS, is called CVBSout.

1 is a block diagram of a WSS processing circuit according to the present invention. The microcomputer 10 generates the modified information on the WSS included in the CVBSindp according to the user's designation and applies it to the data storage unit 36. The retarder 12 delays CVBSin for a 1H (horizontal scan line) period. The WSS correction circuit 14 includes a PLL circuit 18, a synchronous separator 20, a timing generator 22, a data slicer 24, a glitch remover 26 and a start code detector 28. And data clock generator 30, bi-phase demodulation and error detector 32, serial / parallel switching and parity checker 34, data storage 36, bi-phase modulator 38 and run-in, It consists of a start code generator 40 and a pulse generator 42, modifying the WSS of the CVBSin according to the prescribed video standard of the corresponding arm plus VTR and the correction information applied from the microcomputer 10, and modifying the modified WSS to 1 of the CVBSin. Occurs after a frame or 1H period elapses.

The WSS correction circuit 14 first extracts the WSS included in the CVBSin and corrects the video according to the video standard of the corresponding VTR. The PLL circuit 18 inputs CVBSin, generates a system clock signal CLK in synchronization with the run-in code of the WSS in response to the PLL window signal PLL_WIN applied from the timing generator 22, and applies it to the timing generator 22. . The synchronous separator 20 inputs CVBSin and separates the horizontal synchronous signal HS and the vertical synchronous signal VS from the CVBSin and applies them to the timing generator 22. The timing generator 22 inputs the system clock signal CLK from the PLL circuit 18 and the horizontal synchronization signal HS and the vertical synchronization signal VS from the synchronization separator 20 as reference signals, and the data slice window signal DS_WIN and PLL window signal PLL_WIN and the multiplexer. Generates a window signal M_WIN, for the bi-phase demodulation and error checker 32, the serial / parallel conversion and the parity checker 34, the bi-phase modulator 38, and the run-in and start code generator 40. Generate and apply a timing signal. The PLL window signal PLL_WIN is a signal specifying the run-in code section of the WSS included in CVBSin and is active during the run-in code section as a signal specifying the run-in code section. The multiplexer window signal M_WIN is a signal of CVBSin. This signal specifies the WSS interval. The data slicer 24 converts CVBSin into binary digital data of linear force in response to the data slice window signal DS_WIN applied from the timing generator 22. The glitch remover 26 removes spike noise included in the digital data Din converted by the data slicer 24 and applies it to the start code detector 28 and the bi-face demodulation and error checker 32. do. Then, the start code detector 28 detects the start code of the WSS included in the data output from the glitch remover 28 and generates a reset signal. The data clock generator 30 is initialized by the reset signal applied from the start code detector 28, and then generates a data clock signal synchronized with the period of the data Din bits to directly connect with the bi-phase demodulation and error checker 32. / Parallel conversion and parity checker 34 and data storage 36. Accordingly, the bi-phase demodulation and error checker 32, the serial / parallel conversion and the parity checker 34, and the data storage unit 36 can process data in synchronization with the data clock signal. The biphasic demodulation and error checker 32 also bi-phase demodulates the data output from the glitch removal section 26 following the start code and checks for errors. The serial / parallel conversion and parity checker 34 converts the data demodulated by the bi-phase demodulation and error checker 32 into parallel data and checks for errors according to the parity bits.

The data storage unit 36 modifies and stores the data output from the serial / parallel conversion and the parity checker 34 according to the prescribed video standard of the corresponding arm plus VTR and the correction information of the microcomputer 10. At this time, the modification of the WSS in accordance with the prescribed video standard of the corresponding Arm plus VTR is to force b4 and b8 of the data bits of the WSS to zero as described above. In addition, the correction according to the correction information of the microcomputer 10 is to correct the data bits that the user arbitrarily programmed in advance in the microcomputer 10 among the data bits of the aforementioned WSS. Therefore, the data bit designated in advance by the microcomputer 10 is arbitrarily corrected. Therefore, the correction information of the microcomputer 10 is data specifying the data bit to be modified and the bit value. In this way, the modification of the WSS according to the correction information of the microcomputer 10 designated by the user may be omitted without being applied as an option. In addition, the data storage unit 36 stores the start code error in the start code detector 28, the bi-phase demodulation error and the parallel / parallel conversion and parity detector 34 that are checked in the error checker 32. If any of the parity errors to be checked occurs, the data of the previous frame is maintained without storing the data of the corresponding frame. At this time, if any one of the start code error, the bi-phase demodulation error, and the parity error continues more than the preset number, the data is corrected to the default value.

The WSS correction circuit 14 then converts the modified WSS into a signal that can be inserted into the CVBSin. For this purpose, the bi-phase modulator 38 first bi-phase modulates the data stored in the data storage 36. The run-in and start code generator 40 then adds the run-in code and start code to the data modulated by the bi-phase modulator 38. The pulse generator 42 then adjusts the level of the data Dout output from the run-in and start code generator 40 in accordance with the WSS standard and applies it to the multiplexer 16.

Finally, the multiplexer 16 generates the modified CVBS CVBSout by replacing the modified WSS with the WSS of the CVBSin as described above, and the modified WSS applied from the pulse generator 42 and the CVBSin applied from the delay unit 12. Is multiplexed in response to the multiplexer window signal M_WIN applied from the timing generator 22 to generate CVBSout.

The delay 12 is generated so that the timing error does not occur in the multiplexer 16 by delaying the CVBSin by the time required for the WSS correction process by the WSS correction circuit 14. Therefore, in this case, the WSS correction circuit 14 is adjusted so that the corrected WSS is generated and output from the WSS correction circuit 14 at a time point exactly 1H elapsed from the time when the WSS correction circuit 14 starts inputting the WSS. On the contrary, in the case where the WSS correction circuit 14 is adjusted to generate and output the modified WSS from the WSS correction circuit 14 exactly one frame period from the time when the WSS correction circuit 14 starts inputting the WSS. There is no need to use the retarder 12.

As described above, the present invention has the advantage that the WSS contained in the arm plus broadcast signal can be modified in accordance with the video standard of the arm plus type VTR. In addition, the WSS included in the arm plus broadcast signal can be modified according to a user's designation, and there is an advantage that the WSS can be corrected even when an error occurs.

Claims (12)

A wide screen signaling processing circuit of a video tape recorder for recording / reproducing a bi-phase modulated arm plus broadcast signal in the form of a composite video baseband signal, wherein the wide screen signaling of the input composite video baseband signal is performed by the video. A wide screen signaling correction circuit which modifies a wide screen signaling modified according to a prescribed video standard of a tape recorder after one frame period of the composite video baseband signal, and the modified wide screen signaling and the composite video baseband. And a multiplexer for multiplexing the signal to output the modified composite video baseband signal by replacing the modified widescreen signaling with the widescreen signaling of the composite video baseband signal. Processing circuit. 2. The widescreen signaling correction circuit of claim 1, wherein the widescreen signaling correction circuit converts the input composite video baseband signal into serial binary digital data in response to a data slice window signal specifying a run-in code interval of the widescreen signaling. Detects and resets the start code of the preamble of the wide data signaling included in the data slicer to be converted, the glitch removal unit to remove the spike noise included in the converted digital data, and the data output from the glitch removal unit. A start code detector for generating a signal, a bi-phase and error checker for checking errors by bible-phase demodulating data output following the start code from the glitch removing unit, and the bi-phase demodulation and error checker Parry the demodulated data into parallel data A serial / parallel conversion and parity checker that checks for errors according to bits, a data storage unit for modifying and storing data output from the serial / parallel conversion and parity checker according to the video standard, and initializing by the reset signal And a data clock generator for generating a data clock signal synchronized with the period of the data bits and providing the bi-phase demodulation and error checker, a serial / parallel conversion and a parity checker, and the data storage unit. A bi-phase modulator for bi-phase modulating stored data, a run-in and start code generator for adding a run-in code and a start code to the data modulated by the bi-phase modulator, and the run-in and start After adjusting the level of data output from the code generator to the wide screen signaling standard, A pulse generator applied to the multiplexer, a PLL circuit for generating a system clock signal synchronized with the run-in code in response to a PLL window signal specifying the run-in code section, and a horizontal from the composite video baseband signal A synchronous separator for separating a synchronous signal and a vertical synchronous signal, and inputting the system clock signal, a horizontal synchronous signal, and a vertical synchronous signal as reference signals, and the complex for multiplexing the data slice window signal, the PLL window signal, and the multiplexer. A multiplexer window signal for designating a wide screen signaling section of an image baseband signal is generated, and the bi-phase demodulation and error checker, the serial / parallel conversion, the parity checker, the bi-phase modulator, and the run-in and start code generator Characterized in that it comprises a timing generator for generating a timing signal Wide screen signaling processing circuit. The data storage unit of claim 2, wherein when any one of the start code error, the bi-phase demodulation error, and the parity error occurs, the data storage unit maintains the data of the previous frame without storing the data of the corresponding frame. Wide screen signaling processing circuit. The data storage unit of claim 3, wherein the data storage unit modifies the data to a default value when a frame generated by any one of the start code error, the bi-phase demodulation error, and the parity error continues more than a preset number. Wide Screen Signaling Processing Circuit. A wide screen signaling processing circuit of a videotape recorder, which is input in the form of a composite video baseband signal and records / reproduces a bi-phase modulated arm plus broadcast signal, wherein the input composite video baseband signal is input for one horizontal scan line period. A delayer for delaying and modifying the widescreen signaling of the input composite video baseband signal according to a prescribed video standard and modifying the modified widescreen signaling after one horizontal scan line period of the composite video baseband signal has elapsed. A multiplexed signaling modifier and the multiplexed modified widescreen signaling and the composite video baseband signal to replace the modified widescreen signaling with widescreen signaling of the delayed composite video baseband signal to modify the composite video base. Output band signal And a multiplexer for outputting the wide screen signaling processing circuit. 6. The apparatus of claim 5, wherein the widescreen signaling correction circuit converts the input composite video baseband signal into serial binary digital data in response to a data slice window signal specifying a run-in code interval of the widescreen signaling. Detects and resets the start code of the preamble of the wide data signaling included in the data slicer to be converted, the glitch removal unit to remove the spike noise included in the converted digital data, and the data output from the glitch removal unit. A start code detector for generating a signal, a bi-phase demodulation and error checker for bi-phase demodulation and error checking of data output following the start code from the glitch eliminator, and the bi-phase demodulation and error checker Converts the demodulated data into parallel data A serial / parallel conversion and parity checker for parity checking on the tee bits, a data storage unit for modifying and storing data output from the serial / parallel conversion and parity checker according to the video standard, and the reset signal A data clock generator which generates a data clock signal synchronized with the period of the data bit after initialization and provides the bi-phase demodulation and error checker, a serial / parallel conversion and a parity checker, and the data storage unit; A bi-phase modulator for bi-phase modulating the data stored in the apparatus, a run-in and start code generator for adding a run-in code and a start code to the data modulated by the bi-phase modulator, the run-in and After adjusting the level of data output from the start code generator in accordance with the wide screen signaling standard, A pulse generator applied to a multiplexer, a PLL circuit that generates a system clock signal synchronized with the run-in code in response to a PLL window signal specifying the run-in code interval, and horizontal synchronization from the composite video baseband signal. A synchronization separator for separating a signal and a vertical synchronization signal, and inputting the system clock signal, a horizontal synchronization signal, and a vertical synchronization signal as reference signals, for the multiplexing of the data slice window signal, the PLL window signal, and the multiplexer; A multiplexer window signal for designating a widescreen signaling section of a composite video baseband signal is generated, and the bi-phase demodulation and error checker, the serial / parallel conversion and the parity checker, the bi-phase modulator, the run-in and start code generator Characterized in that it comprises a timing generator for generating a timing signal for The wide screen signaling processing circuit. The data storage unit of claim 6, wherein when any one of the start code error, the bi-phase demodulation error, and the parity error occurs, the data storage unit retains the data of the previous frame without storing the data of the corresponding frame. Wide screen signaling processing circuit. The data storage device of claim 7, wherein the data storage unit modifies the data to a default value when a frame generated by any one of the start code error, the bi-phase demodulation error, and the parity error continues more than a preset number. Wide Screen Signaling Processing Circuit. A wide screen signaling processing circuit of a video tape recorder for recording / reproducing bi-phase modulated ARM plus broadcast signals in the form of a composite video baseband signal, the wide screen signaling included in the input composite video baseband signal. A microcomputer for generating correction information according to a user's designation for a user; a delay for delaying the input composite video baseband signal for one horizontal scanning line period; and wide screen signaling of the input composite video baseband signal. A wide screen signaling correction circuit which is modified according to a video standard and correction information of the microcomputer, and the modified wide screen signaling occurs after one horizontal scanning line period of the composite video baseband signal, and the modified wide screen signaling and the delayed signal. Composite video baseband By multiplexing a signal, the modified wide screen signaling the wide screen signaling processing circuit comprising: a multiplexer for the composite image wide output the composite video baseband signal modified by replacing the screen signaling the baseband signal. 10. The apparatus of claim 9, wherein the wide screen signaling correction circuit converts the input composite video baseband signal into serial binary digital data in response to a data slice window signal specifying a run-in code interval of the wide screen signaling. Detects and resets the start code of the preamble of the wide data signaling included in the data slicer to be converted, the glitch removal unit to remove the spike noise included in the converted digital data, and the data output from the glitch removal unit. A start code detector for generating a signal, a bi-phase demodulation and error checker for bi-phase demodulation and error checking of data output following the start code from the glitch eliminator, and the bi-phase demodulation and error checker Convert the demodulated data into parallel data A serial / parallel conversion and parity checker for parity checking of the bits of the bits, and a data storage unit for modifying and outputting data output from the serial / parallel conversion and parity checker according to the video standard and the correction information of the microcomputer; A data clock generator which generates a data clock signal synchronized with the period of the data bits after being initialized by the reset signal and provides the bi-phase demodulation and error checker, a serial / parallel conversion and a parity checker, and the data storage unit. A bi-phase modulator for bi-phase modulating data stored in the data storage unit, a run-in and start code generator for adding a run-im code and a start code to data modulated by the bi-phase modulator; The level of data output from the run-in and start code generator is determined by the widescreen signal. A pulse generator applied to the multiplexer after adjusting to a standard, a PLL circuit for generating a system clock signal synchronized with the run-in code in response to a PLL window signal specifying the run-in code section, and the composite A synchronization separator for separating a horizontal synchronization signal and a vertical synchronization signal from an image baseband signal, and inputting the system clock signal, the horizontal synchronization signal, and the vertical synchronization signal as reference signals, for the data slice window signal, the PLL window signal, and the multiplexer. Generating a multiplexer window signal for designating a widescreen signaling section of the composite video baseband signal for multiplexing; and performing a bi-phase demodulation and error checker, a serial / parallel conversion and a parity checker, a bi-phase modulator, a run-in and To a timing generator that generates a timing signal for the start code generator Wide screen signaling processing circuit, characterized in that the configuration. The data storage unit of claim 10, wherein when any one of the start code error, the bi-phase demodulation error, and the parity error occurs, the data storage unit maintains the data of the previous frame without storing the data of the corresponding frame. Wide screen signaling processing circuit. 12. The method of claim 11, wherein the data storage unit modifies the data to a default value when the frame in which any one of the start code error, the bi-phase demodulation error, and the parity error continues more than a preset number. Wide Screen Signaling Processing Circuit.