KR0166739B1 - Reproducing device for dvcr - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital device (DVCR) reproducing apparatus capable of stably recording and recording data in a transition period without reproducing data. Supply the signal selectively.

That is, in the case of the reproduction section, the equalized reproduction signal is supplied while in the non-signal section, the pseudo reproduction data is supplied to the PLL in a timely manner, thereby preventing the reproduction of the reproduction signal incompletely in the transition section.

Description

Digital VSI playback device

1 is a block diagram of a conventional digital playback device.

2 is an exemplary view showing a recording medium being wound on a drum.

3 is a configuration diagram of a digital playback device of the present invention.

4 is an input / output waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

10,10a: electron conversion unit 20,20a: amplification unit

30,30a: Equalizer 40,40a: Tracking signal detector

50,50a: Servo microcomputer 60,60a: Drive part

70,70a: Slicer 80,80a: PLL

90,90a: Latch part 100,100a: Serial-to-parallel conversion part

110: data generating means 110: controller

112: data generator 113: oscillator

The present invention provides a digital VSI capable of reducing bit errors in an effective period by preventing the PLL circuit supplying a clock for synchronizing playback data from unstable recording during transition periods without playback data by the head switching operation. The present invention relates to a reproducing apparatus of a DVCR, and more particularly to a reproducing apparatus of a digital VSD capable of smoothly performing recording by supplying a pseudo reproducing data to a PLL circuit during a transition period.

In general, a digital VSI requires a process of converting a recording signal into reproduction data in synchronization with a clock output from a PLL circuit when reproducing a signal on a recording medium, and a representative example thereof is shown in FIG. 1.

1 is a block diagram of a digital VSI according to the prior art. As shown in the drawing, the conventional digital BC has an electronic converter 10 including a head, a rotary transformer, and the like. The electronic converter 10 picks up the signal recorded on the recording medium and outputs the signal to the amplifier 20. The amplifier 20 amplifies to an appropriate level after outputting to the equalizer 30. The tracking signal detection unit 40 connected to the amplifying unit 20 receives one end of the amplifying signal, detects the tracking signal, and outputs the tracking signal to the servo microcomputer 50. The servo microcomputer 50 outputs a driving signal to the driving unit 60 to control the drum and the capstan according to the tracking signal.

In addition, the equalizer 30 connected to the amplifying unit 20 compensates the gain and phase of the amplified signal in order to compensate for the nonlinear characteristics generated during the pickup and amplification process, and then outputs the same to the slicer 70. The slicer 70 receives an analog type equalization signal, converts it into a square wave according to a set reference level, and outputs the same to the latch unit 90.

The latch unit 90 latches the output data of the slicer 70 in accordance with the synchronization clock supplied from the PLL 80, and serial-to-parallel converting unit 100 latches data latched according to an applied latch clock (not shown). Will output When serial data is input from the latch unit 90, the serial / parallel conversion unit 100 converts and outputs n-bit parallel data according to the synchronization clock supplied from the PLL 80. Thereafter, n bits of parallel data are signal processed by the reproduction system.

The PLL 80 connected to the output terminal of the equalizer 30 is for extracting a synchronous clock from the equalized signal, and is composed of a phase comparator 81, a low pass filter 82, and a VCO 83. The phase comparator 81 compares the phases of the signals input from the equalizer 30 and the VCO 83, respectively, and outputs an adjustment signal proportional to the phase difference. This adjustment signal is applied to the VCO 83 after the effective band abnormality is removed by the low pass filter 82. The VCO 83 outputs the synchronization clock, which changes according to the filtered adjustment signal, to the phase comparator 81 and the serial-to-parallel converter 100, respectively.

In the conventional digital VSI driving apparatus, as shown in FIG. 2, when the winding angle of the recording medium M wound on the drum D is smaller than 180 degrees, a section without a reproduction signal, that is, a no signal section occurs. In this no-signal section, the clock frequency output from the VCO 83 is free run, thereby increasing the influence of noise.

In other words, as the adjustment signal output by the phase comparator 81 receiving no signal fluctuates excessively, the clock frequency of the VCO 83 also becomes unstable. Therefore, when switching from the no-signal section to the playback section, the PLL 80 is difficult to record in an instant and there is a problem that the original playback signal cannot be obtained at the beginning of playback. SUMMARY OF THE INVENTION An object of the present invention for solving such a problem is to provide a digital playback device for smoothly performing recording by supplying pseudo playback data to a PLL during a transition period.

An object of the present invention as described above includes an electronic converter for picking up a recording signal from a recording medium, and a servo microcomputer for controlling a drum and a capstan. A digital VSI reproducing apparatus for converting into predetermined parallel data, wherein the driving operation of the drum and capstan is controlled in accordance with a tracking signal extracted from the reproducing signal picked up by the head, and the head switching signal generated by the rotation of the drum is controlled. Servo microcomputer that inputs and generates valid data signal and outputs to equalizer and data generating means, and signal-free section is discriminated according to head switching signal and valid data signal applied from the servo microcom and pseudo-playback data is determined according to the discrimination result. It is connected to the data generating means for outputting, and the output terminal of the equalizer and the data generating means This is accomplished by a switching unit which performs a switching operation in accordance with a control signal output from the servo microcomputer to selectively supply each output signal to the PLL.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a configuration diagram of a digital playback device of the present invention, and FIG. 4 is an input / output waveform diagram of each part of FIG. As shown in the drawing, the digital playback device of the present invention includes an electronic converter 10a. The electronic converter 10a reads the signal recorded on the recording medium, converts the signal into an electrical signal, and outputs the signal to the amplifier 20a. The amplifier 20a amplifies the weak signal to an appropriate level and outputs a reproduced signal as shown in FIG. 4 (a) to the equalizer 30a. The equalizer 30a connected to the output terminal of the amplifier 20a adjusts the gain and phase to compensate for the nonlinear characteristics generated during the pickup operation and the amplification process, and then outputs them to the slicer 70a.

The slicer 70a converts the digital signal into digital signals according to the upper limit reference level and the lower limit reference level among the equalized reproduction signals, and outputs them to the latch unit 90a. The latch unit 90a outputs serial data by synchronizing the converted digital signal with the clock of the PLL 80a.

This serial data is converted into n-bit parallel data by the serial-to-parallel converter 100a. In this regeneration process, the servo microcomputer 50a outputs a hole signal to the driving unit 60a according to the tracking signal of the tracking signal detection unit 40a and the head switching signal HDS of the driving unit 60a. Accordingly, the driving unit 60a can drive the drum motor and the capstan motor in the corresponding mode.

Here, as shown in FIG. 4A, the output signal of the amplifying unit 20a has a non-signal section without a playback signal by the head switching operation and is periodically repeated.

The present invention further includes a data generating means (110) between the servo microcomputer (50a) and the PLL (80a) in order to prevent the synchronous clock of the PLL (80a) from becoming unstable in the no signal section. The data generating means 110 is a data generator 112 for outputting pseudo reproduction data, a controller 111 for determining whether to output pseudo reproduction data, and an oscillator 113 for supplying an oscillation frequency to the data generation unit 112. Is made of.

The controller 111 receives a head switching signal HDS as shown in (b) of FIG. 4 and a data valley signal VHS as shown in (c) of FIG. 4 from the servo microcomputer 50a to generate a signal-free period. In response, the start signal START and the stop signal STOP are output to the data generator 112. When the servo microcom 50a receives the tracking signal and the head switching signal HDS from the tracking signal detection unit 40a and the driving unit 60a, respectively, and outputs the driving signal to the driving unit 60a, the driving unit 60a is a drum. Drive the motor and capstan motor. The servo microcomputer 50a outputs the head switching signal HDS and the data valley signal VHS to the controller 111, and also outputs the data valley signal VHS to the equalizer 30a. The equalizer 30a is disabled when the data valley signal VHS as shown in FIG. 4 (c) is enabled when the high state is 'high'. Meanwhile, the controller 111 may enable the data generator 112 to be enabled when the head switching signal HDS is 'high' and the data valley signal VHS is 'low', that is, when there is no signal period. The start signal START is output to the data generator 112, and a stop signal STOP for disabling the data generator 112 is switched when switching to the playback signal section. The data generator 112 determines whether to output the pseudo reproduction data according to the applied start signal START and stop signal STOP.

That is, when the data generator 112 is switched from the disabled state to the enabled state, the data generator 112 outputs the pseudo reproduction data to the switching unit 120 using the oscillation frequency applied from the oscillator 113. At this time, the switching unit 120 short-circuits the Q terminal to supply the pseudo reproduction data to the PLL 80a by the control signal of the servo microcomputer 50a.

On the other hand, when the stop signal STOP is applied from the controller 111, the data generator 112 stops outputting the pseudo reproduction data. This is for supplying the equalized signal to the PLL 80a by enabling the equalizer 30a at the time of switching to the playback section. The switching unit 120 is connected to the P terminal by a control signal of the servo microcomputer 50a. By shorting the equalized signal can be supplied to the PLL (80a).

Therefore, the PLL 80a receives the output signal of the equalizer 30a and outputs a synchronous clock in the reproduction section as in the prior art, and in the non-signal section generated by the head switching operation in the electronic converter 10a. Since the synchronizing clock can be outputted from the generating means 110 and outputs the synchronous clock, the synchronous clock outputted by the PLL 80a can be stably supplied even when the reproducing section is switched from the no signal section or the no signal section to the reproducing section. Can be.

As described above, the present invention can discriminate the presence or absence of a playback signal according to the head switching signal and the data valley signal, and in the case of the no signal section, the pseudo playback data can be supplied to the PLL in a timely manner, thereby reducing the bit error as well as the transition period. The reproduction signal can be prevented from being reproduced incompletely, so that a good reproduction signal can be obtained.

Claims (4)

An electronic conversion unit for picking up a recording signal from a recording medium, a servo microcontroller for controlling a drum and a capstan, and amplifying and equalizing the picked-up playback signal to convert the playback data into predetermined parallel data according to the PLL's sync clock. In the playback device of VSIAL, the driving operation of the drum and the capstan is controlled according to the tracking signal extracted from the playback signal picked up by the head, and the head switching signal generated by the rotation of the drum is input to generate an effective data signal. A servo microcomputer for outputting to the tile and data generating means; Data generating means for discriminating no signal section in accordance with the head switching signal and the valid data signal applied from the servo microcomputer and outputting pseudo reproduction data according to the discrimination result; And a switching unit connected to the output terminal of the equalizer and the data generating means and performing a switching operation according to a control signal output from the servo microcomputer to selectively supply each output signal to the PLL. Playback device. 2. The servo microcomputer of claim 1, wherein the servo microcomputer outputs a first control signal to the switching unit to supply an equalized signal to the PLL in the playback section, and to the switching unit to supply the pseudo playback data to the PLL in the no-signal section. And a second control signal is output. The oscillator according to claim 1, wherein the data generating means includes a controller for discriminating no signal section in accordance with a head switching signal and a valid data signal of a servo microcomputer, and an oscillator for outputting an oscillation frequency corresponding to a bit rate of a reproduction signal to the data generator. And a data generator for outputting the pseudo reproduction data formed from the oscillation frequency to a switching unit under the control of a controller. The apparatus of claim 3, wherein the data generator outputs the pseudo reproduction data to the switching unit by using the oscillation frequency of the oscillator when a start signal is applied from the controller.