KR100230773B1 - Equalizer for vcr - Google Patents

Abstract

The present invention relates to an equalization technique of digital BC, in order to provide a digital equalization circuit of a digital VLC applied a digital equalizer technology to variably change the region of the center frequency for synchronization, A A timing detector 310 for generating a timing signal V _PLL-LPF for adjusting the sampling timing of the / D converter 304; A zone selector 312 which outputs a zone value ZV for determining an initial oscillation frequency of the VIO 314 and also outputs a synchronization determination signal PLL_lock; An adder (313) and BCIO (314) for providing a sampling clock signal with an accurate timing to the A / D converter (304) based on the zone value (ZV) and the timing signal (V _PLL-LPF ); Generation of an internal control signal that generates synchronization determination signal (PLL_lock), PLL timing signal (PLL_Acq), equalization train signal (Eq_Train), etc. so that the digital equalizer 305 can operate adaptively to the characteristics of the digital VLC. It is comprised including the part 316.

Description

DIGITAL LIGHTING CIRCUITS

1 is a block diagram of a general digital equalizer.

2A to 2E are timing signal waveform diagrams of a general digital equalizer.

3 is an exemplary block diagram of a digital equalization circuit of the present invention Digital BC.

FIG. 4 is a detailed block diagram showing an embodiment of the zone selector in FIG.

FIG. 5 is a detailed block diagram showing an embodiment of the synchronization determiner in FIG.

6 is an exemplary explanatory diagram of a zone.

7A to 7F are waveform diagrams of various timing signals generated by the internal control signal generator of FIG.

8 is a track format diagram of a digital VCD.

9 is an explanatory diagram of a PR4 target applied to a digital equalizer in FIG.

FIG. 10 is an explanatory diagram of an output signal pattern of a digital equalizer in FIG.

* Explanation of symbols for main parts of the drawings

300: digital equalizer 301: preamplifier

302: automatic gain control unit 303: low pass filter

304: A / D converter 305: Digital equalizer

306: data detector 307: coefficient initializer

308: coefficient adjusting unit 309: timing initialization unit

310: timing detector 311: zone value initializer

312: zone selector 313: adder

314 V: 315: communication unit

316: internal control signal generator 317: power storage unit

318: reset unit 319: system control unit

TECHNICAL FIELD The present invention relates to a digital VLC equalization technique, and more particularly, to a digital equalizer circuit of a digital VLC capable of variably changing a region of a center frequency for synchronization by applying a digital equalizer to a digital VRL.

FIG. 1 is a block diagram of a general digital equalizer, and its operation will be described with reference to FIG.

Since the data DATAin read out from the recording medium by the head is an extremely weak signal, it is amplified to a predetermined level through the preamplifier 101 and then the automatic gain control unit 102 is used to compensate for the difference in signal levels between channels. Then, the gain is adjusted and output, and the processed signal is converted into a digital signal through the A / D converter 104 after the broadband noise is removed through the low pass filter 103.

The digital equalizer 105 variably changes the initial oscillation frequency value of the local oscillation frequency for synchronous reproduction in the equalization process of the signal output from the A / D converter 104, and outputs the data detector 106. Detects data from the equalized signal and generates final output data DATAout.

At this time, the system controller 117 outputs the servo gate signal SG and the lead gate signal RG as shown in FIGS. 2A and 2B, and also outputs the write gate signal WG. In addition, the internal control signal generator 114 receives the gate signals SG, RG, and WG to receive the lead gate signal RG 'as shown in FIG. 2C synchronized with the internal reference clock. In addition to this, a sync field counter signal SFC is generated as shown in FIG.

However, when the sync field counter signal SFC has a preset value based on the rising edge of the lead gate signal RG 'as shown in (c) and (d) of FIG. 2, an internal flag is set and enabled. When the read gate signal RG 'is set to the falling edge, the PLL is synchronized with the sink field counter signal SFC while the enable state is maintained.

The coefficient is adjusted by the coefficient adjusting unit 108 when the equalization start condition of the digital equalizer 105 is established, and the coefficient adjusting operation is stopped by the coefficient adjusting unit 108 when the equalization stop condition is established.

The communication unit 113 communicates with the system control unit 117 to determine the initialization time of the coefficient initialization unit 107, the timing initialization unit 109, and the low pass filter initialization unit 112. A sampling clock signal corresponding to the output timing signal of the timing detector 110 is generated and provided to the A / D converter 103.

However, such a digital equalizer circuit is designed to be applied to a specific system such as a hard disk drive, so there is a defect that cannot be applied to digital VCs. There is a lot of jitter in the clock, which results in a defect of poor data recovery rate.

Accordingly, it is an object of the present invention to provide a digital equalization circuit of a digital VC with a digital equalizer technology applied so as to variably change a region of a center frequency for synchronization.

FIG. 3 is an exemplary block diagram of the digital equalization circuit of the present invention Digital VR in order to achieve the above object. As shown in FIG. 3, FIG. 3 is suitable for equalizing data DATA read from a recording medium and inputted thereto. A preamplifier 301, an automatic gain control unit 302, and a low pass filter 303 which performs preprocessing to perform the preprocessing; An A / D converter 304 for converting the low-pass filtered analog signal into a digital signal; A digital equalizer 305 which receives the output signal of the A / D converter 304 and equalizes it according to a predetermined format (PR4 Target); A data detector 306 for restoring original data from the output signal y of the digital equalizer 305; A coefficient adjusting unit (308) for adjusting coefficients such that the characteristics of the digital equalizer (305) are close to desired characteristics; A timing detector (310) for generating a timing signal (V _PLL - _LPF ) for adjusting a sampling time point of the A / D converter 304; A zone selector 312 which outputs a zone value ZV for determining an initial oscillation frequency of the VIO 314 and also outputs a synchronization determination signal PLL_lock; An adder (313) for adding the zone value (ZV) and a timing signal (V _PLL - _LPF ); A VSI 314 for generating an oscillation signal having a frequency corresponding to the output signal of the adder 313 and providing it as a sampling clock signal of the A / D converter 304; An internal control signal for generating a synchronization determination signal (PLL_lock), a PEL timing signal (PLL_Acq), an equalization train signal (Eq_Train), and the like so as to be adaptive to the characteristics of the digital equalizer 305 and the digital VLC. A generator 316; It consists of a system control unit 319 for controlling the overall control of the respective parts in the digital equalization unit 300 through the communication unit 315, in detail with reference to FIGS. The explanation is as follows.

After the data DATAin read out from the recording medium by the head is amplified by a low noise preamplifier 301, a gain is obtained through the automatic gain control unit 302 to compensate for the difference in signal levels between channels. The low frequency filter 303 removes the broadband noise through the low pass filter 303. The low pass filter 303 is designed in a programmable form that can change the blocking characteristic and the step-up characteristic. By eliminating this, roughly equalization is performed.

The analog signal output from the low pass filter 303 is converted into a digital signal through an A / D converter 304 and supplied to the digital equalizer 305. The digital equalizer 305 receives the input digital signal ninth. The equalization is performed in accordance with the PR4 target of FIG.

H (D) = (1-D) (1 + D) (Eq. 1)

Where D: delay operator

The coefficient adjusting unit 308 adjusts the characteristics of the digital equalizer 305 so that the characteristics of the entire equalizer are as close as possible to Equation 1, and the timing detector 310 is the A / D converter 304. Digital data having an accurate timing is input to the digital equalizer 305 to generate a timing signal for equalization.

In addition, the zone selector 312 serves as a part for determining the initial oscillation frequency of the VIO 314 and will be described with reference to FIG. 4 showing an embodiment thereof as follows.

The change frequency storage unit 312A stores a basic zone change value (Δ = fc.vco) for changing the center frequency of the VIO 314, which is set in consideration of the synchronous range of the PLL. As a block for storing a value corresponding to the center frequency of the VIO 314 of the zone value storage unit 312E, whenever the zone update clock signal ZCK is input, the change frequency storage unit 312A is added through the adder 312B. The zone change value (Δ) outputted from is cumulatively added, and when the cumulative added value reaches the preset maximum value, the zone change value Δ is changed back to the preset minimum value and stored. For example, as shown in FIG. 6, when the zone is divided into three zones, the zone change value is changed from zone 1 to zone 2 to zone 3 to zone 1... Whenever the update clock signal is applied. Change to and save.

The zone update clock signal ZCK determines whether the PLL is synchronized while the PEL tie signal PLL_Acq generated by the internal control signal generator 316 according to the timing of FIG. 7 is maintained at the "high" level. Is a clock signal generated by the Here, the PEL timing signal PLL_Acq is a signal indicating a time required for determining whether the PLL is synchronized.

When the process of determining whether the PLEL is synchronized, the output signal y of the digital equalizer 305 is supplied to the data determiner 308A to obtain the data value d output therefrom, and the subtractor 308B generates the error signal Error by subtracting the output signal y from the data value d. In addition, the synchronization determiner 312C removes the noise component by passing the error signal through the low pass filter 501 as in the fifth, and then compares the absolute value of the error with the reference value EB in the comparator 502. If it is smaller than the reference value EB, it is determined that synchronization is performed. If it is large, it is determined that synchronization is not performed, and accordingly, the PLL_lock of the PLL is output accordingly.

For reference, when the synchronization is well performed, the output signal y of the digital equalizer 305 is shown in FIG. 10, and when the synchronization is not performed, the data appears in a random form from the reference value.

The PLL synchronization lock signal PLL_lock is validated by the AND gate 312D when the PLL timing signal PLL_Acq is in an enabled state, and is output as the zone update clock signal ZCK.

As another embodiment of the synchronization determination, the timing signal V _PLL-LPF output from the timing detector 310 may be provided as an input signal of the synchronization determiner 312C to determine synchronization.

Meanwhile, the internal control signal generator 316 generates various control signals as shown in FIG. 7 so that the digital equalizer 305 can operate adaptively to the characteristics of the digital VLC. The following is the timing order.

First process; When the user inputs a digital key play key signal PLAY, the system controller 319 receives the play key signal PLAY and transmits data to the communication unit 315 to initialize the digital equalizer 300. When the data transfer operation is completed, the reset signal is output to the reset unit 318 to initialize the digital equalizer 300. The initialization data includes the cutoff frequency of the low pass filter 303, data related to the boosting characteristic, gain and count values for coefficient adjustment, count adjustment stop mode, timing adjustment gain, zone value (ZV), zone change value (Δ), and the like. This is included and they are stored in their respective initializers.

Second process; When the digital VSR servo system is stabilized and the stabilization recognition signal ATF_Lock as shown in FIG. 7B is applied to the internal control signal generator 316, data can be read normally from the tape. That is, the stabilization recognition signal (ATF_Lock) is a signal indicating that the servo system is stabilized in the digital V playback mode. If the signal is "high", the servo system is in a stable state and the data written on the tape can be read correctly. Indicates that it is possible.

Step 3: When the tracking switching signal TS as shown in (c) of FIG. 7 is generated, the internal control signal generator 316 for a predetermined time until the head reaches the shear track PRO of FIG. Wait

Step 4: Then, when the head reaches the front end track PRO, the internal control signal generator 316 generates the PEL timing signal PLL_Acq as shown in (d) of FIG. ), The PLL timing adjustment is started, and at this time, the internal control signal generator 316 observes the synchronization determination signal PLL_lock output from the zone selector 312. Here, the enable holding time T1 of the PLL timing signal PLL_Acq is set such that the PLL is sufficiently synchronized.

Step 5: When the falling edge of the PLL timing signal PLL_Acq is synchronized, the PLL is synchronized when the synchronization determination signal PLL_lock shown in (e) of FIG. 7 output from the zone selector 312 is "high". The internal control signal generator 316 enables the equalization train signal Eq_Train to " high " as shown in FIG. 7 (f) to adjust the digital equalizer 305. However, when the synchronization determination signal PLL_lock is “low”, since the synchronization is not performed, the fourth and fifth processes are repeated.

Step 6: The stopping operation of the coefficient adjustment of the digital equalizer 305 may be executed by the system controller 319 when it is determined that the equalization is sufficiently performed. As another example, when the stabilization recognition signal ATF_Lock becomes " low " because the servo system is not stabilized due to no data or other factors, the coefficient adjusting operation is stopped and the previous coefficient value is maintained as it is.

Step 7: When the stabilization recognition signal ATF_Lock remains "disabled" to "low" and the coefficient adjustment is stopped, when the stabilization recognition signal ATF_Lock is changed to "high", after the third process Repeat the process.

On the other hand, the data detecting unit 306 restores the data originally recorded on the tape by using the output signal y of the digital equalizer 305. The data determiner 308A of FIG. 4 and the subtractor 308B for calculating an error signal are generally included in the coefficient adjusting unit 308, which may be used to obtain equalization error information.

As described in detail above, the present invention is easier to design than the analog equalizer by applying a new type of digital equalization technology to variably change the region of the center frequency for synchronization in designing the digital BC It can be programmed to show various possibilities, and it is possible to absorb the change of data frequency due to the amount of tape or load change at high speed playback by changing the zone even when the speed of drum or capstan motor is fixed. There is an effect, the operation is possible in a smaller synchronization range than the analog equalizer, the jitter of the reproduction data and the clock is reduced, thereby improving the data recovery rate.

Claims (3)

A digital equalizer for pre-processing data DATAin read out from a recording medium, converting it into a digital signal through an A / D converter 303, and then performing equalization through a digital equalizer 305. A timing detector 310 for generating a timing signal V _PLL-LPF for adjusting the sampling timing of the / D converter 304; A zone selector 312 which outputs a zone value ZV for determining an initial oscillation frequency of the VIO 314 and also outputs a synchronization determination signal PLL_lock; An adder (313) and BCIO (314) for providing a sampling clock signal with an accurate timing to the A / D converter (304) based on the zone value (ZV) and the timing signal (V _PLL-LPF ); An internal control signal that generates a synchronization determination signal PLL_lock, a PEL timing signal PLL_Acq, an equalization train signal Eq_Train, and the like so that the digital equalizer 305 can operate adaptively to the characteristics of the digital VLC. A digital equalization circuit of digital V-C, comprising a generator 316. 2. The apparatus of claim 1, wherein the zone selector (312) comprises: a change frequency storage (312A) for storing a basic zone change value (Δ) for changing the center frequency of the VIO (314); A synchronization determiner 312C for comparing the error signal Error with the reference value EB and generating a synchronization determination signal PLL_lock; An AND gate (312D) for validating the synchronization determination signal (PLL_lcok) according to the PEL timing signal (PLL_Acq) and outputting it as a zone update clock signal (ZCK); And a zone value storage unit 312E which generates a zone value ZV by accumulating and adding the zone change value Δ through a trailing device 312B whenever the zone update clock signal ZCK is input. Digital equalization circuit of digital VLC. 3. The apparatus of claim 2, wherein the synchronization determiner (312C) comprises: a low pass filter (501) for low noise filtering the error signal or the timing signal (V _PLL-LPF ) to remove noise components; And a comparator (502) for comparing the absolute value of the error signal output from the low pass filter (501) with a reference value (EB) and outputting a PLL synchronization determination signal (PLL_lock).