KR0165076B1 - Dual system cluck supply device of exchanger - Google Patents

Abstract

The present invention provides a system clock supplying device for supplying a system clock having a simple configuration suitable for a small-capacity local exchange but synchronously with an upper station exchange and a system clock having the same phase and frequency as the system clock to an internal device of the exchange. It is about.

The present invention corrects the clock synchronization with the host station at every cycle of the synchronous clock, and performs phase correction between the master and the slave in the system clock output of the counter and the basic clock oscillation of the oscillator. It can be provided to the device, and it is not necessary to have an expensive oscillator with high stability, and since it consists of two single unit system clock supply units in a redundant configuration, small capacity is considered in consideration of performance, cost, and installation space. The effect is most suitable for the exchanger.

Description

Redundant system clock supply of exchange

1 is a simplified configuration diagram of a conventional system clock supply device.

2 is a detailed configuration diagram of the first or second system clock oscillation unit of the conventional system clock supply.

3 is a simplified configuration diagram of a system clock supply apparatus according to the present invention.

4 is a detailed configuration diagram of each system clock supply apparatus of the redundant system clock supply apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

A, B, C: first to third oscillator 10, 10A: first and second system clock oscillator

1: basic clock selector 2, 121: phase detector

3: filter part 4, 131: oscillation part

5, 132: counter section 6: main slave selection section

7: Clock distribution supply unit 100, 100A: system clock supply unit

110: sync clock generator 111: reference clock selector

112: dividing circuit 120: oscillation control unit

122: comparison and counting unit 123: D / A unit

130: system clock generator 140: reset signal selector

150: main control unit 151: search unit

152: state control unit 160: system clock selector

The present invention relates to a system clock supply apparatus for supplying a system clock to an internal device of an exchanger. In particular, the present invention relates to a stable system clock in which phase synchronization and frequency synchronization are repeatedly corrected every predetermined period while having a simple configuration suitable for a small capacity local exchange. A redundant system clock feeder for supplying each internal device of the exchanger.

In general, since the system clock for the internal device of the exchange is essential to the operation of the exchange, the same two system clocks are supplied to each internal device, and each internal device selects and operates one of the two system clocks. At this time, the two system clocks supplied to each internal device are output from separate clock supply devices having the same structure, and each internal device selects the system clock output from the clock supply device operating as a master by initial setting. Each internal device selects the system clock output from the clock supply device acting as a slave when the clock supply device acting as a master fails.

Referring to the redundant system clock supply of the prior art from the above-described general description as follows.

1 is a simplified configuration diagram of a conventional redundant system clock supply device, the first oscillation unit A for receiving a reference clock from an upper station exchanger and outputting a basic clock for generating a system clock synchronized with the reference clock; The second and third oscillators B and C and the first to third oscillators A, which have the same structure as the first oscillator A and output a reference clock synchronized with the reference clock of the first oscillator A, The system clock is generated in synchronization with the basic clock of the first oscillator A among the basic clocks output from B and C), and the generated system clock is transmitted to each internal device of the exchanger, and the first system clock oscillator 10 is provided. The second system clock oscillator 10A having the same structure as the system clock oscillator 10 and outputting the system clock synchronized with the system clock output from the first system clock oscillator 10 to each internal device of the exchanger. have.

2 is a detailed configuration diagram of the first or second system clock oscillator 10, 10A of the conventional system clock supply apparatus, and shows the basic clock output from the first to third oscillator A, B, C. A basic clock selector 1 to select, an oscillator 4 for outputting a clock frequency of a predetermined frequency according to the input voltage, a clock output from the oscillator 4, and a basic clock selected from the basic clock selector 1 Phase detection unit 2 for outputting a constant voltage according to the comparison result by comparing the phase difference with the filter unit, filter unit 3 for supplying the voltage output from the phase detection unit 2 to the oscillation unit 4 by removing the AC component The counter unit 5 receives the clock output from the oscillator 4 through the phase detector 2 and outputs a plurality of system clocks necessary for the internal device of the exchange and outputs a reset signal of a predetermined frequency for synchronizing the system clock. And the system clock output from the counter section 5 inside each of the exchangers. The clock distribution supply unit 7 for distributing and supplying to the device and the reset signal output from the counterpart secondary oscillator in the slave operation are supplied to the counter unit 5, and the counter unit 5 outputs the counter signal when operating as a master. It consists of a main slave selector (6) for returning the reset signal to the counter (5).

Referring to the operation of the conventional system clock supply device configured as described above, the first oscillation unit (A) is the first clock, the second system clock oscillation unit (10, the base clock of a predetermined frequency in synchronization with the reference clock supplied from the upper station exchange) 10A), and the remaining second and third oscillators B and C use the first and second system clock oscillators to output a basic clock having a predetermined frequency in which the phase and the frequency coincide with the clock output from the first oscillator A. FIG. Output as (10, 10A). At this time, the first oscillator A becomes a master and the remaining second and third oscillators B and C become slaves. If the second oscillator B or the third oscillator C is supplied from an upper station exchange, The second oscillator B or the third oscillator C will be the master if the basic clock of the predetermined frequency synchronized with the output is output.

Thereafter, the basic clock selector 1 of the first and second system clock oscillators 10 and 10A is the first oscillator A that is the master among the basic clocks of the first to third oscillators A, B, and C. Select the basic clock and apply it to the phase detector 2, and the phase detector 2 phases the phase of the clock of the predetermined frequency output from the oscillator 4 and the basic clock applied from the basic clock selector 1. In comparison, a predetermined voltage according to the comparison result is applied to the filter unit 3. The filter unit 3 supplies the voltage applied from the phase detector 2 to the oscillator 4 after removing the AC component, and the oscillator 4 clocks at a predetermined frequency according to the DC voltage supplied from the filter unit 3. Generate and print

The counter unit 5 receives the clock output from the oscillator 4 through the phase detector 2 and divides it, generates and outputs a system clock necessary for each internal device of the exchanger, and synchronizes the occurrence of the system clock by division. Outputs a reset signal. Thereafter, the system clock output from the counter section 5 is supplied to each internal device by the clock distribution supply section 7, and the reset signal output from the counter section 5 is supplied to the main slave selection section 6. The above operation is an operation common to the first and second system clock oscillators 10 and 10A. If the first system clock oscillator 10 is set as a master and the second system clock oscillator 10A is set as a slave during initial setting, 1 The main slave selector of the system clock oscillator 10 supplies the active signal to the main slave selector of the second system clock oscillator 10A, and resets the reset signal output from the counter to the main slave selector of the second system clock oscillator 10A. To the counter that outputs the reset signal.

In addition, the main slave selector of the second system clock oscillator 10A receives an active signal from the main slave selector of the first system clock oscillator 10 and receives the reset signal output from the counter. Outputs the reset signal supplied from the second system clock oscillator 10A to the counter unit. Therefore, at the initial setting, the system clock oscillator selected as the master generates its system clock using its own reset signal and supplies it to each internal device, and the system clock oscillator selected as the slave uses the reset signal provided by the counterpart system clock oscillator. A system clock is generated and supplied to each internal device.

In the conventional system clock supplying device operating as described above, the phase correction is not performed in the clock oscillation step by the oscillator when the second system clock oscillator operating as a slave is phase corrected with the first system clock oscillator operating as a master. Since the phase is corrected by the reset signal provided from the first system clock oscillator operating as a master in the system clock generation step by the negative, an expensive oscillator having high stability is required, and the triplet of the first to third oscillators Since it takes a lot of cost and installation space, there is a problem that is not suitable to apply to a small-capacity local exchange.

An object of the present invention for solving this problem is to configure the system clock generator of a single unit that can be switched to the master or slave in a redundant configuration to reset the reset signal and the system clock output from the system clock generator selected as the master The present invention provides a redundant system clock generator which is supplied from a system clock generator operating as a slave to enable phase correction in both the clock oscillation step by the oscillator and the system clock generation step by the counter.

In order to achieve the above object, a feature of the present invention is a redundant system clock supply apparatus of an exchanger for supplying a system clock to an internal device of an exchanger, wherein the system synchronizes phase synchronization with a reference clock provided by a host station at regular intervals. The master outputs the clock to each internal device and the first external terminal of the exchanger, and outputs a reset signal for output timing of the system clock and a master slave selection signal related to master or slave operation to the second and third external terminals. A first system clock supply device; A system clock in which phase synchronization and output timing are adjusted by the reference signal and the reset signal output from the first system clock supply device is generated, and the system is output from the first system clock supply device and input to the internal device. And a second system clock supply device which supplies a clock and acts as a slave to act as the first system clock supply device according to a master slave selection signal output from the first system clock supply device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a simplified configuration diagram of a redundant system clock supply device according to the present invention. The system synchronous clock, which is supplied with a reference clock provided by an upper station exchange and matches a reference clock and phase synchronization, is applied to each device in the exchange. A first system clock supply device (100) for outputting a reset signal for output timing of the synchronous clock and a master synchronous selection signal (M / S) related to master or slave operation through an external terminal; Received the master slave selection signal (M / S), the reset signal and the system clock output from the system clock supply device 100 and the reference clock provided from the upper station exchange and the reset output from the first system clock supply device 100. A system synchronous clock is generated according to a signal and an internal device is input from the first system clock supply device 100. A second system clock supply device 100A which applies a synchronous clock and performs a function performed by the first system clock supply device 100 when necessary according to the master slave selection signal M / S.

4 is a detailed configuration diagram of each of the system clock supply apparatuses 100 and 100A of the redundant system clock supply apparatus according to the present invention, which outputs a synchronous clock for matching phase synchronization to a reference clock provided from an upper station exchange. An oscillation controller 120 that detects a phase difference between the synchronous clock and the system clock output from the synchronous clock generator 110, and outputs a detection result at a predetermined voltage; and the oscillation controller 120. The system clock generator 130 outputs the system clock and the reset signal according to the predetermined voltage outputted by the controller, and resets the system clock generator 130, the system clock generator 130, and the counterpart system clock supply device. A reset signal selector 140 for selecting one of the signals and supplying the signal to the system clock generator 130, and a system clock output from the system clock generator 130 and the counterpart system clock supply device. The system clock selector 160 selects one of the blocks and outputs the data to each internal device of the exchanger, and a main controller 150 for controlling operation of the master or slave and each unit in the system clock supply device.

In addition, the synchronization clock generator 110 divides the selected reference clock with the reference clock selector 111 that selects a reference clock of a predetermined form among the reference clocks provided by the upper station exchange, and synchronizes the phase clock of the system clock. The frequency divider circuit 112 outputs a clock.

In addition, the oscillation controller 120 detects a phase difference between the synchronous clock output from the frequency divider 112 and the system clock output from the system clock generator 130 and outputs digital data indicating the detected phase difference. 121 and the comparison and counting unit 122 for comparing the digital data output from the phase detection unit 121 with preset reference data and outputting the comparison result as digital data, and the output from the comparing and counting unit 122. The D / A unit 123 converts and outputs digital data into analog, that is, DC voltage.

In addition, the system clock generator 130 adjusts the frequency of the basic clock according to the magnitude of the voltage output from the D / A unit 123 and outputs the oscillator 131 and the basic clock output from the oscillator 131. The system clock and reset signal are output by dividing. The system clock output timing is adjusted by the reset signal output by itself when operating as a master, and the system clock output timing by the reset signal provided by the counterpart system clock supply device when operating as slave. It consists of a counter unit 132 to fit.

In addition, the main control unit 150 checks the system clock output from the counter unit 132 and outputs information on the presence or absence of an abnormality, the initial setting and the information output from the search unit 151. Accordingly, by controlling the reference clock selector 111, the reset signal selector 140, and the system clock selector 160, the state controller 152 controls the system clock supply operation by the master or the slave.

Referring to the operation of the redundant system clock supply apparatus according to the present invention configured as described above are as follows.

4 is a detailed view common to each of the system clock generators 100 and 100A shown in FIG. 3, so that all internal blocks of the system clock supply device 100 are shown in FIG. The number specified in the description will be used as it is, and all internal blocks of the system clock supply device 100A will be described with the addition of A in addition to the number specified in FIG. 4 (eg, the system supply device 100). Counter portion 132 and the counter supply portion 132A of the system supply device

Redundant system clock supply apparatus according to the present invention mounted inside the exchanger has a master station or slave operation to the main processor of the exchanger and the state controllers 152 and 152A of the respective system clock supply apparatuses 100 and 100A at the initial setting. Matters such as which reference clock to select among the reference clocks provided from the exchange are set. Thereafter, two reference clocks having different frequencies from the upper station exchanger are supplied to the system clock supply device 100 that operates as a master and the system clock supply device 100A that operates as a slave, and the system clock supply devices 100 and 100A. The state controllers 152 and 152A supply a predetermined control signal for selecting the reference clock to the reference clock selectors 111 and 111A.

The reference clock selectors 111 and 111A select one reference clock according to the control signals supplied from the state controllers 152 and 152A, transfer the selected reference clocks to the division circuits 112 and 112A, and divide the division circuits 112. , 112A divides the reference clock and outputs a synchronous clock of a predetermined frequency to the phase detectors 121 and 121A. On the other hand, in each system clock supply device (100, 100A) after the start of operation, a basic clock of a predetermined frequency is generated according to the oscillation of the oscillation unit (131, 131A) is supplied to the counter unit (132, 132A), the counter unit 132, 132A) divides the basic clock to output a system clock necessary for each internal device of the exchange and a reset signal for output timing of the system clock. At this time, the system clocks outputted from the counter units 132 and 132A in the system clock supply apparatuses 100 and 100A are outputted to the phase detectors 121 and 121A, the system clock selectors 160 and 160A, and external terminals. The signal is output to the reset signal selector 140 and 140A and the external terminal, and the system clock and the reset signal are applied to the system clock selector 160A and the reset signal selector 140A of the system clock supply device 100A, respectively. The system clock and the reset signal output through the external terminal of the system clock supply device 100A are applied to the system clock supply device 100A and the reset signal selector 140, respectively.

When the synchronous clock and the system clock are supplied to the phase detectors 121 and 121A of the system clock supply apparatuses 100 and 100A, the phase detectors 121 and 121A detect the phase difference between the supplied synchronous clock and the system clock and detect the phase difference. Digital data is output to the comparison and counting sections 122 and 122A, and the comparison and counting sections 122 and 122A compare the digital data supplied continuously with reference data representing a phase value of a predetermined value, A plurality of data are compared with each other and the data according to the comparison result is output to the D / A units 123 and 123A, respectively. The data output from the comparison and counting units 122 and 122A is D / A-converted in the D / A units 123 and 123A and supplied to the oscillator units 131 and 131A in the form of direct current voltage, and in the oscillator units 131 and 131A. The oscillation frequency of the basic clock oscillating is adjusted according to the magnitude of the DC voltage supplied from the D / A units 123 and 123A. The adjustment of the oscillation frequency is repeated every cycle of the synchronous clock.

Since the system clock supply device 100 is designated as the master and the system clock supply device 100A is designated as the slave at the initial setting, the state control unit 152 of the system clock supply device 100 may reset the signal selection unit 140. To reset the output signal from the counter unit 132 to the counter unit 132, and control the system clock selector 160 to output the system clock from the counter unit 132 to the internal device of the exchanger. Allow output. On the other hand, the state control unit 152A of the system clock supply device 100A controls the reset signal selector 140A so that the reset signal output from the system clock supply device 100 acting as a master is supplied to the counter 132A. The system clock selector 160A is controlled so that the system clock output from the system clock supply device 100 and applied to the system clock selector 160A is output to each internal device of the exchanger. Therefore, the counter unit 132A of the system clock supply device 100A acting as a slave receives a reset signal provided from the system clock supply device 100 acting as a master to adjust the output timing of the system clock, and the oscillator 131A. Since the basic clock oscillation frequency of) is also adjusted by the phase difference between the system clock and the synchronous clock output from the counter unit 132A, the phase correction between the system clock supply devices 100 and 100A acting as the master and the slave is performed by the oscillator ( Both at 131A and at counter 132A.

The roles of the master and slave of the system clock supply apparatuses 100 and 100A are determined by initial settings. If an abnormality occurs in the system clock of the system clock supply apparatus 100 operating as the master, the search unit 151 Notifies the state control unit 152 that there is an abnormality in the system clock, and the state control unit 152 received the notification from the search unit 151 to the state control unit 152A of the system clock supply device 100A operating as a slave. A predetermined master slave selection signal (M / S) is outputted to transfer the master role. In this case, the system clock supply device 100A operates as a master and the system clock supply device 100 operates as a slave.

As described above, the present invention corrects the phase synchronization between the host station and the slave for each cycle of the synchronous clock, and performs phase correction between the master and the slave in the system clock output of the counter and the basic clock oscillation of the oscillator. The clock can be provided to the internal device of the exchanger, and it is not necessary to have an expensive oscillator with high stability, and in the configuration, two system clock supplies in a single unit are redundantly configured for performance and cost. Considering this, it has the most suitable effect in small capacity local exchange.

Claims (6)

In a redundant system clock supply device for supplying a system clock to an internal device of an exchange, a system clock in which phase synchronization is synchronized with a reference clock provided by an upper station exchanger at regular intervals is provided to each internal device and the first external terminal of the exchange. A first system clock supply device (100) for outputting and outputting a reset signal for output timing of the system clock and a master slave selection signal related to master and slave operations to second and third external terminals; The system clock with phase synchronization and output timing adjusted by the reference signal and the reset signal output from the first system clock supply device 100 is generated, and the first system clock supply device 100 is used as the internal device. It supplies the system clock output from the input, and according to the master slave selection signal output from the first system clock supply device 100 of the slave role that can act as the first system clock supply device 100. Redundant system clock supply of the exchanger, characterized in that it comprises a second system clock supply (100A). The system clock supply apparatus of claim 1, wherein the first system clock supply device 100 or the second system clock supply device 100A outputs a synchronization clock of a predetermined frequency to match phase synchronization with a reference clock provided by the host station switch. A synchronous clock generator 110; An oscillation controller 120 which detects a phase difference between the synchronous clock and the system clock output from the synchronous clock generator 110 and outputs a detection result at a predetermined voltage; A system clock generator 130 matching an output timing of the system clock with the reset signal outputting a system clock and a reset signal according to a predetermined voltage of the oscillation controller 120; A reset signal selector 140 which selects one of a reset signal output from the system clock generator 130 and a reset signal output from a relative system clock supply device and applies the selected reset signal to the system clock generator 130; A system clock selector 160 which selects the system clock outputted from the system clock generator 130 and the counterpart system clock and supplies them to the internal device; It includes a main controller 150 for controlling the operation switching to the master or slave and the operation of the synchronization clock generator 110, the reset signal selector 140 and the system clock selector 160 Redundant system clock supply of the exchanger. The method of claim 2, wherein the synchronization clock generator 110 receives a predetermined number of reference clocks provided by the host station switch and selects any reference clock according to a control signal applied from the main controller 150. A reference clock selector 111; And a divider circuit 112 for dividing the reference clock selected by the reference clock selector 111 and outputting a synchronous clock of a predetermined frequency to the oscillation controller 120. . The phase detection data of claim 2, wherein the oscillation controller 120 detects a phase difference between a synchronous clock output from the synchronous clock generator 110 and a system clock output from the system clock generator 130. Phase detection unit 121 for outputting the; A comparison and counting unit 122 for comparing the phase detection data output from the phase detection unit 121 with a predetermined reference value and outputting comparison result data; Redundant system clock supply of the exchanger, characterized in that the D / A unit 123 for outputting a predetermined voltage to the system clock generation unit 130 according to the comparison result data output from the comparison and counting unit 122 . The oscillator of claim 2, wherein the system clock generator (130) comprises: an oscillator (131) for oscillating a clock of a specific frequency according to a magnitude of a predetermined voltage output from the oscillation controller (120); The counter unit 132 divides the clock oscillated by the oscillator 131 to output a system clock and a reset signal, and adjusts the output timing of the system clock according to the reset signal applied from the reset signal selector 140. Redundant system clock supply of the exchanger, characterized in that. According to any one of claims 2, 3, and 5, the main control unit 150, the system clock output from the counter unit 132 of the system clock generation unit 130 to check the system clock A search unit 151 for outputting status information; Controls the selection operation of the reference clock selector 111, the reset signal selector 140, and the system clock selector 160 and selectively selects the master and slave selection signals according to the status information output from the searcher 151. Redundant system clock supply of the exchanger, characterized in that it comprises a state control unit 152 for outputting.