KR0162146B1 - Method of fabricating mosfet - Google Patents

Method of fabricating mosfet Download PDF

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KR0162146B1
KR0162146B1 KR1019950019119A KR19950019119A KR0162146B1 KR 0162146 B1 KR0162146 B1 KR 0162146B1 KR 1019950019119 A KR1019950019119 A KR 1019950019119A KR 19950019119 A KR19950019119 A KR 19950019119A KR 0162146 B1 KR0162146 B1 KR 0162146B1
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metal
polysilicon
manufacturing
gate
high temperature
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KR970003698A (en
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이재동
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김주용
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

고집적 반도체 소자 제조 방법.Highly integrated semiconductor device manufacturing method.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

트랜지스터의 게이트 전극으로 사용되는 폴리실리콘의 저항을 낮게하여 워드 라인이나 상호접속 라인으로 사용하기 위하여 텅스텐(W), 티타늄(Ti), 백금(Pt), 몰리브덴(Mo), 탄탈륨(Ta) 등의 물질이 적용되고 있으나, 게이트 실리사이드 형성 이후의 고온 열공정에 의하여 소자 특성의 열화를 가져오기 때문에 내화성 금속인 텅스텐만이 반도체 제조 공정에 이용되고 있는 실정이나, 반도체 소자가 고집적화되면서 패턴 형성이나 게이트 집적도 등에 많은 제약 사항이 나타나는 문제점을 해결하고자 함.To reduce the resistance of polysilicon used as a gate electrode of a transistor, and to use it as a word line or an interconnect line, tungsten (W), titanium (Ti), platinum (Pt), molybdenum (Mo), tantalum (Ta), etc. Although the material is applied, the tungsten, which is a refractory metal, is used in the semiconductor manufacturing process due to the high temperature thermal process after the gate silicide formation. However, since the semiconductor device is highly integrated, the pattern formation or the gate integration degree is increased. To solve the problem that many restrictions appear on the back.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

폴리실리콘을 원하는 크기로 패턴을 형성하고 소스/드레인 이온 주입 및 고온 열처리 공정을 완료한 다음, 콘택홀을 형성하기 전에 게이트 금속 실리사이드 공정을 진행하므로써, 사용되는 금속의 고온 열공정에 의한 소자의 특성이 열화되는 것을 방지할 수 있는 MOS 트랜지스터 제조 방법을 제공하고자함.Characterization of the device by the high temperature thermal process of the metal used, by patterning the polysilicon to the desired size, completing the source / drain ion implantation and the high temperature heat treatment process, and then performing the gate metal silicide process before forming the contact hole An object of the present invention is to provide a method for manufacturing a MOS transistor that can prevent this deterioration.

4. 발명의 중요한 용도4. Important uses of the invention

고집적 반도체 소자, 특히 MOS 트랜지스터 재조에 이용됨.Used to fabricate highly integrated semiconductor devices, especially MOS transistors.

Description

모스 트랜지스터 제조 방법MOS transistor manufacturing method

제1a도 내지 제1d도는 본 발명에 따라 MOS 트랜지스터를 제조하는 방법의 공정도.1A-1D are process diagrams of a method of manufacturing a MOS transistor in accordance with the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체 기판 2 : 게이트 산화막1 semiconductor substrate 2 gate oxide film

3 : 폴리실리콘 4 : 소스/드레인 영역3: polysilicon 4: source / drain regions

5,7 : 층간 절연막 6 : 금속 실리사이드5,7 interlayer insulating film 6 metal silicide

본 발명은 일반적으로 반도체 소자 제조 방법에 관한 것으로서, 특히 폴리사이드 게이트 전극을 가진 MOS 트랜지스터를 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to methods of manufacturing semiconductor devices, and more particularly to methods of manufacturing MOS transistors having polyside gate electrodes.

트랜지스터의 게이트 전극으로 사용되는 폴리실리콘의 저항을 낮게하여 워드라인이나 상호접속라인으로 사용하기 위하여 텅스텐(W), 티타늄(Ti), 백금(Pt), 몰리브덴(Mo), 탄탈륨(Ta) 등의 물질이 적용되고 있으나, 게이트 실리사이드 형성 이후의 고온 열공정에 의하여 소자 특성의 열화를 가져오기 때문에 내화성 금속인 텅스텐만이 반도체 제조 공정에 이용되고 있는 실정이다. 그러나 반도체 소자가 고집적화되면서 패턴 형성이나 게이트 집적도 등에 많은 제약 사항이 나타나고 있으므로 이용할 수 있는 금속의 종류를 다양화할 필요가 있다.Tungsten (W), titanium (Ti), platinum (Pt), molybdenum (Mo), tantalum (Ta), etc. to lower the resistance of the polysilicon used as the gate electrode of the transistor to be used as a word line or an interconnect line. Although a material is applied, tungsten, which is a refractory metal, is used in a semiconductor manufacturing process because deterioration of device characteristics is caused by a high temperature thermal process after gate silicide formation. However, as semiconductor devices have been highly integrated, many constraints such as pattern formation and gate integration have emerged. Therefore, it is necessary to diversify the types of metals available.

따라서 전술한 문제점을 해결하기 위해 안출된 본 발명은 폴리실리콘을 원하는 크기로 패턴을 형성하고 소스/드레인 이온 주입 및 고온 열처리 공정을 완료한 다음, 콘택홀을 형성하기 전에 게이트 금속 실리사이드 공정을 진행하므로써, 사용되는 금속의 고온 열공정에 의한 소자의 특성이 열화되는 것을 방지할 수 있는 MOS 트랜지스터 제조 방법을 제공하는 것을 목적으로 한다.Therefore, the present invention devised to solve the above-mentioned problem is to form a pattern of polysilicon to a desired size, complete the source / drain ion implantation and high temperature heat treatment process, and then proceed with the gate metal silicide process before forming the contact hole. It is an object of the present invention to provide a method for manufacturing a MOS transistor which can prevent deterioration of characteristics of an element due to a high temperature thermal process of a metal used.

본 발명에 따른 MOS 트랜지스터 제조 방법은, 반도체 기판상에 게이트 산화막과 폴리실리콘을 차례로 증차하고, 사진 식각 공정을 실시하여 폴리실리콘 게이트 전극을 형성하는 단계와, 소스/드레인 이온 주입을 실시하고 열처리 공정을 수행하여 소스/드래인 영역을 형성하는 단계와, 상기 폴리실리콘 게이트 전극을 완전히 덮도록 전체 구조 상부에 제1층간 절연막을 증착하는 단계와, 상기 폴리실리콘 게이트 전극이 노출되도록 블랭킷 식각을 실시하여 평탄화하는 단계와, 전체 구조 상부에 소정의 금속을 증착하는 단계와, 상기 금속과 폴리실리콘이 반응하도록 열처리 공정을 실시하여 금속 실리사이드를 형성하는 단계와, 실리사이드화 되지않은 금속을 식각하여 제거하는 단계 및, 전체 구조 상부에 제2층간 절연막을 증착하는 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a MOS transistor according to the present invention comprises the steps of sequentially increasing a gate oxide film and polysilicon on a semiconductor substrate, performing a photolithography process to form a polysilicon gate electrode, performing source / drain ion implantation, and performing a heat treatment process. Forming a source / drain region, depositing a first interlayer insulating film over the entire structure to completely cover the polysilicon gate electrode, and performing a blanket etching to expose the polysilicon gate electrode Planarizing, depositing a predetermined metal on the entire structure, performing a heat treatment process to react the metal and polysilicon to form a metal silicide, and etching and removing the unsilicided metal. And depositing a second interlayer insulating film over the entire structure. It is characterized by.

이제 본 발명의 MOS 트랜지스터 제조 방법의 한 실시예에 대하여 첨부 도면을 참조하여 보다 상세하게 설명하게 된다. 먼저, 제1A도에 도시된 바와 같이, 반도체 기판(1)상에 게이트 산화막(2)과 게이트용 폴리실리콘을 차례로 증착한 다음, 사진 식각 공정을 통해 폴리실리콘 게이트 전극(3)을 형성한다. 다음에 소스/드레인 이온 주입을 실시하고 열처리 공정을 실시하여, 소스/드레인 영역(4)을 형성한다. 다음에 제1B도에 도시된 바와 같이, 층간 절연막으로 산화막(5)을 증착하고, 블랭킷 식각 공정을 통해 평탄화를 실시한다. 다음에 제1C도에 도시된 바와 같이, 전체 구조 상부에 저항이 비교적 낮은 금속을 증착하고 어닐링 공정을 실시하여, 금속 실리사이드(6)를 형성하고, NH4OH+H2O2+H2O 용액을 이용하여 미반응 금속을 제거한다. 이때, 저항이 비교적 낮은 금속으로는 텅스텐 뿐만 아니라, 예를 들어 티타늄(Ti), 백금(Pt), 몰리브덴(Mo), 탄탈륨(Ta) 등의 금속이 사용될 수 있다. 다음에, 다시 층간 절연막(7)을 증착하면 제1D도에 도시된 바와 같이, 폴리사이드 게이트 전극을 가진 모스 트랜지스터 구조가 형성되게 된다.An embodiment of the MOS transistor manufacturing method of the present invention will now be described in more detail with reference to the accompanying drawings. First, as shown in FIG. 1A, the gate oxide film 2 and the gate polysilicon are sequentially deposited on the semiconductor substrate 1, and then the polysilicon gate electrode 3 is formed through a photolithography process. Next, source / drain ion implantation is performed and a heat treatment step is performed to form the source / drain regions 4. Next, as shown in FIG. 1B, the oxide film 5 is deposited using an interlayer insulating film, and planarized by a blanket etching process. Next, as shown in FIG. 1C, a metal having a relatively low resistance is deposited on the entire structure and subjected to an annealing process to form a metal silicide 6, and NH 4 OH + H 2 O 2 + H 2 O The solution is used to remove unreacted metal. In this case, as the metal having a relatively low resistance, not only tungsten, but also metals such as titanium (Ti), platinum (Pt), molybdenum (Mo), and tantalum (Ta) may be used. Next, when the interlayer insulating film 7 is deposited again, as shown in FIG. 1D, a MOS transistor structure having a polyside gate electrode is formed.

반도체 소자 제조시, 진술한 바와 같은 본 발명에 따라 모스(MOS) 트렌지스터를 제조하므로써, 폴리사이드 게이트 전극 형성을 위해 사용되는 금속의 내화성에 의존하지 않고 고온 열공정에 의한 소자 특성의 열화를 방지할 수 있으며, 따라서, 실리사이드 형성을 위해 사용되는 금속의 종류도 다양화 시킬 수 있다는 장점이 있다.When manufacturing a semiconductor device, by manufacturing the MOS transistor according to the present invention as stated, it is possible to prevent deterioration of device characteristics by high temperature thermal process without depending on the fire resistance of the metal used for forming the polyside gate electrode. Therefore, there is an advantage in that the type of metal used for silicide formation can also be diversified.

Claims (4)

모스(MOS) 트랜지스터를 제조하는 방법에 있어서, 반도체 기판상에 게이트 산화막과 폴리실리콘을 차례로 증착하고, 사진 식각 공정을 실시하여 폴리실리콘 게이트 전극을 형성하는 단계와, 소스/드레인 이온 주입을 실시하고 열처리 공정을 수행하여 소스/드레인 영역을 형성하는 단계와, 상기 폴리실리콘 게이트 전극을 완전히 덮도록 전체 구조 상부에 제1층간 절연막을 증착하는 단계와, 상기 폴리실리콘 게이트 전극이 노출되도록 블랭킷 식각을 실시하여 평탄화하는 단계와, 전체 구조 상부에 소정의 금속을 증착하는 단계와, 상기 금속과 폴리실리콘이 반응하도록 열처리 공정을 실시하여 금속 실리사이드를 형성하는 단계와, 실리사이드화 되지 않은 금속을 식각하여 제거하는 단계 및, 전체 구조 상부에 제2층간 절연막을 증착하는 단계를 포함해서 이루어진 모스 트랜지스터 제조 방법.A method of manufacturing a MOS transistor, comprising: depositing a gate oxide film and polysilicon on a semiconductor substrate in turn, performing a photolithography process to form a polysilicon gate electrode, and performing source / drain ion implantation Performing a heat treatment process to form a source / drain region, depositing a first interlayer insulating film over the entire structure to completely cover the polysilicon gate electrode, and performing a blanket etching to expose the polysilicon gate electrode Forming a metal silicide by planarizing, depositing a predetermined metal on the entire structure, performing a heat treatment process to react the metal and polysilicon, and etching and removing unsilicided metal. And depositing a second interlayer insulating film over the entire structure. MOS transistor manufacturing method. 제1항에 있어서, 상기 제1층간 절연막은 산화막인 것을 특징으로 하는 모스 트렌지스터 제조 방법.The method of claim 1, wherein the first interlayer insulating film is an oxide film. 제1항에 있어서, 상기 소정의 금속은 텅스텐(W), 티타늄(Ti), 백금(Pt), 몰리브덴(Mo), 탄탄륨(Ta) 중 어느 한 금속으로 이루어진 것을 특징으로 하는 모스 트랜지스터 제조 방법.The method of claim 1, wherein the predetermined metal is made of any one of tungsten (W), titanium (Ti), platinum (Pt), molybdenum (Mo), and tantalum (Ta). . 제3항에 있어서, 상기 실리사이드화 되지 않은 금속을 식각하여 제거하는 단계는 NH4OH+H2O2+H2O 용액을 이용하여 실시되는 것을 특징으로 하는 모스 트랜지스터 제조 방법.The method of claim 3, wherein the removing of the non-silicided metal by etching is performed using NH 4 OH + H 2 O 2 + H 2 O solution.
KR1019950019119A 1995-06-30 1995-06-30 Method of fabricating mosfet KR0162146B1 (en)

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