KR0161852B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR0161852B1 KR0161852B1 KR1019950000270A KR19950000270A KR0161852B1 KR 0161852 B1 KR0161852 B1 KR 0161852B1 KR 1019950000270 A KR1019950000270 A KR 1019950000270A KR 19950000270 A KR19950000270 A KR 19950000270A KR 0161852 B1 KR0161852 B1 KR 0161852B1
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- oxide film
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- single crystal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 식각기술을 이용하여 실리콘기판내에 매몰산화막을 형성하여 SOI구조 형성을 위한 활성영역을 갖춘 기판을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and to a method of forming a buried oxide film in a silicon substrate using an etching technique to form a substrate having an active region for forming an SOI structure.
본 발명은 단결정 실리콘웨이퍼상에 산화막을 형성하는 공정과, 상기 산화막을 선택적으로 건식식각하여 소자가 형성될 활성영역상에만 남기는 공정, 상기 산화막의 식각에 의해 노출되는 기판부위를 건식식각하여 소정깊이의 트렌치를 형성하는 공정, 상기 트렌치 하부의 양단부위에 국부적인 이온주입영역을 형성하는 공정, 상기 산화막을 제거하는 공정, 상기 단결정 실리콘웨이퍼를 습식식각하는 공정, 및 산화공정을 실시하여 상기 트렌치 하부영역의 식각되어진 부분과 그 트렌치에 이웃하는 트렌치 하부영역에서 성장된 산화막이 서로 연결되도록 하여 매몰산화막을 형성하는 공정을 포함하는 반도체소자의 제조방법을 제공한다.The present invention provides a process of forming an oxide film on a single crystal silicon wafer, a process of selectively dry etching the oxide film and leaving only the active region on which the device is to be formed, and a predetermined depth by dry etching the substrate portion exposed by the etching of the oxide film. Forming a trench of the trench, forming a local ion implantation region at both ends of the lower portion of the trench, removing the oxide film, wet etching the single crystal silicon wafer, and performing an oxidation process. It provides a method for manufacturing a semiconductor device comprising the step of forming a buried oxide film by connecting the etched portion and the oxide film grown in the trench lower region adjacent to the trench with each other.
Description
제1도 내지 제3도는 종래의 SOI구조 형성방법을 도시한 도면.1 to 3 show a conventional method of forming an SOI structure.
제4도는 본 발명의 일실시예에 의한 SOI구조 형성방법을 도시한 공정순서도.4 is a process flowchart showing a method for forming an SOI structure according to an embodiment of the present invention.
제5도는 본 발명의 다른 실시예에 의한 SOI구조 형성방법을 도시한 공정순서도.5 is a process flowchart showing a method of forming an SOI structure according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 단결정 실리콘기판 2 : 산화막1: single crystal silicon substrate 2: oxide film
5 : 포토레지스트 6, 12 : 트렌치5: photoresist 6, 12: trench
7 : 경사이온주입 8, 11 : 이온주입영역7: gradient ion implantation 8, 11 ion implantation region
9 : 매몰산화막9: investment oxide film
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 3차원 SOI(Silicon On Insulator)기술을 이용한 MOSFET의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MOSFET using a three-dimensional silicon on insulator (SOI) technology.
절연층상에 실리콘 단결정박막을 형성하고 그위에 MOSFET등과 같은 반도체소자를 형성하는 기술이 SOI기술이다.SOI technology is a technique of forming a silicon single crystal thin film on an insulating layer and forming a semiconductor device such as a MOSFET thereon.
SOI구조는 완전한 소자 분리구조를 실현할 수 있어 고속동작이 가능하며, 또한 pn접합 분리구조에서 나타나는 기생 MOS트랜지스터나 기생 바이폴라 트랜지스터등의 능동적 기생효과가 없기 때문에 래치업(latch up) 현상이나 소프트 에러(soft error) 현상이 없는 CMOS회로를 구성할 수 있다는 장점을 가지고 있다.Since the SOI structure can realize a complete device isolation structure, high-speed operation is possible, and there is no active parasitic effect such as parasitic MOS transistor or parasitic bipolar transistor shown in the pn junction isolation structure, so the latch up phenomenon or soft error ( soft error) has the advantage of being able to configure the CMOS circuit without phenomenon.
종래의 SOI구조의 MOSFET 제조방법에는 여러가지가 있다.There are many conventional methods for fabricating MOSFETs with SOI structures.
첫째, 제1도에 도시된 바와 같이 실리콘기판(1)위에 산화막(2)을 형성하고 이 위에 다결정실리콘(3)을 증착한 다음, 레이저나 RTP(Rapid Thermal Process)장치를 이용하여 다결정실리콘을 열처리하여 단결정실리콘(3')으로 만들어 이 위에 소자를 제작하는 방법이 그중 하나이다.First, as shown in FIG. 1, an oxide film 2 is formed on a silicon substrate 1, polycrystalline silicon 3 is deposited thereon, and then polycrystalline silicon is formed using a laser or a rapid thermal process (RTP) apparatus. One method is to fabricate a device thereon by heat-treating it into single crystal silicon 3 '.
둘째, 제2도에 도시된 바와 같이 실리콘기판(1)에 높은 에너지로 실리콘이온을 주입시켜 산화를 행하여 매몰 산화막(2)을 형성한 후, 상기 실리콘기판상에 소자를 형성하는 SIMOX(Seperation by implanted Oxygen) 방법이 있다.Second, as shown in FIG. 2, the silicon substrate 1 is implanted with high energy into silicon ions to oxidize to form a buried oxide film 2, and then a SIMOX (Seperation by) is formed on the silicon substrate. implanted Oxygen).
셋째로는 제3도에 도시된 바와 같이 두장의 웨이퍼(1A, 1B)를 산화방법을 이용하여 산화막(2)에 의해 본딩(bonding)한 다음 그위에 소자를 형성하는 웨이퍼본딩방법이 있다.Third, as shown in FIG. 3, there is a wafer bonding method in which two wafers 1A and 1B are bonded by an oxide film 2 using an oxidation method and then an element is formed thereon.
그러나 상기 종래 기술들에는 다음과 같은 문제점이 존재한다.However, the following problems exist in the prior arts.
먼저, 첫번째 방법은 실제로 다결정실리콘을 열처리를 통해서 완전한 단결정실리콘으로 만들기가 어려운 문제가 있고, 두번째 방법은 단결정실리콘과 같은 효과를 기대할 수 있으나 SIMOX웨이퍼 가격이 매우 비싸 실용화에 어려운 문제가 있으며, 세번째 방법은 웨이퍼 단가도 문제가 되고 실제로 웨이퍼를 본딩하는데 신뢰성이 문제가 되고 있어 널리 사용되지 못하는 문제점이 있다.First, the first method has a problem that it is difficult to make the polycrystalline silicon completely monocrystalline silicon through heat treatment, the second method can be expected to have the same effect as the single crystal silicon, but the SIMOX wafer price is very expensive, difficult to practical use, the third method Silver wafer price is also a problem, and reliability in bonding the wafer is actually a problem that is not widely used.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 식각기술을 이용하여 실리콘기판내에 매몰산화막을 형성하여 SOI구조 형성을 위한 활성영역을 갖춘 기판을 형성하는 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming a substrate having an active region for forming an SOI structure by forming a buried oxide film in a silicon substrate using an etching technique.
상기 목적을 달성하기 위한 본 발명의 반도체소자 제조방법은 단결정 실리콘 웨이퍼상에 산화막을 형성하는 공정과, 상기 산화막을 선택적으로 건식식각하여 소자가 형성될 활성영역상에만 남기는 공정, 상기 산화막의 식각에 의해 노출되는 기판부위를 건식식각하여 소정깊이의 트렌치를 형성하는 공정, 상기 트렌치 하부의 양단부위에 국부적인 이온주입영역을 형성하는 공정, 상기 산화막을 제거하는 공정, 상기 단결정실리콘웨이퍼를 습식식각하는 공정, 및 산화공정을 실시하여 상기 트렌치 하부영역의 식각되어진 부분과 그 트렌치에 이웃하는 트렌치 하부영역에서 성장된 산화막이 서로 연결되도록 하여 매몰산화막을 형성하는 공정을 포함한다.The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming an oxide film on a single crystal silicon wafer, and selectively dry etching the oxide film to leave only on the active region where the device is to be formed, the etching of the oxide film Forming a trench having a predetermined depth by dry etching the exposed substrate, forming a local ion implantation region at both ends of the lower portion of the trench, removing the oxide layer, and wet etching the single crystal silicon wafer. And forming a buried oxide film by performing an oxidation process so that the etched portion of the lower trench region and the oxide film grown in the trench lower region adjacent to the trench are connected to each other.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제4도에 본 발명에 의한 SOI구조의 MOSFET 제조를 위한 활성영역 및 매몰산화막을 갖춘 기판 형성방법을 공정순서에 따라 도시하였다.4 shows a method of forming a substrate having an active region and a buried oxide film for producing a MOSFET having an SOI structure according to the present invention in accordance with the process sequence.
먼저, 제4도(a)에 도시된 바와 같이 단결정실리콘기판(1)상에 산화막(2)을 형성하고 이 위에 포토레지스트를 도포한 후, 이를 선택적으로 노광 및 현상하여 소자가 형성될 활성영역상에만 남도록 포토레지스트(5)패턴을 형성한다.First, as shown in FIG. 4 (a), an oxide film 2 is formed on a single crystal silicon substrate 1, a photoresist is applied thereon, and then selectively exposed and developed to an active region in which an element is to be formed. The photoresist 5 pattern is formed so as to remain only on the image.
이어서 제4도(b)에 도시된 바와 같이 상기 포토레지스트(5)패턴을 마스크로 하여 상기 산화막(2)을 건식식각한 후, 이에 따라 노출되는 기판부위를 건식식각하여 소정깊이의 트렌치(6)를 형성한다.Subsequently, as illustrated in FIG. 4B, the oxide layer 2 is dry-etched using the photoresist 5 pattern as a mask, and then the exposed substrate portion is dry-etched to provide a trench of a predetermined depth. ).
다음에 제4도(c)에 도시된 바와 같이 상기 산화막(2)을 마스크로 이용하여 상기 단결정실리콘웨이퍼를 회전시키면서 경사 이온주입(tilt implant)(7)을 실시하여 상기 트렌치 하부의 양단부위에 국부적인 이온주입영역(8)을 형성한다.Next, as shown in FIG. 4 (c), a tilt implant (7) is performed while the single crystal silicon wafer is rotated using the oxide film 2 as a mask so as to be localized at both ends of the lower portion of the trench. Phosphorus ion implantation region 8 is formed.
이어서 제4도(d)에 도시된 바와 같이 상기 산화막(2)을 제거한 후, 습식식각을 실시하면 상기 이온주입영역에서 식각이 더 빨리 이루어져 트렌치 하부의 양단쪽으로 파여 들어간 형태가 얻어지게 된다.Subsequently, as shown in FIG. 4D, when the oxide film 2 is removed and wet etching is performed, etching is performed faster in the ion implantation region, thereby forming a form penetrating into both ends of the lower portion of the trench.
다음에 제4도(e)에 도시된 바와 같이 산화공정을 실시하면 이에 따라 형성되는 매몰산화막(9)에 의해 상기 트렌치 하부 양단의 파여 들어간 부분이 서로 연결됨으로써 매몰산화막(9)이 형성되고, 트렌치가 형성되지 않은 기판부위는 활성영역으로 남게 된다.Next, when the oxidation process is performed as shown in FIG. 4 (e), the buried oxide film 9 is formed by the buried oxide film 9 formed accordingly to connect the trenched portions at both ends of the lower trench, so that the buried oxide film 9 is formed. The portion of the substrate where the trench is not formed remains as an active region.
이때의 산화 공정에서, 트렌치의 모든 부분에서 산화 속도가 동일하므로 트렌치 하부 양단의 파여 들어간 부분이 먼저 이웃하는 트렌치의 산화막이 먼저 연결되어 활성 영역이 상부에 위치하는 매몰 산화막(9)이 형성된다.In the oxidation process at this time, since the oxidation rate is the same in all parts of the trench, the oxide films of the trenches adjacent to the trenches at both ends of the trench are first connected to form a buried oxide film 9 in which the active region is located above.
그리고 도면에 도시하지 않았지만, 실제 소자 제조 공정을 진행하기 위해서는 통상의 에치백 또는 CMP(Chemical Mechanical Polishing) 등의 공정으로 기판 표면의 산화막을 제거하여 활성 영역의 표면을 노출시키게 된다.Although not shown in the drawing, in order to proceed with the actual device fabrication process, the surface of the active region is exposed by removing the oxide film on the surface of the substrate by a process such as a conventional etch back or chemical mechanical polishing (CMP).
상기와 같이 형성된 활성영역에 일반적인 NMOS공정을 이용하여 MOSFET를 제작하면, 실리콘기판-매몰산화막-소자영역의 3차원 SOI구조의 MOSFET를 제조할 수 있게 된다.If the MOSFET is fabricated using the general NMOS process in the active region formed as described above, it is possible to manufacture a MOSFET having a three-dimensional SOI structure in the silicon substrate-buried oxide film-device region.
다음에 본 발명의 다른 실시예를 제5도를 참조하여 설명한다.Next, another embodiment of the present invention will be described with reference to FIG.
먼저, 제5도(a)에 도시된 바와 같이 단결정 실리콘기판(1)에 높은 에너지로 이온주입을 행하여 제5도(b)에 도시된 바와 같이 기판내 소정깊이에 이온주입영역(11)을 형성한 후, 기판 소정부분을 상기 이온주입영역(11)을 포함하는 깊이까지 선택적으로 건식식각하여 트렌치(12)를 형성한다. 이때, 상기 트렌치(12)가 형성되지 않은 기판부분이 소자형성영역인 활성영역이 된다.First, as shown in FIG. 5 (a), ion implantation is performed at high energy into the single crystal silicon substrate 1, and as shown in FIG. 5 (b), the ion implantation region 11 is formed at a predetermined depth in the substrate. After forming, the substrate 12 is selectively dry-etched to a depth including the ion implantation region 11 to form the trench 12. In this case, the portion of the substrate where the trench 12 is not formed becomes an active region that is an element formation region.
다음에 제5도(c)에 도시된 바와 같이 습식식각을 행하게 되면 상기 이온 주입영역(11)의 식각이 빠르게 진행되어 트렌치(12) 하부의 양단쪽으로 파여 들어간 형태가 얻어지게 된다.Next, when wet etching is performed as illustrated in FIG. 5C, the ion implantation region 11 is rapidly etched to obtain a form that is dug into both ends of the lower portion of the trench 12.
다음에 제5도(d)에 도시된 바와 같이 산화공정을 실시하면 이에 따라 형성되는 매몰산화막(9)에 의해 상기 트렌치 하부 양단의 파여 들어간 부분이 서로 연결됨으로써 매몰산화막(9)이 형성되고, 트렌치가 형성되지 않은 기판부위는 활성영역으로 남게 된다.Next, as shown in FIG. 5 (d), when the oxidation process is performed, the buried oxide film 9 is formed by the buried oxide film 9 thus formed, which is connected to each other in the trench. The portion of the substrate where the trench is not formed remains as an active region.
이때의 산화 공정에서, 트렌치의 모든 부분에서 산화 속도가 동일하므로 트렌치 하부 양단의 파여 들어간 부분이 먼저 이웃하는 트렌치의 산화막이 먼저 연결되어 활성 영역이 상부에 위치하는 매몰 산화막(9)이 형성된다.In the oxidation process at this time, since the oxidation rate is the same in all parts of the trench, the oxide films of the trenches adjacent to the trenches at both ends of the trench are first connected to form a buried oxide film 9 in which the active region is located above.
그리고 도면에 도시하지 않았지만, 실제 소자 제조 공정을 진행하기 위해서는 통상의 에치백 또는 CMP(Chemical Mechanical Polishing) 등의 공정으로 기판 표면의 산화막을 제거하여 활성 영역의 표면을 노출시키게 된다.Although not shown in the drawing, in order to proceed with the actual device fabrication process, the surface of the active region is exposed by removing the oxide film on the surface of the substrate by a process such as a conventional etch back or chemical mechanical polishing (CMP).
상기와 같이 형성된 활성영역에 일반적인 NMOS공정을 이용하여 MOSFET를 제작하면, 실리콘기판-매몰산화막-소자영역의 3차원 SOI구조의 MOSFET를 제조할 수 있게 된다.If the MOSFET is fabricated using the general NMOS process in the active region formed as described above, it is possible to manufacture a MOSFET having a three-dimensional SOI structure in the silicon substrate-buried oxide film-device region.
이상 상술한 바와 같이 본 발명에 의하면, SOI소자를 제작하는데 있어서 완전한 단결정 실리콘기판위에 소자를 제작할 수 있게 되므로 단결정실리콘소자와 SOI소자의 장점을 함께 가질 수 있으며, 종래의 방법에 비해 간단한 제작공정에 의해 소자를 제조할 수 있게 된다.As described above, according to the present invention, since the device can be fabricated on a complete single crystal silicon substrate in fabricating the SOI device, the device can have both advantages of the single crystal silicon device and the SOI device, This makes it possible to manufacture the device.
또한 본 발명의 매몰산화막 형성방법으로 LOCOS(Local Oxidation of Silicon)등과 같은 기존의 반도체장치의 소자격리기술을 대체하는 것도 가능하다.In addition, it is possible to replace the device isolation technology of the existing semiconductor device such as LOCOS (Local Oxidation of Silicon) by the method of forming a buried oxide film of the present invention.
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