KR0156136B1 - Automatic data strobing device for digital magnetic recording/reproducing system - Google Patents

Abstract

The present invention relates to an automatic data strobing apparatus of a digital magnetic recording and reproducing system capable of latching data at an optimum point of a data latch.

In the prior art, since the data strobing point is fixed and the amplitude of the input signal, timing jitter, and incomplete equalization cannot be absorbed by the fixed strobing point, the maximum BER of the entire system cannot be obtained. Therefore, the present invention provides a data extractor for extracting data from an output of an equalizer, a clock component extractor for extracting a clock component from an output of the data extractor, and a clock component according to a phase comparison result by comparing the output of the clock component extractor. And a latch for latching and outputting the output of the data extraction section with an output clock of the PLL. The digital magnetic recording and reproducing system comprising: a phase latch for comparing the output clock of the PLL and data of the data extraction section again; A data strobing point control unit is further provided to find the optimal point of the data and latch the data so that the data strobe point is centered in the eye pattern even if the data is shaken, thereby increasing the BER of the system even if the data is shaken. It would be.

Description

Automatic Data Strobing Device of Digital Magnetic Recording and Reproduction System

1 is a block diagram of a reproduction portion of a conventional digital magnetic recording and reproducing system.

FIG. 2A is a circuit diagram of the data extraction unit of FIG.

(b) is a circuit diagram of the clock component extraction section of FIG.

3 is a waveform of the operation of FIG.

4 is a block diagram of an automatic data strobe apparatus of a digital magnetic recording and reproducing system according to the first embodiment of the present invention.

5 is a circuit diagram of the waveform shaping unit of FIG.

6 is a principle vector diagram of signal synthesis of the waveform shaping unit of FIG.

7 is an operation waveform diagram of FIG.

8 is a block diagram of a second embodiment of the present invention.

9 is a block diagram of a third embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

100: data strobe point control unit 101: waveform shaping unit

102, 112, 121: phase comparison unit 103, 113, 122: filter

111: shift register MUX1: multiplexer

ADC1: Analog-to-Digital Converter TR1-TR9: Transistor

The present invention relates to an automatic data strobing apparatus of a digital magnetic recording and reproducing system, and more particularly, to automatic data strobing of a digital magnetic recording and reproducing system capable of automatically latching data in the center of an eye pattern. Relates to a device.

In general, when the data is reproduced in the magnetic recording medium and passed through the equalizer and observed with an oscilloscope or the like, it is observed as an eye-shaped waveform, which is called an eye pattern.

1 shows a block diagram of a reproduction part of a general digital magnetic recording / reproducing system, which includes a magnetic recording medium 1, a reproduction amplifier 2, an equalizer 3, a data extractor 4, and a clock component. Phase Locked Loop (PLL), Delay Section 9, and Latch 10 consisting of an extraction section 5, a phase comparator 6, a loop filter 7, and a voltage controlled oscillator (hereinafter referred to as VCO) 8 It consists of.

Since the output of the magnetic recording medium 1, i.e., the disk or the tape, is a small signal, it is amplified by the reproduction amplifier 2, and then the frequency characteristic is corrected through the equalizer 3.

The output of the equalizer 3 is input to the data extracting section 4, and the ternary determination is performed by the comparators COMP1, COMP2 and OR gate OR1 of FIG.

That is, the comparator COMP1 compares the threshold value TH1 determined by the input and the variable resistor VR1, that is, the comparison level. In the comparator COMP2, the input is inverted by the inverter INV1 and the variable is changed. The threshold value TH1 determined by the resistor VR1 is compared, and then is ORed at the OR gate OR1 to be output.

If the input of the comparator COMP1 is smaller than the threshold value TH1, the output of the comparator COMP1 becomes high and the output of the comparator COMP1 becomes high because the value of the non-inverting input terminal (+) is greater than that of the inverting input terminal (−). Becomes

When the value of the inverting input terminal (-) is smaller than the value of the non-inverting input terminal (+), the output becomes high and vice versa, and when the output of the comparator COMP1 becomes high, The comparator COMP2 outputs low by the inverter INV1. When the output of the comparator COMP1 goes low, the comparator COMP2 outputs high by the inverter INV1. The output is 1 when the input is ± 1.

That is, the data extracting unit 4 has a three-value determination circuit as shown in FIG. 2 and outputs ± 1 as 1 and 0 as.

The output of the data extractor 4 is input to the clock component extractor 5 and is delayed by a half cycle of the clock in the delay unit 5a of FIG. Through the clock component is extracted.

That is, in FIG. 3, (a) is the output of the data extraction unit 4, (b) is the output of the delay unit 5a, and (c) is the output of the exclusive unit ora geek EX-OR ₁ . It can be seen that the clock component is obtained by the output.

In the region where the output of the clock component extractor 5 is high, the output of the VCO 8 and the phase comparator 6 are phase-compared, and then the feedback loops of the loop filter 7 and the VCO 8 are used. The clock component and the output (clock) of the VCO 8 are locked.

The relationship at this time is as shown in Figs. 3 (c) and (d). The delay of the VCO 8 is delayed through the delay unit 9 so that the latching clock is applied to the center of the data (the center of the eye pattern). Then, the data is latched and outputted by this delayed clock (Fig. 3 (e)) (Fig. 3 (f)).

However, the conventional technique described above has a fixed data strobe point, a static error of the PLL, a delay caused by a regenerative capacitor on the PCB, a delay caused by wiring, a delay caused by a circuit element, an amplitude variation of an input signal, Timing jitter, incomplete equalization, and the like could not be absorbed by the fixed strobing point, resulting in the maximum bit error rate (BER) of the entire system.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to compare the data and the clock again, so that the data strobe point is located in the center of the eye pattern even if the data is shaken. In providing an ice device.

A feature of the present invention for achieving this object is to phase the data extraction section for extracting data from the output of the equalizer, a clock component extraction section for extracting clock components from the output of the data extraction section, and an output of the clock component extraction section. A digital magnetic recording / playback system comprising: a PLL for outputting a clock component according to a phase comparison result; and a latch for latching and outputting an output of the data extraction section with an output clock of the PLL. The data strobing device of the digital magnetic recording and reproducing system is further provided with a data strobing point adjusting unit for automatically comparing the data of the extracting unit to find the optimum point of the data latch and latching the data.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First of all, the present invention includes a data strobing point adjusting unit to adjust the data strobing point in the center of the eye pattern even when data is shaken. Each embodiment will be described below.

Example 1

4 is a block diagram according to a first embodiment of the present invention, wherein the data strobing point adjusting unit 100 is disposed between the PLL and the latch 10 of the reproducing unit of the general digital magnetic recording and reproducing system as shown in FIG. Is further provided, and the same reference numerals are used for the same parts as in the prior art.

The data strobing point adjusting unit 100 includes a waveform shaping unit 101 for shaping a signal whose output of the PLL is delayed through the delay unit 9, an output of the waveform shaping unit 101, and a data extracting unit ( And a filter 103 for filtering the output of the phase comparing unit 102 and feeding back to the waveform shaping unit 101. FIG.

As shown in FIG. 5, the waveform shaping unit 101 includes transistors TR1 and TR2 to which an output of the delay unit 9 is input to a base terminal, and an emitter stage includes the transistors TR1, An emitter terminal is connected to the transistor terminals TR3 and TR4 that are connected to the emitter terminal of TR2 and the base terminals are connected to each other to receive a driving voltage, and that the emitter terminal is connected to the collector terminals of the transistors TR1 and TR3. An emitter stage is connected to the collector terminals of the transistors TR5 and TR6 to which the driving voltages are supplied, and the output voltage of the phase comparator 102 is connected to the base terminal of the filter 103. The collector stage is provided with transistors TR7 and TR8 connected to the collector stages of the transistors TR5 and TR6 to output waveform shaping outputs.

In the first embodiment of the present invention configured as described above, the operation from the magnetic recording medium 1 to the PLL is the same as in the prior art, and thus the description is weak.

When the output of the VCO 8 is viewed in a phase concept using a plurality of delay elements, when the output of the VCO 8 is →, the? And? Signals are delayed by ± 45 from the delay unit 9.

When the signals delayed through the delay unit 9 are input to the base terminals of the transistors TR1 and TR2 of the waveform shaping unit 101, the collector terminals of the transistors TR1 to TR4 are respectively ↖, ↘, ↗ and ↙ signals appear.

When the output of the waveform shaper 101 is phase compared with the output of the data extractor 4 by the phase comparator 102 and there is no phase error, the output Vout bar adds? And? , V and ↘ signal are added to output Vout, and ↓ signal is synthesized. Here, the synthesis principle of each signal follows the vector diagram of FIG.

When the error voltage that is the phase comparison result of the whisping comparator 102 is changed, the phases of the Vout and Vout bars are changed as shown in (b) and (c) of FIG. 6. In other words, the delay is changed.

On the other hand, what is associated with the eye pattern is the data of the data extraction section 4, and the data is compared with the output of the waveform shaping section 101 and the phase comparison section 102, where the waveform shaping section is located at the center of the data. If the output of 101 is located at the center, the phase comparison error is 0. Otherwise, the phase comparison error is displayed as a + or-value, and the data extraction unit 4 is outputted from the waveform shaping unit 101 according to the phase comparison result. Output data is latched by the latch 10 and outputted.

7 is a waveform diagram of each part of FIG. 4, (a) is an output of the data extraction unit 4, (b) is a clock component, and (c) is an output clock of the VCO (8). , (d) is the r signal waveform, (e) is the r signal waveform, and (f) is the r signal waveform with the r and r signals added.

That is, the present invention is to obtain the ↓ signal by adding the ↙ and ↘ signal, it is possible to place the strobing point in the center of the data as shown by the ↙ + ↘ = ↓ waveform of FIG.

Example 2

8 shows a block diagram according to a second embodiment of the present invention, except that the data strobing point adjusting unit 100 is the same as the first embodiment, and the delay unit 9 is not configured. Do not.

The data strobing point controller 100 includes a shift register 111 for shifting the output of the VCO 8, a multiplexer MUX1 for multiplexing the output of the shift register 111, and the multiplexer MUX1. A phase comparator 112 for phase comparison of the output of the clock component extractor 5 and a filter 113 for filtering the output of the phase comparator 112, and an output of the filter 113. It is composed of an analog-to-digital converter (ADC1) for converting into a digital signal to control the multiplexing of the multiplexer (MUX1).

In the second embodiment of the present invention configured as described above, the operation from the magnetic recording medium 1 to the PLL is the same as in the prior art, and thus the description is weak.

The output of the VCO 8 is input to the shift register 111, and the output of the shift register 111 is input to the multiplexer MUX1 to be output as a clock.

In addition, the shift register 111 may use a delay element. However, the delay value of the delay should be a constant value, for example, there are several delays such as 1 ns, 2 ns, 3 ns, .... 10 ns, which is selected and selected by each multiplexing switch of the multiplexer (MUX1). The signal is used as the clock.

The clock and the output of the clock component extracting section 5 are compared in phase by the phase comparing section 112, and the phase comparison is performed only in a region where the clock component is high.

This coincides with the principle of the PLL, and the PLL portion synchronizes the data and the clock of the VCO 8 as a whole, and the data strobing point controller 100 of the present invention performs fine adjustment.

On the other hand, the output of the phase comparison unit 112 is filtered through the filter 113, and then converted into a digital signal through the analog-to-digital converter ADC1 to switch the multiplexing switch of the multiplexer MUX1 to this digital value. To control.

Therefore, the clock output of the multiplexer MUX1 causes the output of the clock component extraction unit 5 to be in the center of the data, and the output data of the data extraction unit 4 is latched by the latch 10 using the clock. Will print

Example 3

9 is a block diagram according to a third embodiment of the present invention, except for the data strobing point adjusting unit 100, the rest of which is the same as the second embodiment.

The data strobing point controller 100 may adjust the output of the resistor R10 and the variable capacitance diode D10 and the output of the resistor R10 and the variable capacitance diode D10 to adjust the output delay amount of the VCO 8. A phase comparator 121 for comparing a phase with an output of the clock component extractor 5, and a filter 122 for filtering the output of the phase comparator 121 to feed back to the variable capacitance diode D10. do.

In the third embodiment of the present invention configured as described above, the waveform of the output of the VCO 8 is delayed by the low pass filter composed of the resistor R10 and the variable capacitance diode D100.

The delayed signal is compared with the output of the clock component extractor 5 and the phase comparator 121, and then smoothed by the filter 122 to change the value of the variable capacitance diode D10.

Therefore, when the value of the variable capacitor diode D10 is changed, the delay amount of the low pass filter is changed. Therefore, the data component that is the output of the data extractor 4 is latched by the delay output of the resistor R10 and the variable capacitor diode D10. The final output to the data.

As described above, the present invention compares the data and the clock once again to find the optimal point of the data latch even if the data is shaken, and latches the data to output the data strobe point. This improves the overall system BER.

Claims (4)

In the digital magnetic recording and reproducing system, a data extraction section for extracting data, a PLL section for outputting a clock signal from the output of the data extraction section, and data of the output and the data extraction section of the PLL are compared in phase to determine an optimal point of the data latch. A data strobing point adjusting unit to search for; a waveform shaping unit for waveform shaping the signal delayed by the output of the PLL; a phase comparing unit for phase comparison between the output of the waveform shaping unit and the output of the data extracting unit; And a filter for feeding back to the waveform shaping unit by filtering the digital data recording and reproducing apparatus. 2. The waveform generator of claim 1, wherein the waveform shaping unit is connected to the first and second transistors to which the delay output of the PLL is input to the base end, the emitter end is connected to the emitter end of the first and second transistors, and the base end is connected to each other. And fifth and sixth transistors connected to the third and fourth transistors receiving the driving voltage, the emitter terminal is connected to the collector terminals of the first and third transistors, and the driving voltage is supplied to the base terminals. The emitter stage is connected to the collector terminal of the fourth transistor, the output voltage of the phase comparator is supplied to the base terminal through the filter, and the collector terminal is connected to the collector terminals of the fifth and sixth transistors, respectively, to output waveform shaping output. 7. An automatic data strobing device for a digital magnetic recording and reproducing system, comprising: seventh and eighth transistors. The phase shifting circuit of claim 1, wherein the data strobing point adjuster phase-shifts a shift register for shifting the output of the PLL, a multiplexer for multiplexing the output of the shift register, and an output of the multiplexer and an output of a clock component extractor. A comparator, a filter for filtering the output of the phase comparator, and an analog-to-digital converter for converting the output of the filter into a digital signal to control multiplexing of the multiplexer. Ice equipment. 2. The phase comparison circuit of claim 1, wherein the data strobing point controller is configured to compare a phase of a resistor and a variable capacitor diode that adjusts an output delay amount of the PLL, and an output of the resistor and the variable capacitor diode to an output of the clock component extractor. And a filter for filtering the output of the phase comparator and feeding back to the variable capacitance diode.