JP2001143405A - Signal extracting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize a zero-phase start which is higher in precision than conventional by a signal extracting circuit equipped with a PLL circuit. SOLUTION: A 1st comparator 9 compares an inputted analog signal Input with its center value voltage Vref1 and a ZPS circuit 6 receives its output S2 and outputs a start signal SZ. A 2nd comparator 5 compares the analog signal Input with a prescribed voltage Vref2. A delay and delay measuring means 7 measures delays from the transition of the output of a 3rd comparator 22 to the transition of the output S2 of the 2nd comparator 5 when it operates as a delay measuring means, and delays the start signal SZ by the time measured when it operated as the delay measuring means and outputs a control signal SG of a VCO 3, when it operates as a delay means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal extraction circuit using a phase locked loop, and more particularly to a technique relating to a zero phase start for eliminating an initial phase error.

[0002]

2. Description of the Related Art A phase locked loop (hereinafter abbreviated as "PLL") is a circuit for matching the phase of an input signal with the phase of a VCO. Since the PLL is a feedback loop system, it requires a phase acquisition time of about several tens to several hundreds of cycles depending on its performance. For some applications, it is important to make this pull-in time as short as possible.

A good example is a read channel circuit for reading a signal from a disk. The read channel circuit first synchronizes the disk signal with the VCO using a synchronization signal pattern written on the disk, and then reads the user data written after the synchronization signal pattern with the synchronized VCO signal. Here, if it takes time to lock the PLL, it is necessary to write more synchronization signal patterns on the disk, which means that the area of the user data is reduced. Therefore, in order to increase the capacity of the disk medium, it is necessary to lock the PLL in as short a time as possible.

FIG. 12 is a diagram showing a configuration for realizing a zero-phase start (hereinafter abbreviated as “ZPS”) as a conventional digital PLL in order to shorten the pull-in time of the PLL. The system shown in FIG.
And a comparator 11 for adjusting the timing
And a ZPS circuit 12.

[0005] In the PLL circuit 5, the A / D converter 1 uses a clock signal CLOCK generated by a voltage controlled oscillator (hereinafter abbreviated as “VCO”) 3 to input an input signal Inpu.
Sample t. The phase comparator 2 and the loop filter 4 process this sampling result to detect a phase difference between the clock signal CLOCK and the input signal Input,
This is fed back to VCO3. As a result, the system samples the input signal Input with the clock signal CLOCK synchronized with the input signal Input.

The comparator 11 and the ZPS circuit 12 suspend the oscillation of the VCO 3 at the beginning of the phase pull-in of the PLL circuit 5, and thereafter, the VCO 3 has the same phase as the input signal Input.
A so-called zero-phase start of re-oscillating CO3 is performed. That is, the reference voltage V of the comparator 11
ref is set to the center value voltage of the input signal Input, and the comparator 11 detects the zero cross point of the input signal Input. The ZPS circuit 12 is a comparator 11
And outputs a signal d for stopping / re-oscillating the VCO 3. As a result, ideally, the phase of the input signal Input and the phase of the clock signal CLOCK already coincide with each other at the moment when the VCO 3 starts oscillating, and the phase can be pulled in a short time.

FIG. 13 is a timing chart showing the operation of the system shown in FIG. Here, for convenience, it is assumed that the input signal Input is substantially a sine wave. Also, VC
O3 has already been stopped at some timing, and attention is focused only on the start of oscillation of the VCO 3 in the zero-phase start.

As shown in FIG. 13, after the comparator 11 detects the zero cross point of the input signal Input,
There is a delay of time T10 between the time when the oscillation start signal is sent to the VCO 3 via the PS circuit 12 and the time when the oscillation output of the clock signal CLOCK is started. In FIG.
T11 is the delay of the comparator 11, T12 is the delay of the ZPS circuit 12, and T13 is the delay from the stop of the VCO 3 to the start of oscillation. Further, the clock signal CL
Taking into account the delay from when the OCK is supplied to the AD converter 1 and the sampling is performed, the actual delay time is further increased.

This delay time becomes an initial phase error in the phase lock of the PLL circuit. If the initial phase error is large, the lock time of the PLL circuit increases, and in some cases, the lock becomes impossible. Therefore, timing adjustment to reduce the initial phase error is very important,
Even when a ZPS circuit is provided, fine timing adjustment of the circuit delay is actually required.

In order to reduce the initial phase error in the PLL phase lock, the reference voltage Vre of the comparator 11 is reduced.
A method has been proposed in which f is made variable, the timing before the input signal CLOCK crosses zero is detected, and the VCO 3 starts oscillating (see JP-A-10-190456).

FIG. 14 is a timing chart showing the above method. In FIG. 14, the reference voltage Vref is set lower than the center value voltage 0 of the input signal Input, thereby shifting the response timing of the comparator 11 by the time T14 before the zero crossing point. This time T1
By making 4 equal to the above-described delay time T10, sampling can be performed substantially at the zero cross point of the input signal Input.

[0012]

However, the conventional zero-phase start method has the following problems.

The timing adjustment by the conventional method is considered to be effective when the frequency, amplitude, temperature, or power supply voltage of the input signal is constant. However, it is not always effective when the frequency or amplitude of the input signal changes, or when the ambient temperature or the power supply voltage changes.

For example, in the example of FIG. 14, since the reference voltage Vref of the comparator is set to a value different from the central value voltage of the input signal Input, the timing at which the input signal Input crosses the reference voltage Vref with reference to the zero cross point is , Are shifted due to a change in the frequency or amplitude of the input signal Input. Therefore, the timing adjustment time T14 changes, and this change causes an initial phase error in the phase lock.

In a system where the frequency of the input signal is not constant, it is necessary to change the oscillation frequency of the VCO in accordance with the frequency of the input signal. However, the time required for the VCO to start oscillating may greatly depend on the oscillating frequency.
Changes, and this change also causes an initial phase error. Further, if the amount of delay of the circuit or the time required to start the oscillation of the VCO changes due to a change in temperature or power supply voltage, the delay T10 changes, which also causes an initial phase error.

As described above, since the delay T10 and the timing adjustment time T14 change depending on the situation, in the conventional example, there is a possibility that a problem such as an increase in the response time of the PLL circuit or an increase in the probability of failure of the phase lock may occur. . In particular, when the frequency of the input signal is further increased, it becomes necessary to control the re-oscillation timing of the VCO with higher accuracy. However, according to the conventional method, the above-described problem may be further exacerbated.

In view of the above problems, it is an object of the present invention to realize a zero-phase start with higher accuracy than in a conventional signal extraction circuit having a PLL circuit.

[0018]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 includes, as a signal extraction circuit, a VCO for oscillating and outputting a clock signal,
A PLL circuit that synchronizes the clock signal with the input analog signal and samples the analog signal in accordance with the synchronized clock signal; and a timing adjustment circuit that adjusts the oscillation output timing of the VCO. The circuit obtains a zero-crossing time from when the analog signal crosses a predetermined voltage to when the analog signal crosses its center value voltage before the PLL circuit starts phase locking of the analog signal and the clock signal. When the circuit starts the phase lock, when the analog signal crosses the predetermined voltage and the zero crossing time has elapsed, the VC signal is output.
O causes the oscillation output of the clock signal to start.

According to a second aspect of the present invention, the timing adjustment circuit in the signal extraction circuit of the first aspect uses a voltage lower than the central value voltage as the predetermined voltage.

According to a third aspect of the present invention, in the signal extracting circuit according to the second aspect, the timing adjustment circuit includes a first comparator for comparing the analog signal with the center value voltage, and an output of the first comparator. A ZPS circuit for receiving and outputting a start signal; a second comparator for comparing the analog signal with the predetermined voltage;
A third comparator for comparing the clock signal, which is oscillated and output by O, with the predetermined voltage, and an operation switchable as delay means or delay measurement means;
The start signal output from the PS circuit and the outputs of the second and third comparators are input to the VCO
And a delay / delay measuring means for outputting a control signal, wherein the delay / delay measuring means operates from the transition of the output of the third comparator to the output of the second comparator when operating as the delay measuring means. While operating as a delay unit, the start signal is delayed by the delay time measured when operating as the delay measuring unit, and is output as a control signal of the VCO. I do.

According to a fourth aspect of the present invention, in the signal extraction circuit according to the second aspect, the timing adjustment circuit includes a first comparator for comparing the analog signal with the center value voltage, and an output of the first comparator. A ZPS circuit for receiving and outputting a start signal; a second comparator for comparing the analog signal with the predetermined voltage;
A second ZPS circuit having a delay time equivalent to that of the circuit, a third comparator for comparing the output of the second ZPS circuit with the predetermined voltage, and the same configuration as the VCO; A delay measurement path having a second VCO controlled by an output, and a switch configured to switch the operation as a delay unit or a delay measurement unit; a start signal output from the ZPS circuit; An output and an output of the second VCO as inputs and outputting a control signal to the VCO;
A delay measuring means, wherein the delay / delay measuring means operates as the second V
While measuring the delay time from the transition of the output of the CO to the transition of the output of the second comparator, when operating as the delay means, only the delay time measured when operating the start signal as the delay measurement means It is assumed that the signal is output as a control signal of the VCO with a delay.

According to a fifth aspect of the present invention, the timing adjustment circuit in the signal extraction circuit according to the first aspect uses a voltage corresponding to the center value voltage as the predetermined voltage, and
The time from when the analog signal falls below the predetermined voltage to when the analog signal exceeds the center value voltage is obtained as the zero-cross time.

According to a sixth aspect of the present invention, in the signal extracting circuit according to the fifth aspect, the timing adjustment circuit includes a first comparator for comparing the analog signal with the center value voltage, and an output of the first comparator. A ZPS circuit for receiving and outputting a start signal, a second ZPS circuit having a delay time equivalent to the ZPS circuit, a second comparator for comparing an output of the second ZPS circuit with the predetermined voltage, and A delay measuring path having the same configuration as the VCO and having a second VCO controlled by an output of the third comparator, and an operation switchable as a delay unit or a delay measuring unit; , The output of the first comparator, and the output of the second VCO are input to the VCO, and a control signal is supplied to the VCO. Output delay / delay measuring means, wherein the delay / delay measuring means operates from the transition of the output of the second VCO to the transition of the output of the first comparator when operating as the delay measuring means. While the delay time is measured, when operating as the delay means, the start signal is delayed by the delay time measured when operating as the delay measuring means and output as the VCO control signal.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing a configuration of a signal extraction circuit according to a first embodiment of the present invention. 1, the same components as those of the conventional configuration shown in FIG. 12 are denoted by the same reference numerals as those in FIG.

In FIG. 1, reference numeral 5 denotes a clock signal CLOCK synchronized with the input analog signal Input.
And the configuration and operation are the same as those described in the section of the prior art. The input signal Input is input to the first comparator 1
1 and delay / delay measuring means 2 via ZPS circuit 12
0 is input as a start signal SZ to a first input terminal IN1 which is an input terminal for delay, and a control signal SC as an output thereof is supplied from an output terminal OUT to a VCO of the PLL circuit 5.
3 is supplied. With such a signal path, the VCO
A zero phase start operation of No. 3 is performed. Input signal I
nput is also input to the second comparator 21 and the second
The output S2 of the comparator 21 is the delay / delay measuring means 2
0 is supplied to the trigger terminal TRG. VCO3
Is supplied as a signal S3 to a second input terminal IN2 of the delay / delay measuring means 20, which is a delay measuring input terminal, through a third comparator 22 for fine adjustment of delay.
First, second and third comparators 11, 21, 21
2. The timing adjustment circuit 10 is composed of the ZPS circuit 12 and the delay / delay measurement means 20.

The delay / delay measuring means 20 has both a function as a delay means and a function as a delay measuring means. Which function is operated is determined by the switching control terminal CT.
The signal is selected according to the input of L, and a signal output from the logic of the external CPU or the external demodulation circuit is supplied to the switching control terminal CTL. When operating as delay measuring means, the delay / delay measuring means 20 has a second input terminal IN2.
Is measured between the input S3 of the trigger terminal TRG and the input S2 of the trigger terminal TRG. Also, when operating as the delay means, it functions so that the delay from the first input terminal IN1 to the output terminal OUT is a time corresponding to the time delay measured when operating as the delay measuring means.

FIG. 2 is a timing chart showing the operation of the signal extraction circuit of FIG. Here, the reference voltage Vref2 of the second and third comparators 21 and 22 is the center value voltage of the input signal Input, and the first comparator 11
Of the reference voltage Vref1 takes a voltage value lower than the central value voltage Vref2.

The operation timing of the timing adjustment circuit 10 in FIG. 1 includes a PHASE 1 for measuring a required circuit delay,
It is divided into PHASE2 which causes the VCO3 to start oscillating based on the measured circuit delay. VCO in PHASE1
The operation of step 3 is temporarily stopped, and the delay amount of the delay / delay measuring means 20 is calculated so that the phase of the clock signal CLOCK matches the phase of the input signal Input. At this time, the delay / delay measuring means 20 operates as a delay measuring means in accordance with an instruction from the CPU or the demodulation circuit, and measures a time difference between the signal S3 of the second input terminal IN2 and the signal S2 of the trigger terminal TRG. At this time, from the first input terminal IN1 to the output terminal O
The delay time to the UT is the minimum delay time of the delay / delay measuring means 20. In PHASE2, PHASE
By delaying the oscillation start signal of the VCO 3 by the delay amount measured in step 1, the ZPS is applied so that the phases of the clock signal CLOCK and the input signal Input match.

As shown in FIG. 2, the output S1 of the first comparator 11 transitions between "H" and "L" due to a change in the input signal Input. ZPS circuit 12 is VC
O3 oscillation is stopped, and when the input signal Input exceeds the reference voltage Vref1 and the output S1 of the first comparator 11 rises, "H" is output to start oscillation of the VCO3. Note that the oscillation stop period of the VCO 3 is preferably shorter. At this time, the third comparator 2
The delay time T5 from the transition of the output S3 of the second comparator 2 to the transition of the output S2 of the second comparator 21 is measured.

Here, T1A = delay time in the first comparator 11 T1B = delay time in the second comparator 21 T1C = delay time in the third comparator 22 T2 = delay time in the ZPS circuit 12 T21 = delay / delay measurement The minimum delay time T3 from the first input terminal IN1 to the output terminal in the means 20 is the time required for the VCO3 to start oscillating. Note that the delay times of the comparators 11, 21, and 22 are represented by different constants because the transition times of the reference voltage and the input voltage are slightly different.

At this time, the delay time T4 required from the transition of the output signal S1 of the first comparator 11 to the transition of the output signal S3 of the third comparator 22 is as follows: T4 = T2 + T21 + T3 + T1C (1) Here, assuming that a time from when the input signal Input crosses the first reference voltage Vref1 to crosses the second reference voltage Vref2 is TA, the third comparator 22 measured by the delay / delay measuring means 20 The time T5 required from the transition of the output signal S3 to the transition of the output signal S2 of the second comparator 21 is as follows: T5 = TA + T1B-T1A-T4 (2) The value obtained by adding the minimum delay time T21 to the measured delay time T5 is the delay time T6 when the delay / delay measuring means 20 operates as the delay means. Time T
6 is represented by the following equation. T6 = T5 + T21 = TA + T1B-T1A-T4 + T21 (3)

In PHASE2 following PHASE1, re-oscillation of VCO3 is performed. In PHASE2, the delay time of the delay / delay measuring means 20 is PHASE1
Is set to the delay amount T6 measured in. Therefore, the output signal of the ZPS circuit 12 causes the VCO 3 to start oscillating at a timing delayed by the time T6.

When PHASE2 is started, the ZPS circuit 12 first outputs "L" to stop the oscillation of the VCO 3, and then inputs the input signal Input, as in the case of PHASE1.
Output “H” when the output voltage S exceeds the reference voltage Vref 1 and the output S 1 of the first comparator 11 rises.
Start oscillation. Note that the timing at which the oscillation of the VCO 3 is stopped is not important here, and is not particularly described.

Here, the input signal Input is the reference voltage V
Using the equations (1) and (3), TB = T1A + T2 + T6 + T3 = T1A + T2 + TA + T1B-T1A- (T2 + T21 + T3 + T1C) + T21 + T3 = TA + T3 T1 ). Here, assuming that T1B ≒ T1C, TB ≒ TA is obtained. Here, since PHASE1 and PHASE2 are performed continuously, it is considered that the frequency of the input signal Input hardly changes during that time, so that the VCO 3 restarts oscillation substantially at the zero crossing point of the input signal Input. Therefore, the initial phase error in the phase lock of the PLL circuit 5 becomes almost zero.

<Delay / Delay Measuring Means> FIG. 3 is a circuit diagram showing an example of the internal configuration of the delay / delay measuring means 20. The circuit of FIG. 3 operates as a delay measuring means when the signal value applied to the switching control terminal CTL is “H”, and operates as a delay means when the signal value is “L”.

In FIG. 3, the selector 34 is connected to a first input terminal IN1 and a second input terminal IN2,
Of the delay input input to the input terminal IN1 and the delay measurement input input to the second input terminal IN2 are selected in accordance with the input signal of the switching control terminal CTL.

On the output side of the selector 34, a predetermined number of unit delay elements 30 are connected in series. Then, the output of each unit delay element 30 is
Are connected to a latch circuit 31 for latching the output digital signal of the first stage and the tristate buffer 33. The output of each tristate buffer 33 is commonly connected to an output terminal OUT. Between each adjacent latch circuit 31,
A logic gate 32 for controlling each tri-state buffer 33 is provided.
Activates the tristate buffer 33 only when the output of the preceding latch circuit 31 is “H” and the output of the subsequent latch circuit 31 is “L”; otherwise, the tristate buffer 33 is activated. Put the output in a high impedance state.

The trigger terminal TRG is connected to the clock terminal of each latch circuit 31 via the H holding circuit 42. When the signal at the terminal 41 is “L”, the H holding circuit 42 holds “H” as an output as it is once the input trigger signal becomes “H”. As a result, only the first rising of the output pulse of the second comparator 5 connected to the trigger terminal TRG is extracted, and the subsequent change in the trigger signal is not transmitted to each latch circuit 31. As a result, malfunction of the latch circuit 31 can be prevented.
When the signal at the terminal 41 is “H”, the H holding circuit 42 does not perform the holding function, and transmits the input trigger signal to each latch circuit 31 as it is.

The first input terminal IN1 and the output terminal O
Between the UT and the UT, a tri-state buffer 40 having the same characteristics as the tri-state buffer 33 provided on the output side of each unit delay element 30 is provided. Thereby, even when the circuit of FIG. 3 operates as the delay measuring means,
This buffer 40 requires a delay T21 between the first input terminal IN1 and the output terminal OUT.

The reset terminal R of each latch circuit 31
Is connected to a reset terminal RST (not shown in FIG. 1), whereby the latch data of each latch circuit 31 can be externally initialized to “L”. This reset terminal RST is also appropriately controlled by an external demodulation circuit or CPU.

The operation of the delay / delay measuring means 7 shown in FIG. 3 will be described with reference to FIG. In the figure, (a) shows the operation as delay measuring means, (b) shows the operation as delay means,
Each is shown.

First, the operation as the delay measuring means is shown in FIG.
This will be described with reference to FIG. Before operation, reset terminal R
A pulse signal is supplied to ST, and the latch data of all the latch circuits 31 is reset to “L”. Since this circuit is not used for other purposes before operating as the delay measuring means, this reset operation can be performed in parallel with other operations of the system, and therefore, this reset operation will The operating time does not increase.

Then, the signal of the switching control terminal CTL is set to "H". Thus, the selector 34 is set to select the second input terminal IN2 for delay measurement as an input terminal. In this state, this circuit operates as a delay measuring means, and measures the time difference between the signal S3 input from the second input terminal IN2 and the signal S2 input to the trigger terminal TRG.

The input signal S 3 propagates through each unit delay element 30 via the selector 34. That is, the output of the unit delay element 30 to which the signal S3 has propagated becomes “H”, and the output of the unit delay element 30 that has not yet propagated becomes “L”. In the process in which the signal S3 propagates through each unit delay element 30,
When the signal S2 input to the trigger terminal TRG rises (trigger signal is applied), the digital output value of each unit delay element 30 is held in each latch circuit 31. FIG.
In the example of (a), the first-stage and second-stage latch circuits 31
Holds "H", and the third and subsequent latch circuits 31 hold "L".

The output terminal OUT is driven by the tri-state buffers 33 and 40. However,
When operating as delay measuring means, each latch circuit 31
Are all "L", the outputs of each tristate buffer 33 are all in a high impedance state.
On the other hand, the tri-state buffer 40 is in an active state because “H” is given to the switching control terminal CTL. Therefore, even when operating as delay measuring means, the output terminal OUT is connected to the first input terminal IN1, which is a delay input terminal, via the tri-state buffer 40, and thus also operates as delay means. This delay time corresponds to the aforementioned minimum delay time T21.

Next, the operation as the delay means will be described with reference to FIG.
This will be described with reference to FIG. In this case, the signal of the switching control terminal CTL is set to “L”. As a result, the selector 34 is set to select the first input terminal IN1 for delay as an input terminal. In this state, the circuit operates as a delay unit, delays the signal SZ input from the first input terminal IN1 by a predetermined time, and outputs the signal to the output terminal OUT.

By the operation of each logic gate 32, only the tri-state buffer 33 connected to the output of the earliest unit delay element 30 to which the input signal SZ has propagated when operating as the delay measuring means is activated, and Connected to terminal OUT. In the example of FIG. 4B, only the second-stage tri-state buffer 33 is in the active state, and a signal propagation path as indicated by a broken line in the figure is formed.
Through such a signal propagation path, the first input terminal IN
Since the signal SZ input to 1 is output from the output terminal OUT, the delay time in this case is a time corresponding to the time measured when operating as the delay measuring means. More precisely, from the first input terminal IN1 to the output terminal OUT
The delay amount up to is the sum of the delay measured when operating as the delay measuring means and the delay amount T21 in the tristate buffer 33.

As described above, when the circuit of FIG. 3 operates as the delay means, the delay amount corresponding to the delay measured when operating as the delay measuring means can be set. Thereby, the timing adjustment function as described above can be realized.

When the H holding circuit 42 is not provided, each latch circuit 31 also reacts by the second pulse of the trigger signal during the operation as the delay measuring means. The delay amount may be maintained. The H holding circuit 42 serves to prevent such a malfunction. Immediately before operating as the delay measuring means, a pulse is applied to the terminal 41 to temporarily release the H holding function of the H holding circuit 42. Thereafter, the H holding circuit 42 holds “H” in response to the first pulse of the trigger signal.

If there is a shift in the latch timing of each latch circuit 31, the latch data may have a value such as "H", "H", "L", "H", "L", "L".
There is a possibility that so-called bubbling in which the latch circuit 31 holding “L” is mixed between the latch circuits 31 holding “H”. By providing a logic circuit for eliminating such bubbling at the subsequent stage of the output of each latch circuit 31, the delay measurement and the delay setting can be performed more accurately.

Also, by sharing the delay measuring means and the delay means as in the configuration of FIG. 3, the circuit scale can be reduced. Of course, it is needless to say that the same effect as that of the present embodiment can be obtained even if the delay measuring means and the delay means having configurations different from those in FIG. 3 are used.

As described above, according to the signal extraction circuit according to the present embodiment, the delay time for performing the optimal timing adjustment is measured before the zero-phase start is performed, and this delay time is used to initialize the PLL circuit. Zero phase start is performed so that the phase error becomes zero. Therefore, even when the frequency or amplitude of the input signal changes, or when the delay value in the circuit changes due to a change in temperature or power supply voltage, it is possible to flexibly cope with the change, and the PLL circuit can be controlled by a short phase pull-in time. Operation can be stabilized.

(Second Embodiment) FIG. 5 is a block diagram showing a configuration of a signal extraction circuit according to a second embodiment of the present invention. 5, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 5, a delay measuring path 13 including a second ZPS circuit 12A having the same configuration as the ZPS circuit 12, a third comparator 22, and a second VCO 3A having the same configuration as the VCO 3 of the PLL circuit 5 is provided. The output of the second VCO 3A is input to the second input terminal IN2 of the delay / delay measuring means 20.
First and second comparators 11 and 21, ZPS circuit 12, delay measuring path 13, and delay / delay measuring means 2
0 forms the timing adjustment circuit 10A.

The operation of the configuration of FIG. 5 is exactly the same as the configuration of FIG. That is, in the description of the first embodiment, T2 = the delay time in the ZPS circuit 12 and the second Z
Delay time in PS circuit 12A T3 = time required for VCO3 to start oscillation and second V
By reading the term "the time required for the CO3A to start oscillating," the same description holds true in the present embodiment. Therefore, the effect of the first embodiment is not lost at all in the present embodiment.

In the configuration shown in FIG. 1, it is necessary to temporarily stop the oscillation of the VCO 3 for measuring the delay time and then stop it again for the ZPS. On the other hand, in the configuration of FIG. 5, the provision of the delay measurement path 13 allows the delay time to be measured by the delay measurement path 13. Therefore, in PHASE 1 for performing delay measurement, the PLL circuit 5 may be in any operation state, and there is no need to stop the VCO 3 for delay measurement. For this reason, VCO3 uses ZP in PHASE2.
It only needs to be stopped once for S, which allows a short phase lock. That is, when it is desired to reduce the phase pull-in time by one clock, the configuration shown in FIG. 5 is effective.

Conversely, the first embodiment requires a time corresponding to one cycle of the input signal Input for delay measurement in comparison with the present embodiment, but instead of the delay measurement path, There is an advantage that the circuit scale and power consumption can be reduced by unnecessary amounts.

Further, since the second ZPS circuit 12A is a digital circuit, even if it is replaced with a digital delay element having a smaller circuit scale, the amount of delay hardly shifts significantly. Therefore, the circuit scale can be reduced by this replacement. Similarly, the circuit size and power consumption of the third comparator 22 can be reduced by replacing the third comparator 22 with digital elements having substantially the same delay amount.

Further, in the configuration of FIG. 5, since the operation of the PLL circuit is not restricted in PHASE 1, a zero-phase start with high accuracy can be performed without hindering the high-speed operation. For example, when starting the zero phase start, V
PHASE1 may be executed in parallel with the process of stopping CO oscillation. Further, for example, in the case where the PLL circuit performs frequency locking before performing phase locking, PHASE1 may be executed in the final stage of frequency locking.
However, it is desirable that PHASE1 and PHASE2 be as close in time as possible because the timing error is reduced.

1 and 5, the delay until the clock signal CLOCK is oscillated and output from the VCO 3 is taken into consideration.
CK is applied to the AD converter 1 to input the input signal Inpu.
It is preferable to adjust the timing in consideration of the delay until t is sampled. In order to perform such minute timing adjustment, a delay adjusting circuit having a plurality of fixed delay elements 50 having a small delay as shown in FIG. 6 may be inserted in series with the delay / delay measuring means 20. As a result, A that cannot be measured by the delay / delay measuring means 20
The delay inside the D converter 1 can be corrected. Also,
It is also possible to correct a difference in delay time between the second comparator 21 and the third comparator 22 or an error such as a clock delay of the latch circuit 31. Therefore, more accurate timing adjustment can be performed.

Further, in the configuration of FIG. 6, by allowing the number of stages of the unit delay circuit 50 selected by the selector 51 to be externally controllable, the timing can be adjusted with a higher degree of freedom. Further, if a logic circuit that determines the number of stages of the unit delay circuit 50 so as to reduce the initial phase error with reference to the output of the phase comparator 2 of the PLL circuit 5 is provided, the delay adjustment can be automated, and the adjustment process can be performed. It becomes unnecessary.

The reference voltage Vref1 of the first comparator 11 is within the voltage range of the input signal Input, and the transition of the output signal S1 of the first comparator 11 to the transition of the output signal S2 of the second comparator 21 Any value may be used as long as the VCO 3 can start oscillating during this time. However, the closer the reference voltage Vref1 is to the central value voltage of the input signal Input, the more the output signal S
Since the slope of the input signal Input between the transitions 1 and S2 is steep, a timing error due to noise is less likely to occur. Therefore, the reference voltage Vref
It is desirable that 1 be as close as possible to the center value voltage of the input signal Input.

<Modification> FIG. 7 is a block diagram showing a configuration of a signal extraction circuit according to a modification of the present embodiment. 7, the same components as in FIG. 5 are denoted by the same reference numerals as in FIG. In FIG. 7, a signal processing circuit 61 is provided in a stage preceding the A / D converter 1. In this case, the signal processing circuit 61 includes a filter 62 and an automatic amplitude adjustment amplifier (AG).
C) 63 is provided. The input signal of the signal processing circuit 61 is supplied to the first comparator 11 instead of the input signal of the A / D converter 1.

As shown in FIG. 7, the first comparator 1
Even if the input signal of the signal processing circuit 61 is given as the input of 1, the effect of the present embodiment is not lost at all. Further, FIG.
In the configuration of, the input signal of the first comparator 11 is A /
Since the time until the signal is input to the D converter 1 becomes long, the time required for the zero-phase start has a margin. Therefore, the reference potential Vref1 of the first comparator 11 can be made closer to the center value of the input signal Input, so that an error caused by noise superimposed on the input signal Input can be avoided.

(Third Embodiment) FIG. 8 is a block diagram showing a configuration of a signal extraction circuit according to a third embodiment. 8, the same components as those in FIG. 5 are denoted by the same reference numerals as those in FIG.

In the first and second embodiments, two types of reference signals S1 and S2 are generated from the input signal Input using the two comparators 11 and 21, and delay measurement is performed using these two types of reference signals S1 and S2. On the other hand, in the present embodiment, two types of timing are generated using one comparator 11. The comparator 11, the ZPS circuit 12, the delay measurement path 13, and the delay / delay measuring means 20 constitute a timing adjustment circuit 10C.

FIG. 9 is a timing chart showing the operation of the configuration of FIG. Reference potential Vref of comparator 11
1 is set to the center value voltage of the input signal Input. Here, of the transitions of the output signal S1 of the comparator 11, the falling is used instead of the rising of the output S1 of the first comparator 11 in the first and second embodiments, and the rising is changed to the first and second. It is used instead of the rise of the output S2 of the second comparator 21 in the embodiment. Thereby, in the present embodiment, the same operation and effect as those of the first and second embodiments can be obtained. Therefore, according to the present embodiment, the number of comparators can be reduced as compared with the first and second embodiments, so that both the circuit scale and the power consumption can be reduced.

In this embodiment, the input signal Inpu
Since the center value voltage having the largest slope of t is set as the reference voltage Vref1 of the comparator 11, it also has a feature that it is hardly affected by noise superimposed on the input signal Input.

In the present embodiment, the input signal to the first input terminal IN1 of the delay / delay measuring means 20 is inverted as compared with the first and second embodiments. This case can be dealt with by replacing the latch 31 with an edge trigger type having a reverse polarity in the configuration of FIG.

When the present invention is used in a system in which the frequency of an input signal changes, the length and accuracy of the delay time to be measured change depending on the situation. For example, when the frequency of the input signal is high, the period of the input signal is short, so that the time required for the timing adjustment is short, but the accuracy of the timing adjustment must be high. On the other hand, when the frequency of the input signal is low, the accuracy of the timing adjustment may be low, but the time required for the timing adjustment becomes long.

Therefore, in order to satisfy all of these requirements, the unit delay element used in the delay / delay measuring means must be designed so that the timing adjustment accuracy is sufficiently high.
The delay per unit needs to be small, and the number of units needs to be set large enough so that long delay time can be measured. This leads to an increase in circuit size and power consumption.

In order to cope with a system in which the frequency of an input signal changes while avoiding an increase in circuit scale and power consumption, a delay time of the VCO is used as a unit delay element used in the delay / delay measuring means. A method using a delay element proportional to the period can be considered. Such a unit delay element can be realized by inputting a VCO frequency control signal to a delay element having a variable delay amount. For example, a variable delay inverter constituting an inverter ring type VCO may be used as a unit delay element as it is.

By using such a unit delay element, when the frequency of the input signal is high, the unit delay element 1
The delay per unit is short, and the delay time can be measured with high accuracy. On the other hand, when the frequency of the input signal is low, the delay per unit delay element is long, so that a long delay can be achieved without increasing the number of stages. Time can be measured. Therefore, it is possible to cope with a system in which the frequency of an input signal changes while avoiding an increase in circuit scale and power consumption.

A system to which the present invention is effective includes, for example, a read channel system that handles various disk media.

FIG. 10 is a diagram showing the overall structure of a disk read channel. The system shown in FIG. 10 extracts a clock signal from an original signal read from the disk 71,
The digital signal is demodulated by sampling the original signal with the clock. First, a signal from the disk 71 is read by a head amplifier 72, amplified by a variable gain amplifier 73, and a high-frequency noise component is removed and a waveform is shaped by a low-pass filter 74 in the next stage. This signal is the signal extraction circuit 7 according to the present invention.
5 is input.

The signal extraction circuit 75 extracts a clock signal from an input signal and uses this to demodulate a digital signal from the input signal. The extracted clock signal is supplied to the demodulation circuit 76 and the CPU 77 at the subsequent stage, where it is used for error correction of digital signals and signal processing using the extracted data. CP
U77 also has a role of controlling the functions of the entire system, and a control signal to each block is supplied from the CPU 77. For example, in the signal extraction circuit 75, the CPU 77 controls the switching between the frequency pull-in and the phase pull-in, and controls the signal path of the delay measuring means and the delay element. Note that, depending on the configuration, some or all of these control signals can be generated by a logic circuit in the demodulation circuit 76 or the signal extraction circuit 75.

FIG. 11 is a diagram showing a data format of a disk. The disk data is composed of a set of tracks arranged on the same circumference, and the track is divided into a plurality of sectors. In each sector, the required data is “USER
DATA "area. "USER D
In order to read a signal in the "ATA" area, a clock synchronized with the signal is required. In order to generate this clock, “SYNC PAT” must be added before “USER DATA”.
A synchronization signal pattern called "TERN" is described, and a clock is extracted from this "SYNC PATTERN".

The clock extraction is performed by using “SYNC PATTE
"RN" to adjust the frequency of the VCO,
Large 2 with phase pull-in to match the phase of VCO
Divided into two. In other words, "SYNC PATTERN" for the time required for these two types of pull-in must be written in each sector. Therefore, when it takes a long time to pull in the phase, it is necessary to prepare a longer “SYNC PATTERN”, and the subsequent “USER DATA” area is pressed. This leads to a reduction in disk capacity.
Therefore, realizing high-speed frequency pull-in and phase pull-in is a very important factor for increasing the disk capacity.

The present invention relates to a read channel system which performs so-called jitter-free reproduction for reading data by locking a PLL circuit before the rotation of a disk is stabilized for high-speed data access.
Especially effective. In such a system, the input frequency changes when the phase of the PLL circuit is pulled in, and it is difficult to know the frequency value in advance. Even in such a system in which the frequency of the input signal changes every moment, the use of the present invention makes it possible to perform a zero-phase start at an optimal timing according to the situation.

In the present invention, PHASE1 and PHA1
When the amplitude or frequency of the input signal changes with SE2, an error may occur in the delay. However,
Since PHASE1 and PHASE2 are temporally continuous, even if the amplitude or frequency of the input signal changes,
The difference is considered small. In the case of a disk system, since a synchronization signal of a constant frequency is input as an input signal, the difference is very small. Also, in the case of the system for performing the jitter-free reproduction described above, although the frequency of the input signal changes, the change is the PHASE
This is not a problem since the period is sufficiently slow in view of the period of 1 and PHASE2.

When the present invention is applied to a disk drive system having a digital PLL, a stable signal can be read because the initial phase error of the PLL is small. Therefore, it is possible to configure a highly reliable disk drive system with a low bit error rate. Also, since it can cope with various frequencies of the input signal, it is suitable for a highly reliable system that can read and write a disk of a plurality of media by one drive.

[0081]

According to the present invention as described above, the influence of the timing shift due to the fluctuation of the frequency, amplitude, temperature and power supply voltage of the input signal is corrected, and the operation of the PLL circuit is prevented without impeding the high-speed operation. Stable operation can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a signal extraction circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the configuration of FIG.

FIG. 3 is a circuit diagram showing an example of an internal configuration of a delay / delay measuring unit.

FIGS. 4A and 4B are diagrams for explaining the operation of the delay / delay measuring means of FIG. 3;

FIG. 5 is a block diagram illustrating a configuration of a signal extraction circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a delay adjustment circuit.

FIG. 7 is a diagram showing a modification of the second embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a signal extraction circuit according to a third embodiment of the present invention.

FIG. 9 is a timing chart showing the operation of the configuration of FIG. 8;

FIG. 10 is a diagram showing an overall configuration of a disk read channel.

FIG. 11 is a diagram showing a data format of a disc.

FIG. 12 is a diagram showing a configuration of a conventional signal extraction circuit.

FIG. 13 is a timing chart showing the operation of a conventional signal extraction circuit.

FIG. 14 is a timing chart showing a conventional zero-phase start.

[Explanation of symbols]

 CLOCK Clock signal Input Input analog signal SZ Start signal SG Control signal 3 VCO 3A Second VCO 5 PLL circuit 10, 10A, 10B, 10C Timing adjustment circuit 11 First comparator 12 ZPS circuit 12A Second ZPS circuit 13 Delay measurement Path 20 delay / delay measuring means 21 second comparator 22 third comparator

Continued on the front page F term (reference)

Claims (6)

[Claims] A PLL circuit for oscillating and outputting a clock signal, synchronizing the clock signal with an input analog signal, and sampling the analog signal in accordance with the synchronized clock signal; A timing adjustment circuit that adjusts an oscillation output timing, wherein the timing adjustment circuit is configured to execute a phase adjustment of the analog signal and the clock signal before the analog signal crosses a predetermined voltage before the PLL circuit starts a phase lock. When the PLL circuit starts the phase lock by obtaining a zero crossing time until the center voltage crosses, when the analog signal crosses the predetermined voltage and the zero crossing time elapses, the VCO Starting the oscillation output of the clock signal. Signal extraction circuit. 2. The signal extraction circuit according to claim 1, wherein the timing adjustment circuit uses a voltage lower than the central value voltage as the predetermined voltage. 3. The signal extraction circuit according to claim 2, wherein the timing adjustment circuit receives a first comparator that compares the analog signal with the center value voltage, and receives an output of the first comparator. A ZPS circuit that outputs a start signal; a second comparator that compares the analog signal with the predetermined voltage; a third comparator that compares the clock signal oscillated and output by the VCO with the predetermined voltage; Is configured to be switchable as delay means or delay measurement means, receives a start signal output from the ZPS circuit and outputs of the second and third comparators, and outputs a control signal to the VCO. The delay / delay measuring means, when operating as the delay measuring means, While the delay time from the transition of the output of the comparator to the transition of the output of the second comparator was measured, when operating as delay means, the start signal was measured when operating as delay measurement means. A signal extraction circuit for outputting a control signal of the VCO with a delay by a delay time. 4. The signal extraction circuit according to claim 2, wherein the timing adjustment circuit receives a first comparator that compares the analog signal with the center value voltage, and receives an output of the first comparator. A ZPS circuit that outputs a start signal; a second comparator that compares the analog signal with the predetermined voltage; and a second ZPS having a delay time equivalent to that of the ZPS circuit.
Circuit, a third comparator for comparing the output of the second ZPS circuit with the predetermined voltage, and a delay having the same configuration as the VCO and having a second VCO controlled by the output of the third comparator A measurement path and an operation configured to be switchable as delay means or delay measurement means. The start signal output from the ZPS circuit, the output of the second comparator, and the output of the second VCO are input. And a delay / delay measuring means for outputting a control signal to the VCO. When the delay / delay measuring means operates as a delay measuring means, the delay / delay measuring means changes from the output transition of the second VCO to the second 2
When operating as a delay means while measuring the delay time until the transition of the output of the comparator, the start signal is delayed by the delay time measured when operating as the delay measurement means, A signal extraction circuit for outputting as a control signal. 5. The signal extraction circuit according to claim 1, wherein the timing adjustment circuit uses, as the predetermined voltage, a voltage corresponding to the center value voltage, and after the analog signal falls below the predetermined voltage. A signal extraction circuit for obtaining a time until the voltage exceeds the center value voltage as the zero-cross time. 6. The signal extraction circuit according to claim 5, wherein the timing adjustment circuit compares the analog signal with the center value voltage.
, A ZPS circuit receiving the output of the first comparator and outputting a start signal, and a second ZPS having a delay time equivalent to that of the ZPS circuit
Circuit, a second comparator for comparing the output of the second ZPS circuit with the predetermined voltage, and a delay having the same configuration as the VCO and having a second VCO controlled by the output of the third comparator A measurement path, and an operation configured to be switchable as a delay unit or a delay measurement unit. The start signal output from the ZPS circuit, the output of the first comparator, and the output of the second VCO are input. And a delay / delay measuring means for outputting a control signal to the VCO. When the delay / delay measuring means operates as a delay measuring means, the delay / delay measuring means changes from the output transition of the second VCO to the second 1
When operating as a delay means while measuring the delay time until the transition of the output of the comparator, the start signal is delayed by the delay time measured when operating as the delay measurement means, A signal extraction circuit for outputting as a control signal.