KR0155839B1 - Isolation method of device of semiconductor apparatus - Google Patents

Abstract

The present invention relates to a device isolation method of a semiconductor device, comprising: sequentially stacking a first insulating film and a second insulating film on a semiconductor substrate, and patterning the second insulating film to form an oxide film having a predetermined thickness on the exposed first insulating film portion. ; Removing a portion of the oxide layer through an isotropic etching process to leave only a proper amount of the center portion; Forming a thin oxide film on the portion from which the oxide film is removed by thermal oxidation; Depositing polycrystalline silicon on the resultant and over-etching it by an anisotropic etching to form a polycrystalline silicon spacer on sidewalls of the patterned second insulating layer; And forming a device isolation film by performing an oxidation process. Therefore, the present invention provides a deeper sub-substrate oxide depth to improve the electrical characteristics of device isolation, and to reduce the thickness of the thin oxide film that controls BIRD'S BEAK unaffected during subsequent spacer etch. There is an advantage to this.

Description

Device Separation Method of Semiconductor Device

1A to 1E are cross-sectional views for explaining a device isolation method of a semiconductor device by a conventional method.

2A to 2F are cross-sectional views illustrating a device isolation method of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method of a semiconductor device using a polycrystalline silicon spacer.

In order to construct a circuit on a semiconductor substrate, it is necessary to electrically isolate several elements. In the device isolation method, a partial oxidation method of silicon (hereinafter referred to as LOCOS process) is most commonly used.

The LOCOS process includes forming a pad oxide film and a nitride film sequentially on a silicon substrate, patterning the nitride film, and selectively oxidizing the silicon substrate to form an isolation layer. However, according to the LOCOS process, as the oxygen penetrates into the side of the pad oxide film under the nitride film used as the mask for the selective oxidation of the silicon substrate, a bird's beak is generated at the end of the device isolation film. Since the device isolation film extends into the active region by the length of the buzz beak by such a buzz beak, it is difficult to integrate the device at a high density.

In this regard, the present applicant has invented a device isolation method that solves the problems of the LOCOS process by using a polysilicon spacer, and has filed it with Korean Patent Application Nos. 92-0682 and 93-0591. Currently, he is continuing with Korea Patent Office.

The process procedure of the above-mentioned 92-0682 is briefly described with reference to FIGS. 1A to 1E.

As shown in FIG. 1A, the first insulating film 3 is laminated on the silicon substrate 1, and at this time, the first insulating film is used as a thin pad oxide film. Subsequently, the second insulating film 5 is laminated. A nitride film is used as the second insulating film and is laminated to a thickness of about 1000 to 2000 micrometers. Thereafter, a photo pattern (PHOTO-PATTERN) is formed on the resist in a desired shape to divide the active region and the inactive region, and then anisotropically etch the second insulating layer 5 using the photoresist as a mask to expose a portion to be an inactive region. In FIG. 1B, a portion of the first insulating film that is introduced through the isotropic etching process is subsequently removed. In this case, the larger the amount removed, the smaller the size of the BIRD'S BEAK by the subsequent process, while if too large, the lifting of the second insulating layer may occur. The isotropic etching amount X1 should consider the thickness of the first insulating film 3. Subsequently, a thin oxide film 7 that controls BIRD'S BEAK is formed. The thickness of the oxide film should consider the thickness of the first insulating film 3, and the smaller the thickness of the oxide film is, the less BIRD'S BEAK is formed (FIG. 1c). Subsequently, any one of silicon-based polysilicon, amorphous silicon, and doped polysilicon is stacked as a fourth insulating layer, and a spacer SPACER is formed by an anisotropic etching process. At this time, the spacer etch should be over etched by a certain amount (X2). This is because, if the oxide film of the spacer 9 portion grows too large after the subsequent thermal oxidation process, it is not completely removed by the subsequent process. The over etch amount X2 should consider the thickness of the second insulating film 5, and the thin oxide film 7 should be able to serve as a mask layer (MASK LAYER) during spacer over etch (FIG. 1D). Subsequently, the field oxide film 11 is formed by the thermal oxidation method to deepen the sub-substrate oxide film depth X3 to improve the electrical characteristics of device isolation (FIG. 1E).

The above is a process progression process according to the present invention, wherein the thin oxide film 7 serves as a mask at the time of the over etch when the spacer 9 is formed, thereby forming the grooves of the substrate silicon. Should be prevented. In the LOCOS structure, the thicker the active nitride layer (5), the fewer BIRD'S BEAKs are formed. In addition, in the present invention, the smaller the thickness of the thin oxide film 7 is, the less BIRD'S BEAK is formed. In addition, due to the structural features of the present invention, the spacer 9 over etch is inevitable, and the thicker the thickness of the active nitride layer ACTIVE NITRIDE 5 is, the more OVER ETCH X2 is applied. shall. In the above-described invention, in order to minimize the size of BIRD'S BEAK, the thickness of the oxide layer 7 is minimized, and it is difficult to apply an over etch as much as the spacer is desired. have. That is, it is difficult to take the thickness of the thin oxide film 7 below a certain level.

The present invention compensates for and improves the disadvantages of the device separation method of the semiconductor device of No. 92-0682 filed in 92.1.18 and the device separation method of the semiconductor device of No. 93-0591 filed in 94.6.8. .

Accordingly, it is an object of the present invention to provide a device isolation method for a semiconductor device that can solve the problems of the conventional method described above.

In order to achieve the above object, the present invention comprises the steps of sequentially forming a pad oxide film and an active nitride film by sequentially stacking a first insulating film and a second insulating film on a semiconductor substrate; Patterning the second insulating layer by a photolithography process; Forming an oxide film with a predetermined thickness on a portion of the first insulating film formed by using the patterned second insulating film as a mask; Removing a portion of the oxide film having a predetermined thickness through an isotropic etching process, and leaving only an appropriate portion of the oxide film to remove a portion of the first insulating film under the second insulating film, thereby forming a pupil; Forming a thin oxide film on the portion from which the oxide film is removed by thermal oxidation; Depositing polycrystalline silicon on the resultant and over-etching it by an anisotropic etching to form a polycrystalline silicon spacer on sidewalls of the patterned second insulating layer; And forming an isolation layer by performing an oxidation process and sequentially removing the second insulation layer and the first insulation layer by an isotropic etching process.

In this case, the reason for the predetermined amount of OVER ETCH when the polysilicon spacer is etched is that when the oxide film of the spacer portion grows too large after the subsequent thermal oxidation process, it is not completely removed by the subsequent process.

In the case of the previously filed invention, in order to prevent substrate groove forming, a thin oxide film must be able to play a role as a mask layer during a spacer over etch. However, the present invention is not limited because the oxide film, which is somewhat thickened in the middle of the present invention, serves as an etch stopper.

Therefore, the present invention has the first advantage of making the thickness of the thin oxide film controlling the BIRD'S BEAK as small as desired without being influenced by subsequent spacer etch. The second advantage is that the more the amount of the oxide film (X3) below the substrate of the oxide film can improve the electrical characteristics at the same size (SIZE) and less ion implantation concentration (IMPLANTATION DOSE), thereby improving the performance (REFRESH) characteristics of the product. That is, the depth of the oxide sub-substrate (X3) is further deepened to improve the electrical characteristics of device isolation, and the thickness of the thin oxide layer controlling BIRD'S BEAK is less affected by the subsequent spacer etch. It is an object of the present invention to be able to take it.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; 2A to 2E are cross-sectional views illustrating a device isolation method of a semiconductor device according to the present invention.

2A shows a step of exposing a portion to be an inactive area. Specifically, a thin pad oxide film is formed on the silicon substrate 51 with the first insulating film 53 to a thickness of about 100 to 300 Å. Subsequently, a second insulating film 55 is stacked. As the second insulating film, nitride (NITRIDE) film quality is deposited at about 1000 to 2000 GPa. Thereafter, a photo pattern (PHOTO PATTERN) is formed on the resist in a desired shape to divide the active region and the inactive region, and then anisotropically etches the second insulating layer 55 using the resist as a mask to expose a portion to become an inactive region. Let's do it.

FIG. 2B forms an oxide film on the exposed inactive region. Specifically, an oxide film 57 of about 600 to 1500 Å is formed on the first insulating film 53 by the thermal oxidation method. Substrate silicon 51 has a recessed RECE effect by the oxide layer 57 in the inactive region, thereby increasing the oxide penetration amount (Y3X3) toward the bottom of the substrate when forming the thermal oxide layer, thereby improving the electrical characteristics of the device isolation oxide layer. Will be improved.

In FIG. 2C, the oxide layer 57 is partially removed through an isotropic etching process. Specifically, the first insulating film 53 under the second insulating film 55 is removed by the isotropic etching process, and a predetermined portion Y1 is removed. In this case, the larger the amount removed, the larger the BIRD'S BEAK size is by the subsequent process. On the other hand, if too large, the patterned second insulating layer may cause a lifting phenomenon. The amount Y1 under the second insulating film is preferably about 200 to 500 kPa. The isotropic etching amount removes 70 to 80% of the thickest portion of the oxide film 57 in consideration of the thickness of the oxide film 57 so that only the center portion 57a remains in the non-active region. The oxide film 57a serves as an etch stopper when forming the subsequent spacer 59. Subsequently, a thin oxide film 61 is formed by about 40 to 150 microseconds by the thermal oxidation method. This oxide film is used to control BIRD'S BEAK, and in the case of the present invention, it is difficult to take it below a certain thickness to serve as an etch stopper when forming a subsequent spacer. Since the oxide film 57a is in the inactive region, the thickness of the thin oxide film 61 that controls BIRDS 'S BEAK can be reduced as much as desired.

Figure 2d shows the step of forming a spacer. As the third insulating layer, any one of silicon-based polysilicon, amorphous silicon, and doped polysilicon is laminated, and a spacer 59 is formed by an anisotropic etching process. In this case, a certain amount of over etch (Y2) should be performed during spacer etching. This is because if the oxide film of the spacer 59 portion grows too large after the subsequent thermal oxidation process, it is not completely removed by the subsequent process. The amount of over etch (Y2) should consider the thickness of the second insulating film 55, and in the case of the previously filed invention, a thin oxide film may serve as a mask layer during spacer over etch. Although it should be possible to limit the amount of over etch (OVER ETCH: Y2), in the present invention, since the oxide film 57a serves as an etch stopper, it is not restricted. As a result, when the polysilicon spacer 59 is formed, the portion Y2 formed due to overetching on the sidewall of the second insulating film 55 is smaller than the thickness of the remaining oxide film 57a so that the amount of overetching is not limited.

FIG. 2E shows a step of forming a field oxide film 63 of 2500 to 4000 kV by the thermal oxidation method after the above process.

FIG. 2F shows the second isolation layer 55 and the first insulation layer 53a are sequentially removed by an isotropic etching process to form a device isolation oxide film of a desired portion. Subsequent progression of the oxidation process (SACRIFITIAL OXIDATION) and ion implantation (IMPLANTATION) follows the normal semiconductor manufacturing process.

The above is the process proceeding process according to the present invention. In the formation of the spacer 59, the oxide film 57a acts as a mask during the over etch and thus prevents the groove forming of the substrate silicon. The thickness of the thin oxide layer 61 that controls BIRD'S BEAK is not limited by the amount of OVER ETCH. Accordingly, the present invention provides a deeper sub-oxide oxide depth (Y3) (Y3X3) to improve the electrical properties of device isolation, and to control the thickness of the thin oxide film 61 that controls BIRD'S BEAK to the subsequent spacer etch ( SPACER ETCH) has the advantage of being able to take less without being affected.

Claims (5)

Sequentially stacking a first insulating film 53 and a second insulating film on the semiconductor substrate 51 to sequentially form a pad oxide film and an active nitride film; Patterning the second insulating layer by a photolithography process; Forming an oxide film (57) with a predetermined thickness on the exposed portion of the first insulating film by using the patterned second insulating film (55) as a mask; Isotropically etching the oxide film 57 so that only a portion of the center portion 57a of the oxide film formed to the predetermined thickness is removed, and a predetermined portion of the first insulating film under the second insulating film is also removed. Forming a thin oxide film (61) on the portion from which the oxide film is removed by thermal oxidation; Depositing polysilicon on the resultant and over-etching it by an anisotropic etching to form polycrystalline silicon spacers 59 on sidewalls of the patterned second insulating layer 55; And selectively performing an oxidation process on the silicon substrate to form a device isolation film (63). 2. The method of claim 1, wherein the oxide film has a thickness in the range of about 600-1500 GPa. 2. The method of claim 1 wherein the thin oxide film (61) is formed to a thickness of about 40 to 150 microns by thermal oxidation. The method of claim 1, wherein when the polysilicon spacer 59 is formed, a portion Y2 formed due to overetching is formed on the sidewall of the second insulating layer 55 to be smaller than the thickness of the remaining oxide film 57a. Device isolation method of a semiconductor device. The method of claim 1, further comprising sequentially removing the second insulating layer 55 and the first insulating layer 53a by an isotropic etching process after the spacer 59 is formed and the oxidation process 63 is performed. A device isolation method for a semiconductor device.