KR0155620B1 - Pulse width control circuit of semiconductor memory device - Google Patents

Abstract

The present invention relates to a pulse width control circuit of a semiconductor memory device, comprising: an inactivation pulse generator for applying a deactivation pulse, an activation pulse from an external activation pulse generator, and an inactivation pulse generator; A semiconductor for controlling the width of the output pulse by the active pulse and the inactive pulse is provided with a pulse input part which does not receive a deactivation pulse, and a latch part which latches and outputs an active pulse and an inactive pulse from the pulse input part for a predetermined time. As a pulse width control circuit of a memory device, a latch circuit is used in comparison with a delay stage consisting of a delay device, and the circuit does not become large according to the width of the output pulse. An effective feature is that it can generate a pulse having a stable value.

Description

Pulse Width Control Circuit of Semiconductor Memory Device

1 is a schematic circuit diagram for explaining the structure of a conventional pulse width control circuit.

2 is a circuit diagram illustrating a conventional pulse width control circuit adopted in an actual semiconductor memory.

3 is a timing diagram for explaining signal states in respective portions of a conventional pulse width control circuit.

4 is a schematic circuit diagram for explaining the configuration of the pulse width control circuit of the present invention.

FIG. 5 is a circuit diagram illustrating the implementation of the pulse width control circuit of the present invention in an actual semiconductor memory device. FIG.

6 is a timing diagram for explaining signal states in respective parts of the pulse width control circuit of the present invention.

7A and 7B are block diagrams illustrating an embodiment of an inactive pulse generator employed in the pulse width control circuit of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for controlling the pulse width of a semiconductor memory device, and in particular, to generate a stable pulse width without using a delay circuit in generating a pulse having a long width. to be.

Conventional pulse width control circuits, as shown in Figure 1, when a pulse signal (AP: activiation pulse) having a relatively small width through the input stage, the delay unit for delaying this signal and the original signal and the delayed signal In addition, it consists of a pulse width control part consisting of an inverted element and a gate of a gate that generates a pulse width controlled signal (PCS) which is an output signal.

2 shows an example in which the circuit is actually applied to a semiconductor memory device.

The circuit detects an address buffer ADBUF that receives input signals AxO..AxN, AyO..AyN, AzO..AzN from outside, and detects a change in address by detecting a change in the address buffer for the signal. an address transition detector (hereinafter referred to as 'ATD') that generates one shot pulse, which is a transition detection signal (ATDxO..ATDxN, ATDyO..ATDyN, ATDzO..ATDzN); There is an address transition detection summation unit (hereinafter referred to as 'ATDSUM'), which is a portion of the pulses generated from various ATD circuits, and the same pulse width control as the circuit illustrated in FIG. The circuit is connected to output a signal PCS in which the pulse width is controlled.

At this time, the delay unit is usually configured by using a plurality of inverting elements and capacitors.

The operation of the circuit will now be described with reference to FIG. 3, which is a timing diagram in which signal states in the respective parts shown in FIG. 2 and FIG.

When a signal is applied to an address pad from the outside and input to a specific address buffer, when a change is generated in a specific ATD circuit connected to the specific address buffer to generate a short pulse signal, the ATDSUM circuit connected to each ATD circuit detects all signals. Together they generate a short pulse signal (ATDSUM). This signal ATDSUM passes through a pulse width control circuit to obtain a PCS signal which is a pulse of a desired length. At this time, the delay unit in the pulse width control circuit generates a signal Dout which is slightly delayed compared to the non-delayed signal Din, and overlaps the two signals to obtain a signal having a larger width than the signal before passing through the delay unit. By repeating this operation, the desired pulse width can be obtained.

In the related art, in order to increase the pulse width of an input signal, a delay stage for delay is required by increasing an input pulse using a delay circuit, and this delay stage has a problem that increases in proportion to the desired pulse width. In addition, there is a possibility that a mismatch of an output pulse may occur by overlapping an input pulse with a signal output through a delay stage.

In the present invention, a delay stage is provided and used to control the output pulse width, thereby increasing the circuit area by installing the delay stage and increasing the pulse width by overlapping the output signal at the delay stage and the input signal. Accurate and stable output pulses are provided by providing a latch section for latching an input pulse and an inactive pulse generator for applying an inactive pulse for changing an input signal to the latch section in order to prevent the delay stage from mismatching the output pulse caused by the output pulse. A pulse width control circuit of a semiconductor memory device for providing a.

The present invention provides a deactivation pulse generation unit (DAPG) for applying a deactivation pulse, an activation pulse from an external activation pulse generator and an inactivation pulse from an inactivation pulse generator. and a latch input unit for receiving a deactiviation pulse, and a latch unit for outputting the active pulses and the inactive pulses from the pulse input unit for a predetermined time.

Based on the pulse width control circuit of the semiconductor memory device having such a structure, a capacitor may be connected between the pulse input unit and the latch unit to determine the initial value of the output value to 'low' or 'high' to the latch unit. The other end is connected, for example, to the supply voltage Vcc. Therefore, when no pulse is applied to the pulse input unit, the supply voltage Vcc is applied to the input node of the latch unit so that the output value passing through the latch unit becomes 'low'. If the inverting element is connected to the front end or the rear end of the latch portion, the state of the output can be changed.

In addition, the latch unit may be configured as a loop circuit composed of two inverting elements. In this case, the driving capability of the inverting element forming the latch unit is not very large, and to compensate for this, 2n (n = 1) is provided at the rear end of the output node of the latch unit. A stable output pulse can be obtained by forming two inverting elements.

The pulse width control circuit of the semiconductor memory device of the present invention will be described with reference to the drawings as follows.

4 is a circuit diagram exemplified for explaining the configuration of the pulse width control circuit of the semiconductor memory device of the present invention.

The present invention has a pulse input section comprising an NMOS transistor receiving an active pulse which is a short pulse from an ATDSUM circuit, and a PMOS transistor receiving an inactive pulse. At this time, the NMOS transistor is connected to the gate ATDSUM circuit is an active pulse generator, one end of the channel is connected to the ground power supply (Vss), one end of the other channel is connected to the output node of the pulse input unit. In addition, the PMOS transistor has a gate connected to an inverting element connected to the inactive pulse generator, one end of the channel is connected to the supply voltage Vcc, and one end of the other channel is connected to the output node of the pulse input unit.

The pulse input unit output node between two MOS transistors constituting the pulse input unit is connected to the input node of the latch unit, and a capacitor connected to the supply voltage Vcc is connected to initialize a signal applied to the input node of the latch unit.

The latch unit is a green circuit consisting of two inverting elements, INV1 and INV2. In addition to the input node connected to the output node of the pulse input unit, an output node to the output terminal is formed.

A plurality of inverting elements formed to output a pulse applied from the latch portion in a more stable state are connected to the output terminal. In some cases, the connection of the inverting element to the output terminal can be omitted. In addition, the number of inverting elements of the output stage can be formed into 2n or 2n _-1 (n = 1, 2, ...) according to the desired output pulse type. Since the same state is desired, two inverting elements were used.

5 illustrates an example in which the pulse width control circuit of the semiconductor memory device of the present invention is applied to an actual semiconductor memory device.

This circuit includes an address buffer ADBUF that receives input signals AxO..AxN, AyO..AyN, AzO..AzN from the outside, and an address transition detection signal ATD circuit that generates one shot pulse, which is ATDxO..ATDxN, ATDyO..ATDyN, ATDzO..ATDzN), and ATDSUM circuit that combines the pulses from several ATD circuits. To this, a pulse width control circuit such as the circuit illustrated in FIG. 4 is connected to output a signal PCS in which the pulse width is controlled.

The operation of the circuit will now be described with reference to FIG. 6, which is a timing diagram in which signal states in the respective parts shown in FIG. 5 and FIG. 5 are illustrated.

When a signal is applied to an address pad from the outside and input to a specific address buffer, when a change is generated in a specific ATD circuit connected to the specific address buffer to generate a short pulse signal, the ATDSUM circuit connected to each ATD circuit detects all signals. In addition, a short pulse signal ATDSUM is generated as an active pulse signal. This signal ATDSUM turns on the NMOS transistor of the pulse input section and makes the output node state of the pulse input section low.

The state of the output node of the pulse input unit is applied to the input node of the latch unit. In this case, the role of the capacitor for the initial value connected between the pulse input unit and the latch unit is smaller than the current supply capability of the MOS transistors constituting the pulse input unit. By using, once the output node of the pulse input unit becomes low by the ATDSUM signal, the low value can be input to the input unit of the latch unit without the influence of this capacitor.

The signal latched in this latch portion can continue the same output of high value while continuing the loop circuit composed of the inverting element.

However, after a certain time from the inactive pulse generator, when the inactive pulse is supplied, a signal is applied to the PMOS transistor through the inverting element constituting the pulse input unit, and when the PMOS transistor is turned on, the output node of the pulse input unit is supplied. The voltage (Vcc) level becomes high.

When the high state is applied to the input node of the latch unit, the latch unit outputs the low state.

As described above, the output pulse of the pulse width control circuit of the semiconductor memory device of the present invention is applied with an inactivation pulse (DAP: deactiviation pulse) generated in the inactive pulse generator from the time point when the ATDSUM signal, which is an active pulse from the ATDSUM circuit, is applied. You can get the active pulse until the moment.

7 (a) and 7 (b) are block diagrams showing two embodiments of the inactive pulse generator used in the pulse width control circuit of the semiconductor memory device of the present invention.

FIG. 7A illustrates a dummy sense amplifier connected to a dummy cell, and detects a change in the dummy cell and generates the inactive pulse.

FIG. 7 (b) uses a sense amplifier connected to a cell array, and detects a change in cell data and generates it as an inactive pulse.

The present invention has the advantage that the circuit is not large according to the width of the output pulse by using a latch circuit, compared to simply using a delay stage consisting of a delay element in order to increase the pulse width of the semiconductor memory device. An effective feature is that the latch can generate a pulse having a stable value.

Claims (8)

In the pulse width control circuit of a semiconductor memory device, an inert pulse generator for applying a deactivation pulse, an activation pulse from an external active pulse generator, and an inactive pulse from the inactive pulse generator and a pulse input unit configured to receive a deactiviation pulse, and a latch unit which latches and outputs the active pulse and the inactive pulse from the pulse input unit for a predetermined time, thereby controlling the width of the output pulse by the active pulse and the inactive pulse. Pulse width control circuit of memory device. The pulse width control circuit of claim 1, wherein the pulse input unit comprises two different conductive MOS transistors connected in series between a supply voltage Vcc and a ground power supply Vss. 3. The pulse input according to claim 1 or 2, wherein the pulse input unit is connected to a gate terminal with an active pulse connected to a gate bias, one channel is connected to a ground power supply (Vss), and the other channel is connected to an output node to the latch unit. A PMOS transistor connected to the NMOS transistor connected to the gate terminal, a non-active pulse connected to a gate bias, one channel connected to a supply voltage Vcc, and the other channel connected to an output node to the latch unit; And an inverting element receiving an inactive pulse and applying an inverted pulse to the PMOS transistor. The pulse width control circuit of claim 1, wherein the latch unit comprises a loop circuit including two inverters and has an input node and an output node. 2. The pulse width control circuit of claim 1, wherein 2n (n = 1, 2, ...) inverting elements are added to the rear end of the latch output stage to output stable output pulses. 2. The pulse width control circuit of claim 1, wherein a capacitor is provided between the pulse input section and the latch section to set an initial value for the input to the latch section to a supply voltage (Vcc). The pulse width control circuit of claim 1, wherein the inactive pulse generator is configured to detect an output of a sense amplifier that amplifies cell data of the semiconductor memory device to generate a short pulse. The pulse width control circuit of claim 1, wherein the inactive pulse generator is configured to detect an output of a dummy sense amplifier for amplifying dummy cell data of the semiconductor memory device to generate a short pulse.