KR0152838B1 - Data transmitting apparatus for 24/25 modulation of dvcr - Google Patents

Abstract

The present invention relates to a 24/25 modulation data transmission device for digital VLC, comprising: a divider for dividing a main clock pulse into 1/8 to generate an input byte clock pulse; A first-in, first-out memory for storing input data according to the input byte clock pulses of the frequency divider during an allocated dummy time; A transmission control unit which outputs an output byte clock pulse and a transmission signal every 25 bits of the input data; A data transfer unit transferring input data input by the first-in first-out memory according to the output byte clock pulse of the transmission control unit; According to the transmission signal of the transmission control unit, it consists of a parallel / serial conversion unit for transmitting the input data delivered by the data transfer unit to the 24/25 modulation device by one bit, the configuration is simple and the frequency difference before and after 24/25 modulation It was made to disappear.

Description

Digital VRL's data transmission device for 24/25 modulation

1 is a diagram of a typical 24/25 modulation device.

2 is a block diagram of a data transmission device for 24/25 modulation of the present invention Digital VR.

3 is an angle waveform diagram of FIG. 2.

4 is a tape recording pattern diagram in FIG. 1 or FIG.

* Explanation of symbols for the main parts of the drawings *

102: 24/25 modulation device 200: data transmission device

201: First-in, first-out memory 202: Data transfer unit

203: parallel / serial conversion unit 204: divider

205: transmission control unit 205a: counter

205b: signal output unit

The present invention relates to a data transmission device for 24/25 modulation of a digital VCR, and transmits input data to a 24/25 modulation device without using a PEL circuit. It relates to a data transmission device for / 25 modulation.

In general, 24/25 modulation means inserting one bit of '0' or '1' into every 24 bits of input data corresponding to one track in order to distinguish between tracks and tapes of tape in digital VLC. It means converting into bits. [See Fig. 4 (a) and (b)].

FIG. 1 is a diagram related to a 24/25 modulation device that converts 24 bits of input data into 25 bits.

In this case, the digital V data transmission device for modulation of 24/25 modulation, as indicated by reference numeral '200' in FIG. 1, is an ECC (Error Correction Code) that controls the amount of input data under the control of the controller 100. Installed between the encoder 101 and the 24/25 modulation device 102, and receives the input data from the ECC encoder 101 and transmits it to the 24/25 modulation device 102. Digital VRL's data transmission device for 24/25 modulation is composed of PLL (PLL: Phase-Locked Loop) circuit.

The problem with the conventional digital data transmission device for 24/25 modulation of VR. The use of the PEL circuitry complicates the configuration and causes frequency differences before and after 24/25 modulation.

The present invention has been devised in view of the above-mentioned conventional problems, and the data for digital VLC's 24/25 modulation is simplified by not using the PEL circuit and the frequency difference is not seen before and after 24/25 modulation. An object is to provide a transmission device.

According to the present invention, the data transmission device for 24/25 modulation of the digital VLC of the present invention, as shown in FIG. 2, divides the main clock pulse (fout) by 1/8 to generate an input byte clock pulse. 204; A first-in, first-out memory 201 that stores input data according to the input byte clock pulses of the divider 204 during an allocated dummy time; A transmission control unit 205 for outputting an output byte clock pulse and a transmission signal every 25 bits of the input data; A data transfer unit 202 which transfers input data input by the first-in first-out memory (FIFO) 201 according to the output byte clock pulses of the transmission control unit 205; In accordance with the transmission signal of the transmission control unit 205, the parallel / serial conversion unit 203 for transmitting the input data transmitted by the data transfer unit 202 to the 24/25 modulation device 102 of FIG. It is composed of

Hereinafter, the operation will be described in detail.

In the present invention, a system clock pulse, i.e., main clock pulse (fout) as shown in (a) of FIG. 3, solves all the necessary clock problems. The first main clock pulse (fout) input by the divider (204) Dispense 1/8.

3B is a waveform of an input byte clock pulse divided by the divider 204 and appearing at the output side of the divider 204. The input byte clock pulse is input to the first-in first-out memory 201.

The first-in first-out memory 201 stores input byte clock pulses input from the divider 204 during the dummy time allocated repeatedly in the order of 3 bytes, 4 bytes, 4 bytes, and 4 bytes. 90 bytes of input data of FIG. 4C are sequentially stored by the dummy control pulse inputted through the input byte clock pulse and the first and gate AND1. Done.

On the other hand, the counter 205a of the transmission control unit 205 receives the main clock pulse fout and starts to count the clock of the main clock pulse fout. Output byte clock pulses as shown in (c) are output and input to the first-in first-out memory 201 and the data transfer unit 202, and simultaneously to the signal output unit 205b of the transfer control unit 205. The data transfer unit 202 has three flip-flops FF1 to FF3.

The first-in first-out memory 201 that receives the output byte clock pulses inputs the input data stored in the data transfer unit 202, and the data transfer unit 202 receives the first-in first-out memory (in accordance with the output byte clock pulses). The input data input by 201 is transmitted to the parallel / serial converter 203.

In addition, when the first-in first-out memory 201 and the data transfer unit 202 receive the output byte clock pulse, the signal output unit 205b of the data transfer unit 202 received as shown in FIG. The transmission signal is output and input to the parallel / serial conversion unit 203.

As a result, this transmission signal is generated at the position of the 25th bit of the input data.

The second and gate AND2, which is a reset unit of the transfer control unit 205, resets the counter 205a by outputting the reset signal when the transmission signal is output from the signal output unit 205b. Alternatively, when a reset signal is input from the outside, the counter 205a is reset.

The reset counter 205a starts counting again from the beginning.

Meanwhile, the parallel / serial conversion unit 203 transmits the input data previously transmitted by the data transfer unit 202 to the 24/25 modulation device 102 in order of 1 bit.

As described in detail above, the present invention inputs the input data to the 24/25 modulation device without using a complicated PEL circuit, so that the configuration is very simple and the frequency difference does not appear before and after the 24/25 modulation.

Claims (3)

A divider for dividing the main clock pulse into 1/8 to generate an input byte clock pulse; A first-in first-out memory for storing input data according to the input byte clock pulses of the frequency divider during an allocated dummy time; A transmission control unit which outputs an output byte clock pulse and a transmission signal every 25 bits of the input data; A data transfer unit for transferring input data input by the first-in first-out memory according to the output byte clock pulse of the transmission control unit; 24/25 modulation data transmission of the digital V-C has a parallel / serial conversion unit for transmitting the input data delivered by the data transfer unit to the 24/25 modulation device by one bit according to the transmission signal of the transmission control unit Device. The counter of claim 1, wherein the transmission control unit generates an output byte clock pulse when the number of pulses counted by the main clock pulse is 24, and a transmission signal when the output byte clock pulse is generated at the counter. And a reset unit for resetting the counter and counting again from the beginning when the signal output unit generates a transmission signal or when a reset signal is input from the outside. Data transmission device for / 25 modulation. The apparatus of claim 1, wherein the dummy time is repeatedly allocated in the order of 3 bytes, 4 bytes, 4 bytes, 4 bytes.