KR0151530B1 - Receiving and displaying circuit suitable for searching device - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs; It is a technology related to signal reception and display of surveillance equipment.

2. The technical problem to be solved by the invention; It provides a signal receiving and display circuit suitable for surveillance equipment that can guarantee the reception of accurate and reliable data.

3. Summary of the Solution of the Invention; A line receiver for receiving a clock and data which are independently applied to a signal receiving circuit suitable for monitoring equipment, a counting clock generator for generating a monostable pulse in response to the clock and providing it as a counting clock; A counting control unit for outputting an enable signal and a latch clock, and a converting unit operating in response to the enable signal of the counting control unit and converting the data output through the line receiver into parallel data in response to the counting clock. And a data latch unit for latching the parallel data in response to the latch clock, a buffer unit for storing and outputting the parallel data output from the data latch unit, and counting and decoding an internally oscillated clock to buffer the buffer. Applying the input / output control signal to the And a driving signal generator for generating a blanking pulse for the display and a driving signal for driving the display element.

4. Significant use of the invention; It is suitably used for surveillance equipment.

Description

Signal reception and display circuit suitable for surveillance equipment

1 is a block diagram of a signal receiving and display circuit according to the present invention;

2 is an operation timing diagram according to FIG.

The present invention relates to a circuit for monitoring equipment that receives a signal provided from a transmission system and displays it as a letter or number, and more particularly, to receive and display a clock and data among signals provided by the transmission system through independent paths. The present invention relates to a signal receiver and a display circuit which can reduce a data reception error.

In general, signals provided at the transmission side of a communication system are roughly divided into clocks and data, and signals including them are applied to a receiving system through one transmission path. Therefore, the receiving side extracts the data and the clock from the received signal and processes the data by the recovered clock. If there is a signal received due to a misalignment or a distortion of the transmission path in the processing of the data, the processed data contains an error. In the field of surveillance or surveying, which requires more precise and reliable data, the design of data processing should be considered more carefully.

In conventional monitoring equipment, a signal is applied through a line in a transmission system to provide display information to the display circuit and a display circuit which simultaneously displays letters or numbers of five (4, 5) digits. Receiving circuits are known in the art. The signal receiving circuit in the reception system for the conventional surveillance equipment has a communication protocol with the transmission system set in advance, and receives a signal according to such a protocol, which is complicated in terms of hardware and software, and performs reception. The circuit was very complicated. In addition, since a method of extracting clock and data from a signal applied through one line and processing them in synchronism is used, an error often occurs in the data, and a display circuit displaying the same cannot achieve the proper display function. This has been.

Accordingly, it is an object of the present invention to provide a signal receiving and display circuit suitable for monitoring equipment that can solve the conventional problems as described above.

Another object of the present invention is to provide a signal reception and display circuit suitable for monitoring equipment that can ensure the reception of more accurate and reliable data.

Another object of the present invention is to provide a signal reception display circuit which can reduce a reception error of data by receiving and displaying a clock and data among signals provided in a transmission system through independent paths.

According to an aspect of the present invention for achieving the above objects, a line receiver for receiving a clock and data applied independently of each other, and generates and counts a monostable pulse in response to the clock output through the line receiver. A counting clock generation unit serving as a clock, a counting control unit counting the clock to output an enable signal and a latch clock, and a reset signal that is operated and applied in response to the enable signal of the counting control unit, and is cleared A conversion unit for converting the data output through the line receiver into parallel data in response to the counting clock, a data latch unit for latching the parallel data in response to the latch clock, and a buffer input / output control signal applied thereto. In response to the output from the data latch portion Counting and decoding a buffer for storing and outputting the output, the internal oscillating clock to apply the input and output control signal to the buffer and generates a blanking pulse for the display of the segment and a drive signal for driving the display element A signal receiving circuit including a driving signal generator; And a plurality of segment light emitting units capable of displaying one number or letter, and decoding the history data provided by the buffer unit in the signal receiving circuit in response to the blanking pulse and corresponding to the driving signal. And a data display circuit for displaying the decoded data. The driving signal generation unit generates an oscillation unit for generating the oscillation clock, a division unit for dividing the oscillation clock at a predetermined division ratio, and outputs a division clock, and outputs counting data in response to the division clock and combines the counting data. A counter part cleared by the counting signal, a decimal decoder part receiving the counting data and providing a decimal decoded output as the input / output control signal, and a periodic short pulse in response to the division clock and the bright control input. A multi-vibrator generated, a blanking pulse generator for generating the blanking pulse in response to the short pulse, and an inversion driver for inverting the input / output control signal to generate the drive signal. Here, each of the devices used is a general-purpose device as a bipolar digital integrated circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, there are many specific details such as the name of a specific circuit, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It will be self-evident to those who have knowledge. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. In particular, the embodiment of the present invention has been illustrated the case of the circuit for monitoring equipment, it is possible to apply in the same way to a similar field. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

1 is a block diagram of a signal reception and display circuit according to the present invention. Referring to FIG. 1, in the signal receiving circuit 100, the clock and data receiving unit 2 including two dual differential line receivers SN55115 corresponds to the line receiver, and receives clock and data applied independently from each other. Receive through. The counting clock generator 4 composed of one 54LS221 generates a monostable pulse in response to the clock output through the line receiver 2 and provides it as a counting clock. The counting control unit 6 composed of one 54LS221 counts the clocks and outputs an enable signal and a latch clock. The first and second serial / parallel converters 8 and 10 each configured as 54LS164 are operated in response to the enable signal of the counting controller 6 and cleared in response to a reset signal applied through a reset input terminal R1. Shifting the data output through the shifted to the parallel data in response to the counting clock. The first and second range data latch units 12 and 14 each configured as 54ALS574 latch and output the parallel data in response to the latch clock. The first and second buffers 16 and 18 respectively configured as 54LS244 correspond to the buffer unit, and store the parallel data output from the first and second range data latch units 12 and 14 in response to an applied buffer input / output control signal. And output.

The driving signal generator 150 counts and decodes an internally oscillated clock to apply the input / output control signal to the buffer unit, and generates a blanking pulse for displaying a segment and a driving signal for driving a display element. Here, the parts are included in the signal receiving circuit 100.

The data display circuit 200 is connected to the signal receiving circuit 100 and has a plurality of segment light emitting units 22 capable of displaying a single number or letter, and is provided by the buffer units 16 and 18 in the signal receiving circuit 100. The parallel data is decoded in response to the blanking pulse and the decoded data is displayed on the plurality of segment light emitters 22 corresponding to the driving signal.

The driving signal generation circuit 150 may include an oscillator 101 generating the oscillation clock, a division unit 102 for dividing the oscillation clock at a predetermined division ratio, and outputting a division clock, and outputting counting data in response to the division clock. A counter unit 103 which is cleared by the combined counting signal in the counting data, a decimal decoder unit 105 which receives the counting data and provides a decimal decoded output as the input / output control signal, and the division clock and the bright control input (BRIGHTNESS) A multivibrator 106 generating a periodic short pulse in response to a control input), a blanking pulse generator 108 generating the blanking pulse in response to the short pulse, and inverting the input / output control signal to generate the driving signal. And inversion driving units 107 and 110.

The data display circuit 200 includes a segment decoder 20, a resistor 21, and a seven-segment light emitter 22 configured of CD45118.

2 shows an operation timing diagram according to FIG. 1 having the above configuration. Referring to FIG. 2, waveform 2A shows a clock of 2 megahertz applied through the clock input terminal CI. When the clock is applied, data such as waveform 2B may be provided to DI at the data input terminal of FIG. Here, the high section represents information 1 and the low section represents information 0. Waveform 2C is an enable signal output from the counting control unit 6 to the serial / parallel converter to maintain a high level in the operation section T1 and a low level in the non-operation section T2. Waveform 2D is the monostable pulse output by the counting clock generator 4, which is provided to the counting clock. In this case, the interval T3 is a point indicating a counting time point of the data. Waveform 2E is the latch clock provided by the counting control unit 6 to the latch units 12 and 14. Here, the period T4 indicates the latch point of the data.

Accordingly, the latched data is stored in the first and second buffers 16 and 18, and then is output as BCD data in response to an input / output control signal provided from the decimal decoder 105, and the resistor unit is decoded by the decoding operation of the segment decoder 20. Data decoded through 21 is provided to and displayed on the plurality of segment light emitters 22 corresponding to the driving signal.

Therefore, according to the present invention as described above, the reception error of the data can be reduced by receiving and displaying the clock and data of the signals provided by the transmission system through independent alarm. This is because the present invention provides a signal reception and display circuit suitable for surveillance equipment that can ensure the reception of more accurate and reliable data.

Although the above-described invention has been described and limited by way of example with reference to the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. .

Claims (4)

A signal receiving circuit suitable for surveillance equipment; A line receiver for receiving clocks and data applied independently from each other, a counting clock generator for generating a monostable pulse in response to the clock output through the line receiver and providing the counting clock as a counting clock, and counting the clocks A counting control unit that outputs an enable signal and a latch clock, and a data that is cleared in response to a reset signal that is operated and applied in response to the enable signal of the counting control unit, and that outputs data through the line receiver to the counting clock. A conversion section for converting the data into history data, a data latch section for latching the parallel data in response to the latch clock, and the parallel data output from the data latch section in response to an applied buffer input / output control signal. Output buffer and clock generated internally And a driving signal generator for counting and decoding the signal to apply the input / output control signal to the buffer unit, and generate a blanking pulse for displaying a segment and a driving signal for driving a display element. A display circuit suitable for monitoring equipment, the display circuit having a plurality of segment light emitting parts capable of displaying a single number or character, decoding parallel data received in response to an applied blanking pulse, and transmitting the decoded data to an applied driving signal. A data display circuit displayed on the corresponding segment light emitting unit, an input signal for counting and decoding an internally oscillated clock to control parallel data input to the data display circuit, a drive signal inverting the input signal, And a driving signal generator for generating and outputting a blanking pulse for displaying the segment. A signal reception and display circuit suitable for surveillance equipment; A line receiver for receiving a clock and data applied independently of each other, a counting clock generator for generating a monostable pulse in response to the clock output through the line receiver and providing the counting clock as a counting clock, and counting the clock A counting control unit that outputs an enable signal and a latch clock, and a data that is cleared in response to a reset signal that is operated and applied in response to the enable signal of the counting control unit, and that outputs data through the line receiver to the counting clock. A conversion section for converting the parallel data into parallel data, a data latch section for latching the parallel data in response to the latch clock, and the parallel data output from the data latch section in response to an applied buffer input / output control signal. Output buffer and clock generated internally Counting and decoding the received signal including the buffer unit is applied to the input and output control signal and the driving signal generating section for generating a drive signal for the drive of the blanking pulse and the display element for the display of the segment circuit; And a plurality of segment light emitting units capable of displaying one number or letter, and decoding the parallel data provided from the buffer unit in the signal receiving circuit in response to the blanking pulse to thereby generate the segment light emitting unit corresponding to the driving signal. And a data display circuit for displaying the decoded data. 4. The driving signal generator of claim 3, wherein the driving signal generator comprises: an oscillator for generating the oscillation clock, a divider for dividing the oscillation clock at a predetermined division ratio, and outputs a divided clock; A counter section for outputting and clearing by the combined counting signal in the counting data, a decimal decoder section for receiving the counting data and providing a decoded output as the input / output control signal, and the division clock and bright control input. A multivibrator for generating a periodic short pulse in response to the second pulse, a blanking pulse generator for generating the blanking pulse in response to the short pulse, and an inverting driver for inverting the input / output control signal to generate the driving signal. It is a circuit characterized by.