KR0149769B1 - Device and implementation method of phased locked(tracking)loop and decision feedback equalizer with connection structure - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Crystal feedback equalizer and phase tracking loop device with coupling structure

2. The technical problem to be solved by the invention

If there is phase noise, the decision feedback equalizer 1 makes a bad decision, which adversely affects the output of the decision feedback equalizer 1 until this value completely exits the feedback FIR filter 4. To solve the problem of adversely affecting the phase tracking loop 20 connected to the rear end.

3. Summary of Solution to Invention

An operation switching means for switching between an equalizer, a phase tracking loop device, an equalizer convergence detector for detecting the convergence of the equalizer, and an operation switching between the equalizer and the phase tracking loop device according to the convergence detection of the equalizer convergence detector In order to prevent interference between symbols in the residual sideband modulation method receiver and to remove phase noise, the operation switching means is switched to the equalizer to reduce the interference between symbols of initial data received by the receiver. An equalizer is operated, and then the equalizer convergence detector simultaneously operates the equalizer and the phase tracking loop device in accordance with the equalizer convergence detection.

4. Important uses of the invention

A receiver of a digital communication system with residual sideband and single sideband modulation.

Description

Crystal feedback equalizer and phase tracking loop device with coupling structure and its implementation method

1 shows a typical decision feedback equalizer.

2 shows an eight-level VSB receiver having a combined structure of an equalizer and a phase tracking loop.

3 is a view showing a coupling structure of a phase tracking loop of an equalizer according to the present invention.

4 is a complex signal generated by the complex signal generator 45 Showing the real axis-imaginary axis relationship.

* Explanation of symbols for main parts of the drawings

1: crystal feedback equalizer 20: phase tracking loop device

40: forward FIR filter 45: complex signal generator

50: complex multiplier 53: digital VCO

58 switch 62 equalizer convergence detector

The present invention relates to a digital communication system of a residual sideband and a single sideband modulation method, and more particularly to a decision feedback equalizer and a phase tracking loop device for removing phase noise to prevent interference between symbols generated by a transmission channel. A device coupled to each other and a method of implementing the same.

In general, receivers of digital communication systems use channel equalizers and carrier recoverers to improve reception performance. The channel equalizer is used to prevent intersymbol interference caused by a transmission channel. The carrier recoverer removes the frequency error and phase error of the received signal. A phase tracking loop device is also provided after the channel equalizer to track the phase of the carrier signal.

1 shows an example of a channel equalizer used in a receiver of a digital communication system. FIG. 2 shows a structure in which the channel equalizer and the phase tracking loop connected to the rear end of the channel equalizer of FIG. This FIG. 2 architecture is an example of use in a US 8-level VSB receiver.

First, the operation of the channel equalizer will be described with reference to FIG. The channel equalizer of FIG. 1 is a general decision feedback equalizer. The decision feedback equalizer has a forward FIR filter 2, a feedback FIR filter 4, a level determining section 8, a delay section 10, an adder 12 and a switch. It consists of (14). The internal configurations of the forward FIR filter 2 and the feedback FIR filter 4 are already known. The output value of the forward FIR filter 4 is The filter output value of the feedback FIR filter (4) to be. The forward FIR filter 2 removes the pre-ghost of the data Din input from the filter elements in front of the center tap and posts the data Din in the filter elements of the center tap. -Band-filters the input data Din by eliminating post-ghosts.

The filtering output value (filtered symbols) of the forward FIR filter 2 is applied to the level determining section 8 via an adder 6, and the level determining section 8 determines the level of the filtered symbol. The symbol level determination is performed when the symbol value input to the level determination section 8 is close to a preset symbol level (e.g., -3, -1, +1, +3, etc.). Determined by the symbol level value. The output of the level determining section 8 is applied to the feedback FIR filter 4 which is delayed by a predetermined time through the delay unit 10. The role of the retarder 10 is to prevent the ghost area that can be removed by the forward FIR filter 2 from overlapping with the ghost area that can be removed by the feedback FIR filter 4.

Accordingly, the number of delay elements of the retarder 10 is required by the number of taps + 1 of the filter element (located at the rear end of the center tap) that is responsible for the post-ghosting of the forward FIR filter 2.

The feedback FIR filter 4 removes the ghost at this time when the forward FIR filter 2 has not completed the filtering process. For example, the forward FIR filter 2 actually filters the 3 μsec delay symbols, but delays more than this, for example, a symbol delayed by 5 μsec cannot be processed by the forward FIR filter 2. In this case, the feedback FIR filter 4 is used to remove this ghost. The subtractor 6 subtracts the filtering output value of the feedback FIR filter 4 from the filtering output value of the forward FIR filter 2, so that the output line 16 is completely filtered. Is output.

On the other hand, the training signal is applied as a promised signal sent from the transmitter to help the receiver adjust the correct filter coefficient of the equalizer. On the receiver side, the switch 14 is switched to the first stage while the training signal is applied, otherwise the switch 14 is transferred to the second stage. The subtractor 12 is a signal of the output line 16 while the switch 14 is switched to the first stage. Is reduced to the training signal applied through the switch 14 and the error signal Outputs The error signal Calculate the filter coefficients C (0) ..... C (M) of the forward FIR filter (2) and the filter coefficients b (0) ..... b (N) of the feedback FIR filter (4). To be a variable.

In FIG. 2, the channel equalizer 1 of FIG. 1 and the phase tracking loop device 20 connected to the rear end of the channel equalizer 1 are combined. Hereinafter, the operation of the phase tracking loop device 20 will be described with reference to FIG. 2.

Output signal of the decision feedback equalizer 1 Is applied to the complex signal generator 23 via the multiplier 22. The multiplier 22 feeds the gain control signal GC and the output signal fed back from the output terminal of the phase tracking loop device 20. Multiply by. The complex signal generator 23 is composed of a delay 46 and a digital filter 48. The complex signal generator 23 generates a one-dimensional signal applied through the multiplier 22 as a complex signal that is a two-dimensional signal. The delayer 24 delays the output signal of the multiplier 22 by a signal delay to the digital filter 26 so that the real axis component signal is delayed. Will output The digital filter 26 performs a Hilbert transform on the output signal of the multiplier 22 to form an imaginary axial component signal. Outputs

Therefore, the complex signal output from the complex signal generator 23 is a real axis component signal. And imaginary signal If you express it as exponential function Becomes Where A is the size, Is the residual phase error of the signal.

The complex signal output from the complex signal generator 23 Is applied to the complex multiplier 28. The complex multiplier 28 is initially a complex signal. Outputs as is. At this time, the complex signal output from the complex multiplier 28 Is applied to the error determining unit 30 to correct the phase error. The complex signal 4 is a diagram showing a real axis-imaginary axis relationship.

The error determining unit 30 estimates the phase correction value from the real axis signal and the imaginary axis signal of the applied complex signal. Calculate Phase correction prediction Is obtained as follows.

Phase correction prediction value obtained by the error determining unit 30 Is applied to the multiplier 22 as the phase gain control signal GC via the accumulator limiter 38. The multiplier 22 controls the phase gain to ultimately correct the phase error in the phase tracking loop device 20. In addition, the phase correction prediction value Is applied to the digital VCO 32. The digital VCO 32 is composed of an accumulator 36 and a sine / cosine table 34, and a phase correction predictor Read the value mapped to the sine / cosine table 34 corresponding thereto as an input. The sine / cosine table 34 has a complex signal Complex signal to correct phase error Is mapped. Thus the complex signal read Is output to the complex signal multiplier 28.

Hereinafter, the complex signal output from the complex signal generator 23 For the sake of convenience, the first complex signal is referred to as a complex signal applied from the digital VCO 32. Is called a second complex signal. The complex multiplier 28 multiplies the first complex signal by the second complex signal and outputs a corrected complex signal. That is, the complex multiplier 28 Outputs a corrected complex signal such as

The phase tracking loop device 20 of FIG. 2 continues the above operation until the phase error is completely eliminated.

However, when the crystal feedback equalizer 1 and the phase tracking loop device 20 have a structure as shown in FIG. 2, the following problems occur.

The decision feedback equalizer 1 shown in FIG. 1 sets and outputs the input signal Din of the feedback FIR filter 4 to a value determined by the most likely transmittable symbol. Therefore, in the presence of phase noise, the decision feedback equalizer 1 may make a wrong decision. In this case, an incorrect decision will affect the output of the decision feedback equalizer 1 until this value completely exits the feedback FIR filter 4. As a result, the performance of the crystal feedback equalizer 1 is deteriorated. Incorrect determination of the crystal feedback equalizer 1 also adversely affects the phase tracking loop 20. This adverse effect is caused because the equalizer and the phase tracking loop operate independently.

Accordingly, an object of the present invention is to provide an equalizer and a phase tracking loop device and an implementation method thereof which are combined to have excellent reception performance.

Another object of the present invention is to provide an equalizer and a phase tracking loop device combined to simultaneously remove intersymbol interference and phase noise in a transmission channel.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view showing a coupling structure of the crystal feedback equalizer 1 of FIG. 1 and the phase tracking loop device 20 shown in FIG. 2 according to the present invention. In FIG. 3, looking at the crystal feedback equalizer 1 while contrasting with FIG. 1 and looking for the phase tracking loop apparatus 20 while contrasting with FIG. 2 will more clearly understand the organic coupling structure of the present invention.

In FIG. 3, blocks belonging to the decision feedback equalizer 1 include a forward FIR filter 40, a subtractor 42, a level decision unit 68, a feedback filter 70, a subtractor 64 and a switch ( 66). The delay 46 of FIG. 3 is used as the delay 10 of FIG. In FIG. 3, blocks belonging to the phase tracking loop device 20 include a complex signal generator 45, a complex multiplier 50, and a multiplier 44, a delay 46, and a digital filter 48. It consists of the digital VCO 53 and the accumulator limiter 60 which consist of the error determination part 52, the accumulator 54, and the sine / cosine table 56. As shown in FIG.

The characteristic configuration in FIG. 3 is briefly described. The retarder 46 of FIG. 3 is also used as a retarder of the crystal feedback equalizer 1 and is also used as a retarder of the phase tracking loop device 20. Then, a switch 58 for on-off operation is newly added under the control of the equalizer converge detector 62 and the equalizer converge detector 62 for detecting the convergence of the equalizer. Equalizer convergence detector 62 outputs an error signal that is an output of subtractor 64. Detects convergence of the equalizer as an input and detects that the equalizer converges so that the switch 58 is turned on. A switch 58 is located between the sine / cosine table 56 of the digital VCO 53 and the complex multiplier 58, and the sine / cosine table 56 when the equalizer convergence detector 62 is on control. Second complex signal generated by Is applied to the complex multiplier 50.

Operational features of the present invention in accordance with the structural features of Figure 3 are as follows. In the present invention, the equalizer initial operation stops the operation of the phase tracking loop device. This is to reduce the error of the crystal level in the equalizer due to the phase noise. Therefore, the switch 58 is turned off in the equalizer initial operation. Therefore, the input data Din is passed through the subtractor 42, the multiplier 44, the delay 46, the real axis component signal line Re of the complex multiplier 50, the level determiner 68, and the feedback FIR filter 70. The control signal is applied to the subtractor 42 to prevent the interference of symbols. That is, the combined crystal feedback equalizer and phase tracking loop device initially operate as an equalizer.

However, even if the input data Din contains the phase noise so severe that the symbol cannot be properly determined by the level determining section 60, the complex signal generating section 45, the complex multiplier 50, the error determining section 52, Phase control is performed on the multiplier 44 through the accumulator limiter 60 to eliminate phase noise. As a result, the operation of the equalizer works correctly, and the equalizer convergence detector 62 detects the convergence of the equalizer. The equalizer convergence detector 62 then controls the switch 58 to be on, so that the switch 58 is on. When switch 58 is turned on, the combined crystal feedback equalizer and phase tracking loop device of FIG. 3 perform both operations to the crystal feedback equalizer and phase tracking loop device. Therefore, the organic coupling structure of FIG. 3 according to the present invention easily eliminates both phase noise and interference between symbols.

As described above, the present invention has an advantage of improving the performance of the receiver since the phase tracking loop devices of the equalizer are organically coupled to each other. It also has the advantage of reducing hardware complexity.

Claims (3)

A residual sideband and single sideband modulation method receiver comprising: a plurality of filter elements, forward filter means for first filtering the data so that the received data removes ghost components, and a plurality of filter elements, A feedback filter means for second filtering to remove the ghost components that cannot be removed from all the data filtered by the forward filter means, and a subtraction for outputting the output data of the forward filter means and the output data of the feedback filter means. A first complex signal generating means for generating a first complex signal by performing a predetermined delay and a Hilbert transform on the output of the subtracting means, the first complex signal and the first complex Complex signal multiplication means for multiplying a second complex signal for correcting a phase error of the signal and outputting a corrected complex signal; A level error means for determining the level of the real axis component signal of the signal to be one of preset levels and outputting it to the feedback filter, and a phase error from the real axis component signal and the imaginary axis component signal of the corrected complex signal of the complex multiplication means. Phase error prediction means for generating a predicted value, multiplication means positioned between the subtraction means and the complex signal generation means and multiplied by the output of the generated phase error prediction value and the subtraction means to output to the complex signal generation means; Second complex signal generating means for reading out the second complex signal corresponding to the generated phase error predicted value from a pre-mapped table and outputting the second complex signal; Equalizer convergence detecting means for detecting the convergence of the equalizer by subtracting the real axis component signal of the corrected complex signal; Bamboo blind is switched by detecting means the equalizer in response to the convergence detection of the second crystal having a binding structure that is characterized by a complex signal composed of a switching means for applying to the complex multiplication means feedback equalizer and the phase tracking loop apparatus. 2. The crystal feedback equalizer and phase tracking loop device according to claim 1, wherein the retarder of the complex generating means is used as a crystal feedback equalizer and a phase tracking loop retarder. Operation switching means for switching between an equalizer, a phase tracking loop device, an equalizer convergence detector for detecting the convergence of the equalizer, and switching between the equalizer and the phase tracking loop device according to the convergence detection of the equalizer convergence detector A method for preventing inter-symbol interference and removing phase noise in a residual sideband modulation method comprising: switching the operation switching means to the equalizer to reduce the interference between symbols of initial data received by the receiver; And a second process of operating the equalizer and the phase tracking loop device simultaneously according to the equalizer convergence detection in response to the first process. How to feature.