KR0148567B1 - Eprom semiconductor memory device - Google Patents

Abstract

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Description

Nonvolatile Semiconductor Memory

1 is a circuit diagram showing one embodiment of an EEPROM according to the present invention.

2 is a circuit diagram showing another embodiment of the EEPROM according to the present invention.

3 is a circuit diagram showing one embodiment of a decoder circuit of an EEPROM.

4 is a circuit diagram showing one embodiment of a ramp voltage generation circuit for generating a high voltage for erasing supplied to a source line.

5A to 5F are waveform diagrams for explaining the operation of the ramp voltage generation circuit.

6 is a circuit diagram showing one embodiment of a source line selection circuit.

7 is a circuit diagram showing one embodiment of a built-in high voltage generation circuit.

* Explanation of symbols for main parts of the drawings

XADB, YADB: Address buffer XDCR, YDCR: Address decoder

UDCR: Unit Circuit PA: Ultra Short Amplification Circuit

CONT: timing control circuit ERC, ERCl ~ ERCn: erase control circuit,

MBl ~ MBn: Memory blocks LVC1, LVC2: Level conversion circuit

OSC: Ring Oscillator Gl: NAND Gate Circuit

N1 to N3: inverter circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a nonvolatile semiconductor memory device, and to a technique effective for use in a nonvolatile memory device having, for example, an electrically rewritable floating gate type nonvolatile memory device having a 1 element / 1 bit configuration. .

A rewriteable floating gate type nonvolatile memory device having a 1 element / 1 bit structure in which one bit (1 memory cell) is composed of one floating gate type nonvolatile memory device is described, for example, in ISSCC88 Digest of Technical Papers, (p.132--133). The method of erasing the floating gate type nonvolatile memory device is discussed in the above document. Like all of the EPROM (Erasable Programmable Read Only Memory), all of the bits commonly apply a high voltage to the source line to collectively erase. The high voltage for erasing is to apply an external power supply directly through a switch MOSFET (insulated gate field effect transistor) or the like.

In the floating gate type nonvolatile memory device, since the source line is common to all the bits, there is a problem in that the erase mode is a single erase mode in which all data is erased in a batch, and partial erasing is not possible. In addition, according to the inventors' review, since the external power is directly applied to the source line via the switch MOSFET during the erasing operation, the potential of the source line increases rapidly, and immediately after the rise, the floating gate of the nonvolatile semiconductor memory device. A high electric field is applied between the source and the source. As a result, the action of the high electric field may lower or destroy the insulating film between the floating gate and the source, which may significantly affect the reliability of the information holding operation.

It is an object of the present invention to provide a nonvolatile semiconductor memory device which enables partial erasure of a memory array. Another object of the present invention is to provide a nonvolatile semiconductor memory device which prevents a decrease in reliability due to an erase operation.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Brief descriptions of representative ones of the inventions disclosed in the present application are as follows.

That is, a high voltage is selectively applied between the word line to which the control gate of the nonvolatile semiconductor memory device is coupled and the source line to which the source of the nonvolatile semiconductor memory device is coupled to direct charge accumulated in the floating gate toward the source line.

In addition, the nonvolatile semiconductor memory device to be erased has a characteristic of a ramp ratio that gradually increases from low voltage to high voltage at the potential of the source line to which the source is coupled.

According to the above means, partial erasing is possible in accordance with the division of the source line or the division of the word line, and it is possible to have a ramp ratio as a high voltage for erasing, so that an excessive strong electric field can be prevented between the floating gate and the source. .

FIG. 1 is a circuit diagram of one embodiment of a memory array unit of an electrically erasable programmable read only memory (EEPROM) to which the present invention is applied. Each circuit element of the same drawing is not particularly limited, but is formed in a semiconductor engine such as one single crystal silicon by a known manufacturing technique of a CMOS (complementary MOS) integrated circuit.

Although not particularly limited, an integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. The N-channel MOSFET is composed of a source region, a drain region formed on the surface of the semiconductor substrate, and a gate electrode made of polysilicon formed through a thin gate insulating film on the surface of the semiconductor substrate between the source region and the drain region. P-channel MOSFETs are formed in N-type well regions formed on the surface of the semiconductor substrate.

As a result, the semiconductor substrate constitutes a common substrate gate of several N-channel MOSFETs formed thereon, and the ground potential of the circuit is supplied. The N type well region constitutes the substrate gate of the P channel MOSFET formed thereon. The substrate gate, or N-type well region, of the P-channel MOSFET is coupled to the supply voltage V _CC (about 5V).

The integrated circuit may be formed on a semiconductor substrate made of single crystal N-type silicon. In this case, the N-channel MOSFET and the nonvolatile memory device are formed in the P-type well region, and the P-channel MOSFET is formed on the N-type substrate.

Although not particularly limited, in the EEPROM of this embodiment, a complementary address signal formed through the address buffer ADB receiving the X and Y address signals AX and AY supplied from an external terminal is supplied to the address decoder DCR. In the same figure, the address buffer ADB and the address decoder DCR are shown as the same circuit blocks XADB, DCR, YADB, and DCR, respectively. Although not particularly limited, the address buffers XADB and YADB are activated by an internal chip select signal ce to input address signals AX and AY at the external terminals, and are inversely opposite to the internal address signals in phase with the address signals supplied from the external terminals. A complementary address signal that becomes an address signal is formed. In addition, in the same figure and the following figure, 0 mark shows the external terminal provided in the integrated circuit.

The row (X) address decoder (X) DCR forms a selection signal for selecting the word line W in the memory array M-ARY in accordance with the complementary address signal in the address buffer XADB.

The column (Y) address decoder (Y) DCR forms a selection signal for selecting the data line D in the memory array M-ARY in accordance with the complementary address signal in the address buffer YADB.

The memory array M-ARY is composed of a memory device (nonvolatile memory device) having a stack gate structure having a control gate and a floating gate, word lines W1, W2 ..., and data lines D1-Dn. The memory device is not particularly limited, but has a structure similar to that of the EPROM. However, the erase operation is electrically performed by using the tunnel phenomenon between the floating gate and the source coupled to the source line as described below, which is different from the EPROM erasing method using ultraviolet rays.

In the memory array M-ARY, the control gates of the memory elements Q1 to Q3 (Q4 to Q6) arranged in the same row are connected to the corresponding word lines W1 (W2), respectively, and the memory elements Q1 to Q4 arranged in the same column. The drains (one region or one electrode) of Q3 and Q6 are respectively connected to the corresponding data lines D1 to Dn. The source (the other region or the other electrode) of the memory element is coupled to the source lines (common lines) CSl to CSn. That is, in this embodiment, since partial erasing is possible in one memory array M-ARY, several memory elements arranged in a matrix form are divided into n blocks in the vertical direction, and each block is representatively represented as the representative. The displayed source lines CSl and CSn are provided. P-channels supplying the N-channel MOSFETs Q18 and Q20 for turning on the source lines CSl to CSn and providing the ground potential V _SS of the circuit to the source lines CSl to CSn and the high voltage V _PP for erasing. MOSFETs Q17 and Q19 are prepared. These MOSFETs Q17, Q18, Q19, Q20 and the like are switched by the erase control circuits ERCl to ERCn.

The erase control circuits ERCl to ERCn turn on the P-channel MOSFETs Q17, Q19 and the like when the erase signals erl to ern described below are in the erase mode in which the signals erl to ern are at a high level. When the signals erl to ern are other than the low level erase mode, the N-channel MOSFETs Q18 and Q20 are turned on. As a result, the erase second circuits ERCl to ERCn selectively give the source lines CSl to CSn to the high voltage V _PP for the erase operation and the ground potential V _SS for the write / lead and the like. In the case of performing the collective erase operation on the entire memory array M-ARY, the signals erl to ern are all set to high level, so that the switch MOSFETs Q17 to Q19 and the like are all turned ON, and the high voltage for erasing is set. It is good to supply to the source of all the memory cells.

Although not particularly limited, when erasing, the data line of the block is connected to the erasing control circuit EDT through the floating state or through the column switches MOSFETs Q7 to Q9 and the selection gate (MOSFET Q33). The erase control circuit EDT is used to monitor the current flowing through the memory cell in which the erase operation is performed and to control the erase amount. That is, the erase control circuit EDT is used to prevent the memory cells from being erased excessively. In the case of erasing the data line in a floating state, the erase amount is set by a predetermined erase time. When the erase operation is performed with the data line in the floating state as described above, the select gate MOSFET Q33 and the erase control circuit EDT are deleted.

Although not particularly limited, in order to perform write / read in units of 8 bits, the memory array M-ARY is configured so that a total of eight sets is provided. In the same figure, one memory array M-ARY having n divided memory blocks as described above is exemplarily illustrated.

Each data line D1 to Dn constituting the one memory array M-ARY is connected to a common data line CD through a column (column) selection switch MOSFET Q7 to Q9 that receives a selection signal formed by the address decoder DCR (Y). do. The common data line CD is provided corresponding to each memory array. The common data line CD is connected to the output terminal of the data input buffer DIB for write which receives the write data input from the external terminal I / O via the switch MOSFET Q32. Similarly, in the other memory array M-ARY not shown, the same column select switch MOSFETs are provided for each of the data lines D1 to Dn, and a select signal formed by the address decoder YDCR is supplied corresponding to each column select switch MOSFET. do.

The common data line CD provided corresponding to the memory array M-ARY is coupled to the input terminal of the ultra-short amplification circuit PA described below via a switch MOSFET Q16. In addition, the ultra-short amplifier circuit PA constitutes an input stage circuit of the sense amplifier SA.

The common data line CD shown by way of example is connected to the source of the N-channel amplification MOSFET Q11 via the MOSFET Q16 which is turned ON by the read control signal sc. A P-channel load MOSFET Q12 is provided between the drain of the amplifying MOSFET Q11 and the power supply voltage terminal V _CC through which the ground potential V _SS of the circuit is applied via an external potential terminal V _SS at its gate. The load MOSFET Q12 operates to flow a precharge current through the common data line CD for a read operation.

가 공급된다.In order to increase the sensitivity of the amplifying MOSFET Q11, the voltage of the common data line CD passing through the switch MOSFET Q16 is the gate of the driving MOSFET Q13, which is an input of an inverted amplification circuit comprising the N-channel driving MOSFET Q13 and the P-channel loading MOSFET Q14. Supplied to. The output voltage of this inverted amplifier circuit is supplied to the gate of the amplifier MOSFET Q11. In order to prevent unnecessary current consumption in the non-operation period of the sense amplifier, an N-channel MOSFET Q15 is provided between the gate of the amplifying MOSFET Q11 and the ground potential point V _SS of the circuit. The operating timing signal of the sense amplifier is common to the MOSFET Q15 and the gate of the P-channel MOSFET Q14.

Is supplied.

는 로우레벨로 되어 MOSFET Q14는 ON상태로, MOSFET Q15는 OFF상태로 된다. 메모리 셀은 라이트된 데이타, 즉 유지하고 있는 데이타에 따라서 리드동작시의 워드선의 선택레벨(대략V_CC)에 대해서 높은 임계값 전압 또는 낮은 임계값 전압을 갖는다.Sense amplifier operation timing signal when reading memory cells

Becomes low level, MOSFET Q14 is turned ON and MOSFET Q15 is turned OFF. The memory cell has a high threshold voltage or a low threshold voltage with respect to the selection level (approximately V _CC ) of the word line during the read operation in accordance with the written data, i.e., the held data.

In the read operation, the memory cells selected by the respective address decoders X-DCR and Y-DCR (i.e., the memory cells instructed according to the X and Y address signals) are turned off regardless of whether the word lines are at the selection level. In this case, the common data line CD becomes a high level of a relatively low level by the current supplied through the MOSFETs Q12 and Q11. On the other hand, when the selected memory cell is turned ON because the word line is at the selection level, the common data line CD is at a low level of a relatively high level.

In this case, the high level of the common data line CD is limited to a relatively low potential by supplying the gate of the MOSFET Q11 with a relatively low level output voltage formed by the inverting amplifier circuit receiving this high level potential. On the other hand, the low level of the common data line CD is limited to a relatively high potential by supplying the gate of the MOSFET Q11 with a relatively high level of voltage formed by the inverting amplifier circuit receiving this low level potential. In this way, it is possible to speed up the read operation regardless of whether the common data line CD has a floating capacity or the like that limits the speed of signal change in the common data line CD so as to limit the high and low levels of the signal. . In other words, when reading data from several memory cells in sequence, the time until one level of the common data line CD is changed to the other level can be shortened. For such a high speed read operation, the conductance of the load MOSFET Q12 is set relatively large.

In addition, the amplification MOSFET Q11 performs an amplification operation of a gate ground type source input and transfers its output signal to the sense amplifier SA configured by the CMOS inverter circuit. The output signal of this sense amplifier SA is not particularly limited by the corresponding data output buffer DOB, but is amplified and output from the external terminal I / O. The write signal supplied from the external terminal I / O is transmitted to the common data line CD via the data input buffer DIB. The same input terminal circuit, the read circuit serving as the sense amplifier and the data output buffer, and the write circuit serving as the data input buffer are also provided between the common data line corresponding to the other memory block and the external terminal.

,

,

및 V_PP에 공급되는 칩인에이블신호, 출력인에이블신호, 프로그램신호 및 라이트/소거용 고전압과 X계의 내부어드레스 신호 ax에 따라서 내부제어신호 ce,

등의 내부타이밍신호, 소거신호 erl~ern 및 어드레스 디코더 XDCR, YDCR이나 데이타 입력버퍼 DIB에 선택적으로 공급하는 리드용 저전압 V_CC/라이트용 고전압 V_PP등을 형성한다. 또한, 상기 신호 sc는 상기 신호

를 위상반전하는 것에 의해 형성된다.Control circuit CONT is not particularly limited, but external terminal

,

,

And the internal control signal ce, according to the chip enable signal, the output enable signal, the program signal, and the high voltage for write / erase and the internal address signal ax of the X system supplied to V _PP .

Internal timing signals, erase signals erl to ern, and low voltage V _CC for reads and high voltage V _PP for selectively supplying to address decoders XDCR, YDCR or data input buffer DIB. In addition, the signal sc is the signal

Is formed by inverting phase.

가 로우레벨이고, 출력인에이블신호

가 하이 레벨이고, 프로그램신호

가 로우 레벨이면, 라이트모드로 되어 이것들의 신호에 응답해서 상기 제어신호 CONT는 다음에 기술하는 신호 및 전압을 출력한다. 상기 내부신호 ce 는 하이레벨로 된다. 그리고, 어드레스 디코더 회로 XDCR, YDCR 및 데이타 입력회로 DIB 에는 그 동작전압으로써 상기 전원전압 V_CC에 비해서 고전압인 고전압 V_PP가 공급된다. 이것에 의해 라이트되어야할 메모리 셀이 공급된 워드선의 전압은 상기 고전압 V_PP로 된다. 그리고, 플로팅 게이트에 전자를 주입해야 할 기억소자가 결합된 데이타선의 전압은 상기와 마찬가지로 고전압 V_PP로 된다. 이것에 의해 기억소자에 채널포화전류가 흐르고, 데이타선에 결합된 드레인 근방의 펀치오프 영역에서는 고전계에의 가속된 전자가 이온화를 일으키고, 고에너지를 갖는 전자, 소위 고온전자가 발생한다. 한편, 플로팅 게이트의 전압은 워드선이 결합된 콘트롤 게이트의 전압과 드레인 영역의 전압 및 기판과 플로팅 게이트 사이의 용량과 플로팅 게이트 및 콘트롤 게이트 사이의 용량에 의해서 결정되는 값으로 된다. 이것에 의해서 상술한 고온전자가 유인되어 플로팅 게이트의 전위는 부로 된다. 그 때문에 리드동작에서 콘트롤 게이트가 결합된 워드선의 전위가 선택상태(예를들면, V_CC)로 되어도 이 기억소자는 비도통 상태로 되게 된다. 이것에 대해서 상기 전자가 주입되지 않는 기억소자의 드레인은 상술한 라이트 모드시 기억소자의 드레인 근방에서의 핀치오프영역에서 고온전자가 발생하지 않는 낮은 레벨로 된다.Chip Enable Signal with High Voltage V _PP for Write / Erase

Is low-level, output enable signal

Is high level and program signal

If is low, the control mode CONT outputs the signals and voltages described below in response to these signals in the write mode. The internal signal ce becomes high level. The address decoder circuits XDCR, YDCR and the data input circuit DIB are supplied with the high voltage V _{PP which} is higher than the power supply voltage V _CC as their operating voltages. As a result, the voltage of the word line supplied with the memory cell to be written becomes the high voltage V _PP . The voltage of the data line coupled with the memory device to which electrons are to be injected into the floating gate becomes a high voltage V _PP as described above. As a result, a channel saturation current flows through the memory device, and accelerated electrons in the high electric field cause ionization in the punch-off region near the drain coupled to the data line, and electrons having high energy, so-called high temperature electrons, are generated. Meanwhile, the voltage of the floating gate is determined by the voltage of the control gate to which the word line is coupled, the voltage of the drain region, and the capacitance between the substrate and the floating gate and the capacitance between the floating gate and the control gate. As a result, the above-mentioned high-temperature electrons are attracted and the potential of the floating gate becomes negative. Therefore, even when the potential of the word line to which the control gate is coupled in the read operation is brought into the selected state (for example, V _CC ), the memory element is brought into a non-conductive state. On the other hand, the drain of the memory element in which the electrons are not injected is at a low level where no high-temperature electrons are generated in the pinch-off region near the drain of the memory element in the above-described write mode.

가 로우 레벨이고, 출력인에이블신호

가 로우레벨이고, 프로그램신호

가 하이레벨이며, 전압 V_PP가 라이트용 고전압이면, 검증모드로 되어 상기 제어회로 CONT는 다음에 기술하는 신호를 형성한다. 상기 내부신호 sc와 ce는 하이레벨로 된다. 이 검증모드에서 상술한 각 회로 XDCR, YDCR 및 DIB에는 그 동작전압이 상기와 같은 고전압 V_PP에서 낮은 전원전압 V_CC와 같이 전환되어 공급된다.Chip Enable Signal

Is low level and output enable signal

Is low level, program signal

If is high level and the voltage V _PP is a high voltage for writing, then the verification mode is entered and the control circuit CONT forms the signal described below. The internal signals sc and ce go high. In this verification mode, each of the above-described circuits XDCR, YDCR, and DIB is supplied with its operating voltage switched from the high voltage V _PP as described above to the low power supply voltage V _CC .

가 로우 레벨이고, 출력인에이블신호

가 로우레벨이고, 프로그램 신호

가 하이레벨이고, V_PP가 리드용 저전압(V_CC와 같은 레벨)이면, 상기 설명한 바와 같은 리드모드로 되어 상기 제어회로 CONT는 상기 내부신호 sc와 ce를 하이레벨로 한다.Chip Enable Signal

Is low level and output enable signal

Is low level, program signal

Is high level, and V _PP is a low voltage for read (at the same level as V _CC ), then the read mode as described above is set, and the control circuit CONT sets the internal signals sc and ce to a high level.

가 로우레벨이고, 출력인에이블신호

가 하이레벨이고, 프로그램신호

가 하이레벨이고, 전압 V_PP가 고전압이면, 소거모드로 되어 상기 제어회로 CONT는 다음에 기술하는 바와 같은 신호를 형성한다.Chip Enable Signal

Is low-level, output enable signal

Is high level, program signal

Is high level, and the voltage V _PP is high voltage, it is in the erase mode and the control circuit CONT forms a signal as described below.

The internal signal ce becomes high level (V _CC ) and the signal sc becomes low level (V _SS ). In addition to the combination of the above-described signals, a control signal for instructing the erase operation is supplied from an external terminal, and the erase mode is designated by setting the low level to form the signal as described above in the control circuit CONT. Also good. In this erase mode, input of an address signal specifying a block to be erased is executed through the X address buffer. Therefore, the internal signal ce becomes high level and the X address buffer is activated. At this time, the input address signal becomes the address signal ax supplied to the control circuit CONT, and the address signal supplied to the address decoder circuit XDCR is invalidated as described below.

In the erase mode, the X decoder circuit XDCR sets the entire word line to a non-selection level equal to the ground potential V _SS by the signal er. At this time, the address signal supplied to the X decoder circuit XDCR is invalid. However, the address signal ax through the address buffer XADB is supplied to the control circuit CONT and used to designate a memory block to be erased. In this case, as the address signal AX, an internal address signal corresponding to a predetermined n bit in the address signal AX supplied internally via an external terminal may be used. In this case, the n-bit internal address signal ax may be used to correspond one-to-one with each bit to the n-divided memory block. That is, each bit of the address signal corresponds to the erase signals erl to ern one to one. By such a configuration, memory blocks of any number of memory blocks in the n divided memory blocks can be erased. That is, the partial erasing of various combinations including the same batch erasing as the conventional one can be realized by the combination of the signals erl to ern.

Therefore, when the number of memory blocks is smaller than the number of bits of the external address signal AX, the number of bits of the internal address signal ax is smaller than the number of bits of the external address signal AX. In this case, the internal address signal corresponding to the rest of the external address signal is not supplied to the control circuit CONT, for example.

In the erase mode as described above, the entire word line is at a non-selection level equal to the ground potential, and a high voltage for erasing at least one of the source lines CSl to CSn by designating the internal address signal ax supplied to the control circuit CONT. V _PP is supplied. Therefore, in a plurality of memory elements coupled to a source line (e.g., CSl) designated by the address signal ax, a high electric field is directed from the control gate to the source, and electrons accumulated in a floating gate such as the memory element Ql are tunneled. The data erasing operation is performed by drawing out to the source line by the phenomenon.

In the erase mode described above, if the MOSFETs Q18 and Q20 are turned ON and the ground potential is applied to the source lines CS1 to CSn, the high electric field as described above does not work, and thus the tunneling phenomenon as described above does not occur. Therefore, of the divided memory blocks of the memory array M-ARY, the high voltage V _PP is applied to the source line designated by the internal address signal ax, so that only the memory element to which it is coupled is partially erased.

2 is a circuit diagram of another embodiment of the present invention.

In this embodiment, the source lines of the memory array M-ARY are common in the same EEPROM as described above, and the erase voltage V _PP or the ground potential V _SS for write / lead are collectively provided by the P-channel MOSFET Q17 and the N-channel MOSFET Q18. do. That is, when the erasing mode is instructed, the erasing mode instruction signal erc is output from the control circuit CONT, and the erasing control circuit ERC causes the P-channel MOSFET Q17 to be turned ON when the erasing mode is instructed by the signal erc. It is set as high voltage _VPP .

In modes other than the erase mode, the erase control circuit ERC turns on the N-channel MOSFET Q18 and sets each source line CS to the ground potential of the circuit.

At this time, in order to realize partial erasing of the memory array M-ARY, the X decoder circuit XDCR sets the word line to a high voltage V _PP or a ground potential V _SS of a circuit higher than the power supply voltage V _CC . That is, as in the write operation, the X decoder circuit XDCR sets one word line indicated by the address signal AX as the selection level of the high voltage V _PP , and all other word lines are unselected such as the ground potential V _SS of the circuit. Unlike the operation of leveling, for example, several word lines corresponding to the memory block to be erased are partially set to the non-selection level (V _SS ), and other word lines are set to the high voltage V _PP .

That is, the X decoder circuit XDCR supplies the unselected level V _SS to a plurality of word lines included in the memory block to be erased, and supplies a high voltage V _PP to other word lines. In this configuration, the above high electric field is applied to several memory elements coupled to the word lines of the non-selection level, and the erase operation by the tunnel phenomenon is executed. On the other hand, in a plurality of memory elements coupled to a word line of high voltage V _PP , the control gate and the source are coincident and the high field as described above is not applied, so that the erase operation using the tunnel phenomenon is not performed.

When erasing as in the above embodiment, the data line of the block is connected to the erasing control circuit EDT through the floating state or through the column switches MOSFETs Q7 to Q9 and the selection gate (MOSFET Q33). The erase control circuit EDT is used to monitor the current flowing through the memory cell in which the erase operation is executed and to control the erase amount. That is, the erase control circuit EDT is used to prevent the memory cells from being erased excessively. In the case of erasing the data line in a floating state, the erase amount is set by a predetermined erase time. When the erase operation is performed with the data line in the floating state as described above, the select gate MOSFET Q33 and the erase control circuit EDT are deleted.

3 shows a circuit diagram of one embodiment of the X decoder circuit XDCR.

The memory array M-ARY is composed of n divided memory blocks MBl to MBn as shown by the dotted lines.

One of the corresponding NOR gate circuits G2, G3 is supplied to the input terminal of the output signal of the decoder circuit UDCR in the unit forming the selection signal for the word lines W1, W2, etc. included in the memory block MBl. The address signals al are commonly supplied to the other input terminals of these NOR gate circuits G2 and G3 via the AND gate circuit G1 receiving the erasing control signal er. That is, the output signal of the AND gate circuit G1 becomes a common control signal such as the NOR gate circuits G2 and G3 provided on the output side of the decoder circuit in the unit corresponding to the memory block MBl.

The output signals of the NOR gate circuits G2 and G3 are supplied to the corresponding word lines W1, W2 and the like through the inverter circuits N1 and N2 through the level conversion circuits LVC1 and LVC2. The level converting circuit LVC1 is composed of the following circuit elements as shown in the concrete circuit thereof. The output signal of the inverter circuit N1 is supplied to the gate of the P-channel MOSFET Q41 through the cut MOSFET Q40 in which the power supply voltage V _CC is normally supplied to the gate. The gate of the N-channel MOSFET Q42 is not particularly limited, but the output of the inverter circuit N1 is directly supplied.

Instead of this configuration, the gate of the N-channel MOSFET Q42 may be connected to the gate of the P-channel MOSFET Q41. The P-channel MOSFET Q43 is provided between the gate of the P-channel MOSFET Q41 and the node V _CC / V _{PP to} which the high voltage V _PP is supplied. The other level conversion circuit LVC2 or the like is also constituted by the same circuit as above.

In this embodiment, when the erasing mode is instructed, the erasing mode signal er of a high level (V _CC : logic 1) is output from the control circuit CONT. As a result, the AND gate G1 opens the gate, and the address signals al to an (not particularly limited, but the internal address signal of the X system) are made valid, and the respective NOR gate circuits G2 and G3 are replaced instead of the decode output of each unit circuit UDCR. It is transmitted to the level conversion circuit. For example, if the address signal al is at the high level, the output signals of the NOR gate circuits G2 and G2 are at the low level, and the word lines W1, W2, etc. of the memory block MBl are not selected at the low level (V _SS ). As a result, the memory cells in the memory block MBl are erased. At this time, in the level conversion circuit LVC1 and the like, the N-channel MOSFET Q42 is turned ON due to the high level of the output signal of the inverter circuit N1, and the word line W1 is set to the low level ground potential. According to the low level of the word line W1, the P-channel MOSFET Q43 is turned on to make the gate voltage of the P-channel MOSFET Q41 high voltage V _PP . As a result, the P-channel MOSFET Q41 is turned off. As the gate voltage of the MOSFET Q41 becomes V _PP , the N-channel MOSFET Q40 is turned off, and it is possible to prevent the direct current from flowing from the high voltage V _PP toward the operating voltage V _CC of the inverter circuit N1.

When the address signal al becomes low, the output signals of the NOR gate circuits G2 and G3 become high level, and the word lines W1 and W2 of the memory block MBl become high level such as V _PP . That is, the P-channel MOSFET Q41 is turned ON by the low level of the output signal of the inverter circuit N1 by the level conversion circuit LVC1 and the like, and the word line W1 is set to the high level of the high voltage V _PP . At this time, the N-channel MOSFET Q42 is turned off. The same applies to the address signals a2 to an corresponding one-to-one corresponding to other memory blocks MBn and the like.

That is, since each address signal of n bits for each decoder circuit divided in correspondence to the n-divided memory blocks MBl to nBn is output instead of the output of each of the n-decoded decoded sections, each address signal whose n-level word line level is n bits. Can be specified in a one-to-one correspondence. In this configuration, as described above, the erasing operation of various memory blocks including batch erasing is enabled.

When the signal er becomes low level when the operation mode is not in the erase operation mode, the respective NOR gate circuits G2 and G3 operate as different inverter circuits and transmit the output signal of the decoder circuit UDCR in the corresponding unit. Although not shown in the same drawing, the complementary address signal is supplied from the address buffer to the decoder circuit UDCR in each unit, and the selection signal corresponding to the address signal AX is formed in the read operation mode or the like. Although not particularly limited, the signal er is supplied to the decoder circuit UDCR in each unit, and a low level output signal is formed in response to the signal er becoming high.

The NOR gate circuits G2 and G3 can also be used when the entire word line is non-selective in the embodiment of FIG.

Further, the X decoder circuit XDCR may designate a word line to be made non-selection level such as ground potential V _SS by validating only n bits, such as the upper two or three bits of the address signal, by the signal er. In this case, the word lines of the memory array M-ARY are divided into four, so that alternative erasing of the memory block divided into 1 / 2N such as 1/4 or 1/8 is possible.

As described above, a circuit for dividing the word lines of the memory array M-ARY into several and selectively setting the high voltage V _PP / ground potential can take various embodiments. When the memory block is designated one-to-one with the address signal, if the number of bits of the X address signal is insufficient compared with the number of memory blocks, the Y address signal may be used. This also applies to the case where the source line of FIG. 1 is specified. Alternatively, the Y address signal may be used instead of the X address signal. Further, the power supply voltage V _CC is supplied to the node V _CC / V _PP of the level conversion circuit in the control circuit CONT when the high voltage V _PP is in the read mode and the verify mode in the erase mode and the write mode.

6 shows a circuit diagram of one embodiment of a source line selection circuit. This source line selection circuit corresponds to the erase control circuits ERCl to ERCn in FIG. 1, and corresponds to the erase control circuit ERC in FIG. 2. However, these source line selection circuits are not these erase control circuits.

As described above in the erase mode, the internal signal er is always at the high level, and the block selection signal bsn is at the high level for the block to be selected. This block selection signal is formed by one-to-one correspondence with an address signal input via an external terminal in the erasing operation mode as described above, or by decoding an input signal of several bits input by an appropriate decoder circuit. . As a result, the output signal of the NAND gate circuit G4 becomes low level, and a high level output signal is formed through the inverter circuit N4. Thus, the MOSFET Q42 is turned ON and receives the output signal rp of the ramp ratio setting circuit described below. In response to the MOSFET Q43 gradually turning ON, the potential of the node V1 gradually decreases. In response to the drop in the potential of the node V1, the P-channel MOSFET Q44 of the source follower output is gradually turned ON. As a result, the source line CSn is supplied with the high voltage V _PP that changes in response to the potential change of the node V1. At this time, the MOSFET Q41 receives the signal obtained by passing the block selection signal bsn through the NAND gate circuit G4, the inverter circuits N3, and N5 through the gate and is turned off.

There is a possibility that a through current flows between the P-channel MOSFET Q44 and the driving MOSFET Q45 at the end of the erase operation or when switching of the block to be erased. In order to prevent this, delay circuits including inverter circuits N3 and N5 and capacitors C5 and C6 are provided so that the timing at which the driving MOSFET Q45 turns ON has a delay of about 10 ns compared to the gate circuit G4 output change. Similarly, in the reverse operation, a through current may flow, but in this case, there is no problem because a sufficient delay due to the ramp ratio setting circuit exists at the timing when the MOSFET Q43 is turned on. The MOSFETs Q44 and Q45 correspond to the MOSFETs Q17 and Q18, Q19 and Q20 in FIG. It is to be understood that the signals erl to ern in FIG. 1 correspond to the combination of the signal er and block selection signal bsn in FIG.

In addition, when the ramp ratio setting circuit described next in FIG. 1 is not provided, the MOSFET Q43 becomes unnecessary, and the ground potential V _SS of the circuit is supplied to the MOSFET Q42.

In FIG. 2, an inverter circuit for inverting the signal er may be provided instead of the gate circuit G4. What is necessary is just to be similar to the above-mentioned, when not providing a ramp ratio setting circuit.

4 shows a circuit diagram of one embodiment of a ramp voltage generation circuit for generating a high voltage for erasing supplied to the source line.

In the case where the erase operation is performed by supplying a high voltage to the source of the memory cell, in the configuration in which the high voltage V _PP supplied from the outside to the source line is directly supplied by the switch MOSFET, the potential of the source line becomes high voltage V _PP at the same time as the erase operation starts. It is raised to a high voltage such as (about 12V). At this time, since electrons are accumulated in the floating gate of the memory element to be erased, the floating gate has a negative potential equal to or lower than the ground potential V _SS . For this reason, the following high electric field is applied between the floating gate and the source, and there is a concern that the insulating film between the floating gate and the source may be degraded or destroyed, for example, reliability such as deterioration of the retention characteristics of the memory element. There is a problem in that.

In this embodiment, the control signals supplied to the gates of the switch MOSFETs Q17 (Q19) and the like which perform the erase operation in the embodiments of FIGS. 1 and 2 are formed by the following circuit.

The P-channel MOSFETs Q22, Q24 and Q26 and the N-channel MOSFETs Q23, Q25 and Q27 each constitute a CMOS inverter circuit, and are not particularly limited, but the output signals of the CMOS inverter circuits Q22 and Q23 become resistors R1 and capacitors C1. The delay circuit is supplied to the gates of the CMOS inverter circuits Q24 and Q25. The output signals of the CMOS inverter circuits Q24 and Q25 are supplied to the gates of the CMOS inverter circuits Q26 and Q27 through a delay circuit which becomes the resistor R2 and the capacitor C2.

가 공급된다.The output signals of the CMOS inverter circuits Q26 and Q27 are fed back to the input terminals of the CMOS inverter circuits Q22 and Q23 to form a ring oscillator OSC. In this embodiment, the operating voltage supplied to the sources of the P channel MOSFETs Q22, Q24 and Q26 of the CMOS inverter circuit is supplied via the P channel type power switch MOSFET Q32 in order to achieve low power consumption. A reset N-channel MOSFET Q21 is provided between the inputs of the CMOS inverter circuits Q22 and Q23 and the ground potential V _SS of the circuit. The power switch MOSFET Q32 and the reset N-channel MOSFET Q21 are provided. The gate of the power switch MOSFET Q32 and the reset MOSFET Q21 has a phase inverted signal with respect to the erase signal er formed as described above.

Is supplied.

로써 출력된다.The output signal of the ring oscillator OSC is periodically complementary pulse CK, through a parallel CMOS inverter circuit composed of P-channel MOSFETs Q28, Q30 and N-channel MOSFETs Q29, Q31, respectively.

Is output.

는 상기 캐패시터 C3에 차지업된 전하를 캐패시터 C4에 전달하는 전송게이트 MOSFET Q34 의 게이트에 전달된다. 상기 캐패시터 C4의 용량값은 캐패시터 C3의 용량값에 비해서 충분히 큰 용량값을 갖도록 설정된다.The pulse CK is delivered to the gate of the transfer gate MOSFET Q33, which transfers the supply voltage V _CC to capacitor C3. pulse

Is transferred to the gate of the transfer gate MOSFET Q34, which transfers the charge charged up in the capacitor C3 to the capacitor C4. The capacitance value of the capacitor C4 is set to have a sufficiently large capacitance value compared to the capacitance value of the capacitor C3.

를 받는 리세트용 MOSFET Q37 이 병렬로 마련된다.Capacitor C4 has the signal

Reset MOSFET Q37 is provided in parallel.

The sustain voltage V1 of the capacitor C4 is transferred to the gate of the N-channel MOSFET Q36 to which the ground potential V _SS is applied to its source. The P-channel MOSFET Q35 is connected between the drain of the MOSFET Q36 and the high voltage V _PP . The P-channel MOSFET Q35 acts as a resistor by applying the ground potential V _SS of the circuit to its gate normally. Then, the divided voltages V2 of the MOSFETs Q35 and Q36 become the drive voltages supplied to the gates of the MOSFETs Q17 and the like which apply the erase voltage to the source line CS as described above. Although omitted in the same drawing, as shown in FIGS. 1 and 2, a MOSFET Q18 that provides a ground potential to the source line CS is provided in series with the MOSFET Q17. This MOSFET Q18, etc., is turned ON when the control signal is supplied and is other than the erasing operation of the memory array M-ARY to which the source line belongs, and supplies the ground potential V _SS .

As a result, the above write operation, read operation, and the like are performed.

Next, the operation of the circuit of this embodiment will be described with reference to the operation waveform diagrams shown in FIGS. 5A to 5F.

가 로우레벨로 되면, N 채널 MOSFET Q21 이 ON 상태로, 파워 스위치 MOSFET Q32가 ON 상태로 되므로, 링발진기가 발진동작을 개시해서 펄스 CK,

가 교대로 하이레벨/로우레벨로 변화한다. 펄스 CK가 하이레벨일때, 전송게이트 MOSFET Q33이 ON 상태로 되고, 캐패시터 C3이 전원전압 V_CC-V_th(V_th는 MOSFET Q33의 임계값 전압)로 차지업 된다. 펄스신호

가 하이레벨로 되면, 전송 게이트 MOSFET Q33 대신에 MOSFET Q34 가 ON 상태로 되기 때문에 캐패시터 C3과 캐패시터 C4에 의해 전하분산이 이루어진다. 캐패시터 C4 는 상기 신호

가 하이레벨일 때에 ON상태로 되는 MOSFET Q37에 의해서 디스차지 되어 있으므로, 상기 전하분산에 의해 전해진 전하에 따른 전위 V1을 갖게 된다. 상기 펄스 CK,

가 반복해서 발생되므로, 상기 전하분산에 의해 캐패시터 C4의 전위 V1이 계단파 상태로 서서히 높아진다. 이 전앞 V1의 전위상승에 따라서 MOSFET Q36 의 콘덕턴스가 서서히 크게 된다. 그 때문에 MOSFET Q35와 Q36과의 사이의 콘덕턴스비에 의해 결정되는 드레인 출력 V₂는 고전압 V_PP에서 접지전위를 향해서 서서히 저하한다. 이와 같은 전압 V2의 저하에 따라서 MOSFET Q17의 콘덕턴스도 서서히 크게 되기 때문에, 동일도면에 실선으로 표시한 바와 같이 소스선 CS에 공급되는 소거전압은 계단파 형상의 전압 V1에 대응한 램프비율 특성을 갖고 높게 된다. 또한, 점선으로 표시한 전압 CS'는 상술한 바와 같이 스위치 MOSFET 를 통해서 고전압 V_PP를 소스선에 공급한 경우의 소스선의 전압을 도시하고 있다.The signal

Becomes low level, the N-channel MOSFET Q21 is turned ON and the power switch MOSFET Q32 is turned ON, so that the ring oscillator starts oscillation operation, and the pulse CK,

Alternately changes to high level / low level. When the pulse CK is at the high level, the transfer gate MOSFET Q33 is turned ON, and the capacitor C3 is charged up to the power supply voltage V _CC -V _th (V _th is the threshold voltage of the MOSFET Q33). Pulse signal

Becomes high level, charge transfer is caused by capacitor C3 and capacitor C4 because MOSFET Q34 is turned ON instead of transfer gate MOSFET Q33. Capacitor C4 is the signal

Is discharged by the MOSFET Q37, which is turned ON when is at the high level, and therefore has a potential V1 corresponding to the electric charges transferred by the charge dispersion. The pulse CK,

Since is repeatedly generated, the electric potential V1 of the capacitor C4 gradually rises in a stepped wave state by the charge dispersion. The conductance of the MOSFET Q36 gradually increases with this potential rise of the front V1. Therefore, the drain output V ₂ determined by the conductance ratio between the MOSFETs Q35 and Q36 gradually decreases toward the ground potential at the high voltage V _PP . Since the conductance of the MOSFET Q17 also gradually increases as the voltage V2 decreases, the erase voltage supplied to the source line CS has a ramp ratio characteristic corresponding to the stepped voltage V1, as indicated by the solid line in the same drawing. It gets high. In addition, the voltage CS 'indicated by the dotted line shows the voltage of the source line when the high voltage V _PP is supplied to the source line through the switch MOSFET as described above.

Withdrawal of charge starts when the floating gate and the source of the memory element erased by the supply of the erase voltage having such a ramp ratio become a high voltage necessary for tunneling. Therefore, when the potential of the source finally reaches the high electric potential V _PP , since a certain amount of charge has already been taken out of the charges stored in the floating gate, the voltage S-FG acting between the floating gate and the source is the same. The voltage S-FG '(the voltage used between the floating gate and the source) when the potential of the source line indicated by the dotted line on the same drawing increases sharply as shown by the solid line on the same figure. Excessive high electric field can be prevented from occurring. As a result, the degradation or destruction of the insulating film between the floating gate and the source, which is different from the erasing operation, can be prevented, and the high reliability of the device can be ensured.

In addition, in the embodiment of FIG. 6, the voltage V1 shown in FIG. 4 is used as the signal rp shown in FIG.

The working effect obtained in the above Example is as follows. In other words,

(1) For a memory array in which a nonvolatile semiconductor memory device having a control gate and a floating gate is arranged in a matrix form, the source line is divided into a plurality of blocks, and the entire word line is not selected and is selected for each block. By supplying the high voltage for erasing, the effect of erasing for each block becomes possible.

(2) For a memory array arranged in a nonvolatile semiconductor memory fabrication matrix having a control gate and a floating gate, the word lines are divided into blocks, and each block is provided with an erase voltage supplied to a source line of the memory array. The effect of enabling the erase operation for each block is obtained by setting each word line to the ground potential level.

(3) By forming a signal corresponding to the address signal as one-to-one as a control signal for erasing for each block, the effect of erasing by combination of various blocks including batch erasing is obtained.

(4) Charges due to the tunnel phenomenon until the source voltage reaches the high voltage V _PP by having a ramp ratio that gradually raises the potential of the source line to which the source of the nonvolatile semiconductor memory device to be erased is coupled from a low voltage to a high voltage. Since withdrawal is performed, an excessive strong electric field can be prevented from being applied between the floating gate and the source. Thereby, the effect that the high reliability of an element can be prevented is acquired.

와 전원전압 V_CC를 받는 다이오드 형태의 MOSFET Q51~Q66, 캐패시터 C11~C18로 되는 차지펌프 회로를 사용하여 상기 전원전압 V_CC를 승압해서 형성하는 것이어도 좋다. 이 구성에서도 제어신호

에 의해 소거동작시에 승압회로의 동작을 개시시키는 구성으로 하는 것에 의해서 차지펌프 작용에 의한 승압 동작을 이용해서 소스선 CS에 공급되는 소거전압을 램프 비율을 갖고 상승시킬 수가 있다. 출력 MOSFET Q67 의 게이트에는 블럭소거신호

가 공급된다. 이것에 의해 상기 실시예와 같이 블럭마다 선택적인 소거동작을 가능하게 하고 있다. 일괄소거를 하는 경우에는 신호

대신에 소거신호

를 사용할 수 있다. 이 소거제어신호

는 외부단자에서 공급되는 것이외에 상기와 같이 다른 제어신호와의 조합에 의해 형성하는 것이어도 좋다. 또한, 동일 도면에서는 생략되어 있지만, 소스선 CS에 접지전위를 부여하는 MOSFET 가 상기 MOSFET Q67에 대해서 직렬로 마련된다. 이 MOSFET 는 적당한 제어신호가 공급되는 것에 의해서 해당 소스선이 속하는 메모리 어레이 M-ARY내지 메모리 블럭의 소거동작 이외일 때에 ON 상태로 되어 소스선 CS에 접지전위 V_SS를 공급한다.As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example, Of course, can be variously changed in the range which does not deviate from the summary. For example, the memory block to be erased by the combination of the source line and the word line may be specified. As the memory element, in addition to the MOS transistor of the stack structure used for the EPROM, a FLOTOX type nonvolatile memory element that uses tunneling may be used for write operation. The high voltage V _PP for write / erase includes a timing pulse CP formed by the power supply voltage V _CC and the oscillator OSC having the same configuration as the circuit shown in FIG. 4, as shown in FIG.

And the power supply voltage using the charge pump circuit is in the V _CC of the diode-receiving MOSFET Q51 ~ Q66, capacitors C11 ~ C18 or may be formed by the step-up the power supply voltage V _CC. Control signal even in this configuration

In this way, the operation of the booster circuit can be started during the erase operation. Thus, the erase voltage supplied to the source line CS can be raised with the ramp ratio by using the boost operation by the charge pump action. The block erase signal is provided at the gate of the output MOSFET Q67.

Is supplied. This enables selective erasing operation for each block as in the above embodiment. Signal when bulk erasing

A cancellation signal instead

Can be used. 2 erasing control signal

In addition to being supplied from an external terminal, may be formed by a combination with other control signals as described above. In addition, although omitted in the same drawing, a MOSFET that provides a ground potential to the source line CS is provided in series with the MOSFET Q67. This MOSFET is turned on when the control signal is supplied and is in an ON state other than the erase operation of the memory array M-ARY to the memory block to which the source line belongs, and supplies the ground potential V _SS to the source line CS.

The external control signal supplied to the storage device can take various embodiments. In addition to using the circuit by charge dispersing, a circuit having a ramp ratio at a high voltage supplied to a source of a memory element to be erased as described above is integrated with a capacitor and a resistor, and an integrated circuit and a counter using an operational amplifier circuit. Various embodiments, such as a circuit and a D / A conversion circuit which receives the number output, can be taken. The EEPROM which is erased at a high voltage having a ramp ratio in this manner may be a buried EEPROM having only the batch erasing mode as described above.

The specific circuit configuration of the memory array constituting the EEPROM and its peripheral circuits can take various embodiments. The EEPROM may be embedded in a digital semiconductor integrated circuit device such as a microcomputer.

INDUSTRIAL APPLICABILITY The present invention can be widely used for a nonvolatile memory device having a stack gate structure and a FLOTOX type memory device for use in an EPROM.

The effect obtained by the representative of the invention disclosed in this application is briefly described as follows. That is, by selectively applying a high voltage between the word line to which the control gate of the nonvolatile semiconductor memory device is coupled and the source line to which the source of the nonvolatile memory device is coupled, the charge accumulated in the floating gate is drawn out to the source line. Partial erasure is possible. In addition, an excessive strong electric field is applied between the floating gate and the source by making the ramp rate characteristic of gradually rising from a low voltage to a high voltage at a potential supplied to a source line to which a source of a nonvolatile semiconductor memory element to be erased is coupled. Can be prevented.

Claims (8)

A nonvolatile semiconductor memory device formed in one semiconductor, comprising: a plurality of word lines, a plurality of data lines, a plurality of common lines, a first region in which each is coupled to one data line of the plurality of data lines, and the plurality of common lines A second region coupled to one common line in a line, a control gate coupled to one word line among the plurality of word lines, and a plurality of memory cells arranged in a matrix with a floating gate below the control gate, the matrix arranged Indicating means for generating an indication signal indicating a plurality of memory cell rows in a plurality of memory cells and an area which is coupled to the plurality of memory cells and the indicating means and in which the memory cell rows indicated by the indication signal are erased at one time; And erasing control means for performing an erasing operation. Line and the non-volatile semiconductor memory device is larger than the potential difference is a potential difference is not applied between the word line to be supplied between the common lines and the word lines other than the region in the erase operation. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the indicating means instructs the memory cell rows arranged in succession as the plurality of memory cell rows. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said memory cell row comprises one word line and several memory cells coupled to said word line. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the indicating means includes an address buffer which receives data via an address terminal and outputs data as the indicating signal. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell row includes one word line and several memory cells coupled to the word line. 6. The nonvolatile semiconductor memory device according to claim 5, further comprising an address buffer which receives data via an address terminal through the indicating means and outputs data as the indicating signal. 4. The nonvolatile semiconductor memory according to claim 3, wherein the instruction signal generated by the instruction means indicates a plurality of memory cell rows from two memory cell rows to all memory cell rows in the plurality of memory cells arranged in the matrix. Device. 6. The nonvolatile semiconductor memory according to claim 5, wherein the instruction signal generated by the instruction means indicates a plurality of memory cell rows from two memory cell rows to all memory cell rows in the plurality of memory cells arranged in the matrix. Device.

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