KR100379504B1 - Nonvolatile memory device - Google Patents

Abstract

The present invention relates to erasing decoding of a nonvolatile memory device for reducing unnecessary power consumption, comprising: a nonvolatile memory cell array unit in which a plurality of nonvolatile memory cells are arranged in a matrix form; A switching unit to select an erase line of the nonvolatile memory cell; A discharge unit configured to discharge a voltage applied to an erase line of the nonvolatile memory cell; A first driver applied to the switching unit to drive an erase line of the nonvolatile memory cell; A second driver controlling on / off of the switching unit; A third driver for outputting a driving signal to the first and second drivers; A decoder unit for receiving an address and a control signal and outputting an input signal for direct drive control to the first, second, and third driving units and the discharge unit; And a high voltage generator configured to output a high voltage to the first, second, and third driving units.

Description

Nonvolatile Memory Device {NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to erasure decoding of nonvolatile memory devices for reducing unnecessary power consumption.

The nonvolatile memory device according to the related art is related to US Patent 4,437,174 (semiconductor memory device), which will be briefly described with reference to the accompanying drawings referring to a part of the US patent.

1 is a circuit diagram illustrating a nonvolatile memory device according to the related art.

The structure of the nonvolatile memory device according to the related art is shown in FIG. 1 as follows. First, in the memory cells M11, Mi1 and M1j, Mij is a memory matrix, i in the row direction, j in the column direction, respectively. It is numbered and ordered. In each memory cell M11, Mij has a control gate CG, a floating gate FG, an erase gate EG, a drain D, and a source S, and the sources of all the memory cells are grounded.

The drains D of the memory cells numbered i and arranged in the same row are respectively connected to the digit lines DL1 to DLj, and the digit lines DL1 to DLj are connected through the MOS transistor of TC1 to TCj. It is connected to each output line CD1 to CDj of the column decoder COLUMN DECODER 150, respectively.

In addition, the gate of the MOS transistor that is TCj to TCj receives the signal Vpm1.

This signal Vpm1 is placed at a high level when data is read, written, or data erase is detected.

The erase gates EG of the memory cells numbered i in the same row are connected to the erase lines E1 to Ej numbered j, respectively, and the erase lines E1 to Ej are erased through the MOS transistors Te1 to Tej. It is connected to the erase terminal Er to which the voltage Ve is applied. The erase lines E1 to Ej are also grounded through MOS transistors that are Tre1 to Trej, respectively, and the gate of the MOS transistor receives a data erase check signal Vec when data erase is detected. The gate of the transistor Te1 to Tej is connected to the output terminals of the boosters BS1 to BSj, and the boosters BS1 to BSj are respectively grounded through the MOS transistors Tl1 to Tlj and the output line CD1 of the column decoder 150. Raise the voltage of ... CDj).

In addition, line L of column decoder 150 is connected to sense amplifier 154. The sense amplifier 154 detects whether a current flows through one of the selected output lines CD1 to CDj. The output signal from sense amplifier 154 is applied to latch circuit 156 which is resettable and latched.

The output terminal 158 of the latch circuit 156 is connected to the gate of the MOS transistor, which is Tlj to Tlj.

The control gate CG of the memory cell numbered j in the same column is connected to the row lines RL1 to RLi numbered i, respectively, and the row lines RL1 to RLi are connected to the MOS transistors Tr1 to Tri. It is connected to the output terminals RD1 to RDi of the row decoder ROW DECODER 152. The MOS transistor receives a signal Vpm1 at each gate. The row address is input to the row decoder 152. One of the output stages of the row decoder 152 is selected corresponding to the row address when data is read or written. The high level signal is the output from the selected output of the low decoder 152, while the low level signal is the output from all of the non-selected outputs.

The low lines RL1 to RLi are connected to the boosters BC1 to BCi through the MOS transistors of T2 to T21, respectively. The signal Vpm2 is at a low level when data is read or written and is at a high level when data is erased or data erase is detected.

The booster, BC1, consists of a MOS transistor, T11, T12, T13, and T14, and a capacitor, C11. The BC1 booster compensates for the drop at + 40V erase voltage Ve because of the T1 and T2 MOS transistors.

The gate of the T12 transistor receives the signal Vpm2, and one end of the T12 transistor is connected to the erase terminal Er, the gate of the T11 transistor, and one end of the T11 transistor. In addition, the other end of the T12 transistor is connected to one end of the T13 transistor, and the gate of the T13 transistor is connected to the other end of the T11 transistor and one end of the C11 capacitor. The other end of the T13 transistor is connected to the other end of the C11 capacitor and one end of each of the T14 and T21 transistors. The other end of the T14 transistor is grounded and the gate of the T14 transistor is connected to the output terminal RD1 of the row decoder 152. BCi boosters are arranged in the same way as BC1 boosters.

Next, only the erase operation of the nonvolatile memory device having the above structure will be described. The data erase operation is performed in the column direction of the main cell, and the decoding thereof is performed by the column decoder 150. As the signals decoded from the column decoder 150 switch (on / off) the MOS transistors Te1 to Tej through the boosters BS1 to BSj, the erase voltage Ve is transferred from the main cell to the selected column and connected to the selected column. Are supplied to the erase gate EG to perform an erase operation.

The erase operation of the nonvolatile memory device according to the related art will be described in more detail as follows.

When data is erased, the data erase operation and the data erase detection operation are repeated several times alternately. When data erasing is performed, signal Vpm1 is low level, signal Vpm2 is high level, signal Vpm3 is low level, and signal Vec is low level. The erase voltage Ve is placed at + 40V.

For example, if the Mi1 memory cell is selected, the Ti4 MOS transistor of the BCi booster is turned on while the T4 to T (i-1) 4 of each of the other boosters from BC1 to BC (i-1). The transistor is nonconductive. Therefore, since the low level signal is applied through the Ti4 and T2i MOS transistors, only the RLi ROW line is at the low level, and the other low lines RL1 to RL (i-1) are substantially + 30V. Put on.

On the other hand, since the signal Vpm1 is placed at the low level, the MOS transistors from Tc1 to Tcj are turned off, and the outputs from the column decoder 150 are respectively connected to the gates of the MOS transistors from Te1 to Tej through boosters BS1 to BSj. Is approved. If a memory cell of Mi1 is selected, the power source voltage Vcc is only applied to the output line CD1 of the column decoder 150. Thus, the high level voltage is applied to the Te1 MOS transistor through the BS1 booster to turn on the MOS transistor. In addition, the erase voltage Ve of +40 V is only applied to the E1 erase line since Tres MOS transistor is negatively charged at Tre1. Although an erase voltage of +40 V is applied to the erase gate EG of the memory cells M1 through Mi1 in the first column, the data is subject to an increase in the capacitance between the control gate CG and the floating gate FG. Will only be erased from the Mi1 memory cell and not from other memory cells M11 to M (i-1) 1.

As described above, since the control gate CG of the memory cell from M11 to M (i-1) 1 is about + 30V, the potential of the floating gate FG is equal to the electron from M11 to M (i-1). It becomes high so as not to discharge from the floating gate of one memory cell. On the other hand, the potential of the control gate CG of the Mi1 memory cell is at a low level, that is, 0V. Thus, the potential of the floating gate FG of the Mi1 memory cell is set at about 0V even though the capacitance between the control gate CG and the floating gate FG is large. Therefore, the + 40V voltage applied to the E1 erase line is directly erased from the floating gate FG of the Mi1 memory cell in order to efficiently discharge electrons from the floating gate FG of the Mi1 memory cell by field emission. It is applied at one point between the gates EG.

After the data erase operation of the memory cell is performed for the determined period, the data erase detection operation is started.

However, there are the following problems in the conventional nonvolatile memory device as described above.

In order to perform an erase operation in a conventional nonvolatile memory device, a high voltage of 25 V or more is usually generated, and a plurality of switching devices are connected to the voltage to supply a voltage, so that the load in charge of the high voltage generator increases. Unnecessarily, power consumption increases.

When the erase operation is performed by adjusting the column decoder, since the high voltage must bear a huge load, the occupied area of the high voltage generator increases, which is inefficient.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and reduces the power consumption of the internal / external power supply and at the same time reduces the area occupied by the high voltage generator, and controls only the decoder to perform the erase operation. It is an object to provide a memory device.

1 is a circuit diagram of a nonvolatile memory device according to the prior art.

2 is a circuit diagram of a nonvolatile memory device according to the present invention.

3 is a circuit diagram illustrating a first driver of a nonvolatile memory device according to the present invention.

4 is a circuit diagram illustrating a second driver of a nonvolatile memory device according to the present invention.

5 is a circuit diagram illustrating a third driver of a nonvolatile memory device according to the present invention.

Explanation of symbols for the main parts of drawings

21: memory cell array unit 22: switching unit

23: discharge portion 24: first drive portion

25: second drive unit 26: third drive unit

27: decoder 28: high voltage generating unit

31: first level shifter 32: first pumping circuit

41: second level shifter 42: second pumping circuit

51: third level shifter 52: driver

In accordance with an aspect of the present invention, there is provided a nonvolatile memory device including a nonvolatile memory cell array unit in which a plurality of nonvolatile memory cells are arranged in a matrix form, and a switch for selecting an erase line of the nonvolatile memory cell. And a discharge unit for discharging the voltage applied to the erase line of the nonvolatile memory cell, a first driver applied to the switching unit to drive the erase line of the nonvolatile memory cell, and on / off of the switching unit. A second driver for controlling a voltage, a third driver for outputting a driving signal to the first and second drivers, and an address and a control signal to directly drive the first, second, third, and discharge parts. And a high voltage generator configured to output a high voltage to the first, second, and third driving units.

Hereinafter, a nonvolatile memory device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram showing the configuration of a nonvolatile memory device according to the present invention, and FIGS. 3, 4 and 5 are circuit diagrams showing a first driver, a second driver, and a third driver of the nonvolatile memory device.

As shown in FIG. 2, the nonvolatile memory device may include a nonvolatile memory cell array unit 21 for writing, reading, and erasing operations, a switching unit 22 for selecting the nonvolatile memory cell erasing line, and the nonvolatile memory device. After the erase operation of the volatile memory cell is finished, the discharge unit 23 discharging the voltage applied to the erase line, and the first driver 24 for driving the erase line to drive the nonvolatile memory cell erase line through the switching unit 22. ), A second clock driver 25 for controlling the on / off of the switching unit 22, an erase clock driver for driving pumping capacitors of the first driver 24 and the second driver 25. The third driver 26 receives an address and a control signal to generate an input signal of the first, second, and third drivers 24, 25, and 26 and a signal to be applied to the gate of the discharge unit 23. Decoder unit 27, and the first, second, third drive of the respective It consists of a high voltage generating unit 28 for generating a high voltage (VES, VPD, VSGY) for supplying the (24,25,26).

The switching unit 22 and the discharge unit 23 are composed of a plurality of high voltage enMOSs NH00 to NHnm and NHV00 to NHVnm. The high voltage VES generated by the high voltage generator 28 is a memory. The erase line control voltage for controlling the cell erase line, the high voltage (VPD) is a program voltage applied to the cell drain during the erase operation, and the high voltage (VSGY) is for the control of the word line, the voltage for well bias adjustment to be.

First, referring to the switching unit 22, each of the drains D of the plurality of high voltage enMOSs NH0 to NHN constituting the switching unit 22 may have respective output terminals ED_D <0 of the first driving unit 24. > To ED_D <n>, each gate G of the high voltage NMOS (NH00 to NHnm) is connected to each output terminal (EG_G <0> to EG_G <m>) of the second driver 25. The source of the high voltage NMOS (NH00 to NHnm) is connected to the drain of the high voltage NMOS (NHV00 to NHVnm) of the discharge unit 23, and each erase line of the memory cell array unit 21 is connected. EG <00> to EG <nm>).

Next, referring to the discharge unit 23, the plurality of high voltage NMOS (NHV00 to NHVnm) constituting the discharge unit 23 may include a ground terminal and each of the high voltage NMOS (NH00 to NHNnm) of the switching unit 22. Is connected to the source terminal of the high voltage enMOS (NHV00 to NHVnm), and is connected to the output terminal (iXEGPRE <0> to iXEGPRE <m>) of the decoder unit 27 so that the memory cell array unit 21 After the erasing operation, the decoder 27 receives the decoding signals iXEGPRE <0> -iXEGPRE <m> and applies the voltage applied to the erase lines EG <00> -EG <nm> to the high voltage enmos. Through the (NHV00 to NHVnm), it is discharged to the ground terminal.

As illustrated in FIG. 3, the first driver 24 includes a first level shifter 31 to which an output signal XEDPRE <n> of the decoder 27 is input, and the first level shifter 31. A first high voltage NMOS 301 for charging and a second high voltage NMOS 302 for discharge connected in series between a VSGY voltage and a ground terminal, receiving two output signals of each gate input; The first pumping circuit 32 is connected to the source of the high voltage enmos 301 and the drain of the second high voltage enmos 302 in common.

The first level shifter 31 constituting the first driver 24 receives the output signal XEDPRE of the decoder 27 and level shifts the Vcc voltage level signal to the VSGY voltage level. The same signal XEDPRE input from the decoder unit 27 is inverted and applied to the gate of the second high voltage NMOS 302 while being applied to the gate of the first high voltage NMOS 301.

The first pumping circuit 32 includes a third high voltage NMOS 303, a pumping capacitor 304, and a diode 305. The third high voltage NMOS between the VSGY voltage and the ground terminal. The 303 and the pumping capacitor 304 are connected in series, and the diode 305 is connected in the reverse direction between the gate and the source of the third high voltage enmos 303.

In addition, the gate of the third high voltage NMOS 303 is connected in common with the source of the first high voltage NMOS 301 and the drain of the second high voltage NMOS 302 so that the output signal of the first driving unit ( EG_D).

As shown in FIG. 4, the second driver 25 includes a second level shifter 41 to which the output signal XEGPRE <n> of the decoder 27 is input, and the first level shifter 41. And a fourth high voltage NMOS 401 receiving the output signal of the second transistor as a gate input and receiving a VSGY voltage, and a second pumping circuit 42 connected to a source of the fourth high voltage NMOS 401. .

Here, the second pumping circuit 42 has the same configuration as the first pumping circuit 32, but the capacitor 404 inside the second pumping circuit 42 rather than the capacitor 304 inside the first pumping circuit 32. ) Should have a larger capacity.

This is because the output EG_G of the second driver 25 is a gate input of the switching unit 22 for switching the erase gate, so as to transfer a voltage generated in the first driver 24 without a timing loss. This is because it has to be a high voltage quickly.

As illustrated in FIG. 5, the third driver 26 may include the NAND gate 50 and the NAND gate 50 that perform logical operations on the output signal XECLK and the clock signal of the decoder 27. The third level shifter 51 receives the output and the driver 52 receives the output of the third level shifter 51 and outputs output signals ECLK_D and ECLK_G of the third driver.

The driver 52 has the output signal of the third level shifter 51 as a gate input in common between the VPD signal and the ground terminal, and the PMOS 501, the second NMOS 503, and the PMOS connected in series. A first NMOS 502 connected to the drain of the 501 and the drain of the second NMOS 503 to be applied to the first and second drivers 24 and 25 from the drain of the PMOS 501. The output signals ECLK_D and ECLK_G of the three driver 26 are generated.

Here, only one third driving unit 26 may be present, in which case only a control signal is input and the output is supplied to the first driving unit 24 and the second driving unit 25 as a whole.

The erase operation of the nonvolatile memory device according to the present invention configured as described above will be described in detail as follows.

First, the high voltage generator 28 generates VPD (9V), VSGY (10.5V), and VES (15V), which are voltages required for the erase operation, to generate the first, second, and third drivers 24, 25, and 26, respectively. ) Is applied.

The decoder unit 27 generates the decoded signals XEGPRE <0: m>, iXEGPRE <0: m>, and XEDPRE <0: n> for decoding each column of the memory cell array unit. A signal XECLKG <0: m>, XECLKD to be applied to the third driver 26 which generates signals ECLKD <0: n>, ECLKG <0: m> to be supplied to the 24 and the second driver 25. <0: n>).

The third driver 26 receives the VPD voltage from the high voltage generator 28, receives the clock signal and the erased clock decoding signal XECLK, and supplies the erase clock signal (eg, the first driver 24 and the second driver 25) to the first driver 24 and the second driver 25. ECLKD <0: n>, ECLKG <0: m> are optionally supplied.

The second driver 25 receives the VES and VSGY voltages from the high voltage generator 28, receives the decoded signal XEGPRE <0: m> from the decoder 27, and receives the VES and VSGY voltages from the high voltage generator 28. One is selected and the erase clock signal ECLKG <0: m> is supplied from the third driver 26 to be used for pumping.

The decoded signal XEGPRE <0: m> from the decoder unit 27 is input to the second level shifter 41 and shifted from the Vcc level to the VSGY level, and its output is the fourth high voltage enmos ( The node B is charged to (VSGY−Vtnh) by being input to the gate of 401. The voltage charged to the node B is input to the gate of the fifth high voltage enmos 402 to charge the node A to ((VSGY-Vtnh)-2Vtnh).

At this time, if the erase clock signal ECLKG having a VPD voltage of 0 to 9V is supplied to the capacitor 404 in the second pumping circuit 42, the voltage of the node A becomes capacitive coupling. The voltage will increase. Therefore, the increased voltage becomes higher than the built-in potential of the diode 403 inside the second pumping circuit 42 to charge the node B again, and the charged node B is again charged with the fifth high voltage NMOS 402. Is applied to the gate to form positive feedback that causes node A to charge to a higher voltage.

Therefore, as the clocking of the erase clock signal ECLKG continues, the output voltage of the second driver 25 rises above VES to supply a high voltage to the gate of the switching unit 22.

The first driving unit 24 operates almost the same as the second driving unit 25, but the capacitance of the internal capacitor is smaller than that of the capacitor 404 in the second driving unit 25, thereby discharging the second high voltage enmos. Due to 302, the voltage charged in the selected erase gate of the memory cell array unit 21 is quickly discharged to prevent the remaining erase operation from proceeding.

Here, the reason why the capacitor 404 in the second driver 25 is larger is that the output EG_G of the second driver 25 has a plurality of high-voltage engines of the switching unit 22 for switching the erase gate. This is because the gate voltage of the MOS must be a high voltage faster to transfer the voltage generated by the first driver 24 without time loss.

Signals ED_D <0> to ED_D <n> and EG_G <0 applied to the plurality of high voltage NMOSs NHH to NHnm of the switching unit 22 by the first and second drivers 24 and 25. EG_G <m> is selectively supplied to the drain and gate of the high voltage NMOS (NH00 to NHnm) to select the erase line (EG <00> to EG <mn>), and the memory is selected by the selected erase line. An erase operation is performed by charging each erase gate of the cell array unit 21.

On the other hand, when the erasing operation is completed, a plurality of high voltage NMOS (NHV00 to NHVnm) of the discharge unit 23 are selectively selected by the signals iXEGPRE <0> to iXEGPRE <m> supplied from the decoder unit 27. It is turned on to discharge the erase gate.

The nonvolatile memory device according to the present invention may perform a random erase operation, a block erase operation, a chip erase operation, or the like without any other hardware measures according to the operation of the decoder unit 27.

First, in order to perform a random erase operation, the decoder 27 receives an address and a control signal, decodes the first driver 24, the second driver 25, and the third driver 26. Adjust the output.

In order to perform the block erase operation, the output of the decoder unit 27 is selected such that only one of the first driver 24 and the third driver 26 is selected, and both the second driver 25 and the switching unit 22 are selected. Adjust

In addition, in order to perform the chip erase operation, the output of the decoder 27 is adjusted to select all of the first driver 24, the second driver 25, the third driver 26, and the switching unit 22.

As described above, the nonvolatile memory device of the present invention has the following effects.

First, it is possible to reduce the burden of high voltage generated in the high voltage generator by reducing the load to be unnecessarily charged by allowing the driver to be in charge of several switches.

Second, the load to be unnecessarily charged to reduce the leakage loss (leakage loss), and thus the high voltage generator can reduce the pumping rate (pumping rate) can reduce the power consumption.

Third, the area required for high voltage generation can be reduced.

Fourth, since the pumping in the driving unit can supply a voltage higher than the VES to the actual erase gate, the burden on the high voltage of the high voltage generating unit can be reduced.

Fifth, by adding and decoding the erase clock signal to the first and second driving units, the active current drivability of the VPD such as the VPD can be improved and power consumption can be significantly reduced.

Sixth, by adding only a specific control signal to the decoder unit, random acces erase (commonly referred to as sector erase), block erase, chip erase, It can be done without action.

Claims (10)

A nonvolatile memory cell array unit in which a plurality of nonvolatile memory cells are arranged in a matrix form; A switching unit to select an erase line of the nonvolatile memory cell; A discharge unit configured to discharge a voltage applied to an erase line of the nonvolatile memory cell; A first driver applied to the switching unit to drive an erase line of the nonvolatile memory cell; A second driver controlling on / off of the switching unit; A third driver for outputting a driving signal to the first and second drivers; A decoder unit for receiving an address and a control signal and outputting an input signal for direct drive control to the first, second, and third driving units and the discharge unit; And a high voltage generator configured to output a high voltage to the first, second, and third driving units. The switching circuit of claim 1, wherein the switching unit comprises a plurality of high voltage transistors, one end of which is connected to the output of the first driver, a gate of which is connected to the output of the second driver, and the other end of the transistor, Nonvolatile memory device, characterized in that configured to be connected to the discharge unit. The method of claim 1, wherein the discharge unit is composed of a plurality of high-voltage transistors, the transistor is connected between one terminal and the ground terminal of the transistor of the switching unit, the gate of the transistor is configured to be connected to the output terminal of the decoder. Nonvolatile memory device. 2. The display device of claim 1, wherein the first driving unit is connected in series between a first level shifter connected to an output terminal of the decoder, a well bias control voltage VSGY terminal to which the output signal of the first level shifter is applied, and a ground terminal. And a first pumping circuit connected in common with the first and second transistors and one stage of the first and second transistors. The second driving unit of claim 1, wherein the second driving unit is connected to an output terminal of the decoder unit, a third transistor receiving an output signal of the second level shifter, and a second pumping unit connected to one end of the third transistor. Nonvolatile memory device, characterized in that consisting of a circuit. The method of claim 1, wherein the third driver comprises a third level shifter receiving a signal obtained by performing a logic operation on a signal of the decoder and a clock signal, and a driver receiving an output signal of the third level shifter. Nonvolatile Memory Device. The first diode of claim 4, wherein the first pumping circuit comprises: a first capacitor and a fourth transistor connected in series; a first diode connected between one end of a fourth transistor connected in common with the first capacitor and a gate of the fourth transistor; Non-volatile memory device, characterized in that consisting of. 6. The second pumping circuit of claim 5, wherein the second pumping circuit comprises a second diode connected between a second capacitor and a fifth transistor connected in series, and a terminal and a gate of a fifth transistor connected in common with the second capacitor. Nonvolatile memory device. The nonvolatile memory device of claim 7, wherein the capacity of the second capacitor is greater than that of the first capacitor. The semiconductor device of claim 6, wherein the driver comprises: sixth and eighth transistors connected in series between a power supply terminal and a ground terminal of the program voltage VPD, which is commonly applied to the output signal of the third level shifter and is cell drain applied, And a seventh transistor between the sixth transistor and the eighth transistor.