JPH0223597A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To make partial erasure possible and, at the same time, to prevent the decline in reliability of the title device at the time of erasure by performing the erasure by applying a high voltage across a word and source lines and drawing out the electric charges accumulated in the floating gate of a memory cell to the source side. CONSTITUTION:When a P transistor (TR) Q17 for erasure is turned on and N TR Q18 for erasure is turned off through an erasure control circuit ERC 1, a high voltage is applied across a source line CS1 connected with the sources of memory TRs Q1-Q6 of a memory cell array M-ARY selected by word lines W1 and W2 connected with control gates. When the selectively applied high voltage is applied, a high voltage is generated across the word lines W1, W2 and source line CS1, because of the high voltage, electric charges accumulated in the floating gates are drawn out and partial erasure is performed on a selected memory cell TR only.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in an electrically rewritable floating gate type nonvolatile memory device having an element/1 bit configuration.

[Conventional technology]

■For information on how to erase a rewritable floating gate nonvolatile memory device with an element/1-bit configuration, see, for example, Inisni GC 88 Digest of Technical Papers, pp. 132-133 (ISS
CC88Digest of Technical P
As discussed in PP 132-133), similar to EPROM (Erasable & Programmable Read Only Memory), erasing is performed by applying a high voltage to a source line common to all bits.

This high voltage for erasing is directly applied from an external power source.

[Problem to be solved by the invention]

In the above floating gate nonvolatile memory device,
Since the source line is common to all bits, the erasing mode is a single mode of batch erasing, and partial erasing is not possible. In addition, during the erase operation, an external power source is directly applied to the source line, so the potential of the source line rises steeply, resulting in a high electric field between the floating gate of the nonvolatile semiconductor memory element and the source. This may cause deterioration or destruction of the insulating film between the floating gate and the source, which has a serious adverse effect on the reliability of the information retention operation.

An object of the present invention is to provide a nonvolatile semiconductor memory device that allows partial erasure of a memory array.

Another object of the present invention is to provide a nonvolatile semiconductor memory device that prevents reliability from decreasing due to erasing operations.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a high voltage is selectively applied between the word line to which the control gate of the nonvolatile semiconductor memory element is coupled and the source line to which the source of the nonvolatile semiconductor memory element is coupled, and the voltage is accumulated in the floating gate. The accumulated charge is drawn out to the source line side. Further, a ramp rate is provided that gradually increases the potential of the source line to which the source of the nonvolatile semiconductor memory element to be erased is connected from a low voltage to a high voltage.

[Function] According to the above-mentioned means, partial erasing is possible by dividing the source line or word line, and since the high voltage for erasing has a ramp rate, it can be used as a floating gate. It is possible to prevent an excessively strong electric field from acting between the source and the source.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of a memory array section of an EEPROM to which the present invention is applied. Although not particularly limited, each circuit element in the figure may be a known CMO3 (
Complementary MO8) integrated circuit manufacturing techniques are formed on a single semiconductor substrate, such as single crystal silicon.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MO3
The FET has a source region, a drain region formed on the surface of the semiconductor substrate, and a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of electrodes. The P-channel MO3FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

As a result, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MO3FETs formed thereon, and is supplied with the ground potential of the circuit.

The N-type well region has a P-channel M formed thereon.
Configures the substrate gate of the OS FET. The substrate gate of the P-channel MOS FET, ie, the N-type well region, is coupled to the power supply voltage Vcc.

Alternatively, the integrated circuit may be formed on a semiconductor substrate made of single crystal N-type silicon. In this case, the N-channel MO3FET and the non-volatile storage element are formed in the P-type well region, and the P-channel MO3FET is formed on the N-type substrate.

Although not particularly limited, in the EEFROM of this embodiment, a complementary address signal formed through an address buffer receiving X and Y address signals AX and AY supplied from external terminals is supplied to an address decoder DCH. In the figure, an address buffer and an address decoder are shown as the same circuit blocks XADB-DCR and YADB-DCR, respectively. Although not particularly limited, the address buffers XADB and YADB are activated by the internal chip selection signal ce, and are activated by the address signal A from the external terminal.
It takes in X and AY and forms a complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an address signal in opposite phase.

A row (X) address decoder (X)OCR forms a selection signal for the word line W of the memory arrays M-A and RY according to the complementary address signal of the address buffer XADB.

Column (Y) address decoder (Y) DCR forms a select signal for the data line of memory array M-ARY according to the complementary address signal of address buffer YADB.

The memory array M-ARY has a stacked gate structure memory element (non-volatile memory element -MO3FETQI) having a control gate and a floating gate.
~Q6) and '7-1''!Wl.

W2... and data &51D1 to Dn. The above-mentioned memory element is not particularly limited, but E
The structure is similar to that of a FROM memory element. However, as will be described later, the erase operation is performed electrically using a tunnel phenomenon between the floating gate and the source coupled to the source line, unlike conventional EFRO using ultraviolet light.
This is different from the deletion method of M.

In the memory array M-ARY, the control gates of the storage elements Q1 to Q3 (Q4 to Q6) arranged in the same row are connected to the corresponding word line Wl (W2), and the control gates of the storage elements Q1 to Q3 (Q4 to Q6) arranged in the same column are connected to the corresponding word line Wl (W2). , Q4~Q
3. The drain of Q6 is connected to the corresponding data line D1.
~Dn. The sources of the storage elements are coupled to sources IC3I to C3n. That is, in this embodiment, in order to enable partial erasure in one memory array M-ARY, memory elements arranged in a matrix are vertically divided into n blocks, and each block is divided into n blocks as described above. Exemplary source lines C3I and C3n are provided.

The source lines csi to C3n have sources wAcs1 to C3n that are turned on during write/read operations.
N-channel MO3FET1 that provides the circuit ground potential to
8, Q20 and P supplying high voltage vpp for erasing.
Channel MOS FETs Q17 and Q19 are provided. These MO3FETs Q17, Q18, and Q19
, Q20, etc. are switch-controlled by erase control circuits ERCI to ERCn. Erase control circuit ERC1 to ERCn
In the erase mode in which the signals er1 to ern are set to high level in response to the erase signals erl to e'rn as described later, the P-channel MO3FETs QI7 and Q19
etc. are turned on. In other than the erase mode where the above signals erl to ern are at low level, N-channel MO3FETQ
18, Q20, etc. are turned on. Thereby, the erase control circuits ERCI-ERCn selectively apply the high voltage vpp for erase operation and the ground potential for writing/reading etc. to the source lines C81-C3n. Note that when performing a batch erase operation on the entire memory arrays M-A and RY, by setting all the signals erl to ern to high level, the swifter MO3F
ETQ1? , Q19, etc., and supply a high voltage for erasing to the sources of all memory cells.

Although not particularly limited, when erasing, the data line of the block is in a floating state or the selection gate (MO3
It is connected to the erase control circuit through FETQ22).

Although not particularly limited, since writing/continuation is performed in units of 8 bits, the memory array M-ARY is configured to provide a total of 8 sets. In the same figure,
One memory array M-ARY having n-divided memory blocks as described above is exemplarily shown as a representative.

Each data &%D1 to Dn constituting the one memory array M-A, RY is stored in the address decoder DCR.
(Y) is connected to a common data line CD through selection switches MO3FETQ7 to Q9.

A common data line CD is provided corresponding to each memory block. The common data line CD is connected to the output terminal of a write data buffer sofa DIB that receives a write signal input from an external terminal I10 via a switch MO3FETQ21. Similarly, other memory array M-ARY
Also, a column selection circuit switch MO3 similar to the above
A FET is provided, and a selection signal is generated by an address decoder corresponding to the FET.

The common data line CD provided corresponding to the memory array M-ARY constitutes the input stage circuit of the sense amplifier SA via the switch MO3FETQ16, and is coupled to the input terminal of the first stage amplifier circuit PA, which will be described next. .

The common data %i CD exemplarily shown above is the MO3FE turned on by the read control signal sc.
Through the TQI 6, its source is connected to the source of the connected N-channel type amplifying MO3FET QI 1. Between the drain of this amplifying MO8FETQ11 and the power supply voltage terminal Vcc, there is a P-channel type load MO3FETQI2 whose gate is applied with the circuit ground potential.
is provided.

The load MO3FETQI 2 operates to cause a precharge current to flow to the common data vACD for a read operation.

In order to increase the sensitivity of the above amplified MO3FETQI 1,
Common data line C via switch MO3FETQI 6
The voltage of D is the N-channel drive MO3FETQ13.
and a P-channel type load MO3FETQ14, which is an input to the gate of the driving MO3FETQI3.

The output voltage of this inverting amplifier circuit is
Supplied to the gate of QI 1. Further, in order to prevent wasteful current consumption during the non-operation period of the sense amplifier, an N-channel MO3FET QI 5 is provided between the gate of the amplification MO3FET QI 1 and the ground potential point of the circuit. This MO3FETQ15 and the above P channel M
A sense amplifier operation timing signal sc is commonly supplied to the gates of the O3FETQI4.

When reading a memory cell, the sense amplifier operation timing signal sc is set to low level, and the MO3FETQ
I4 is turned on and MO3FETQ15 is turned off. The memory cell has a threshold voltage higher or lower than the selected level of the word line, depending on the write data.

When the memory cell selected by each address decoder X-DCR, Y-DCR is turned off even though the word line is set to the selection level, the common data line CD receives current from MO3FETQ12 and Qll. supply to a relatively high level. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data vACD is set to a relatively low level.

In this case, the high level of the common data 1JcD is limited to a relatively low potential by supplying the relatively low level output voltage formed by the inverting amplifier circuit that receives this high level potential to the gate of MO3FETQI1. Ru. On the other hand, the low level of the common data line CD is limited to a relatively high potential by supplying a relatively high level voltage formed by an inverting amplifier circuit receiving this low level potential to the gate of MO3FET QI1. By restricting the high level and low level of the common data ICD, it is possible to speed up reading even though there is a stray capacitance or the like that limits the signal change speed in the common data line CD. can. That is, when data is read out from a plurality of memory cells one after another, the time required for one level of the common data IcD to change to the other level can be shortened. For such a high-speed read operation, the conductance of the load MO3FET QI 2 is set relatively large.

The MO5FET QI 1 for amplification performs the amplification operation of the gate-grounded source input, and outputs the output signal to the CM
Sense amplifier S configured by OS inverter circuit
Tell A. The output signal of this sense amplifier SA is amplified by the corresponding data output buffer DOB, although not particularly limited, and is sent out from the external terminal I10.

Further, the write signal supplied from the external terminal I10 is transmitted to the common data line CD via the data manual buffer DIB. Also between the common data line corresponding to other memory blocks and the external terminal, a read circuit consisting of an input stage circuit, a sense amplifier, and a data output buffer sofa similar to the above, and a write circuit consisting of a data manual buffer are provided, respectively. .

Although the timing # control circuit C0NT is not particularly limited,
Internal control signals ce, se, etc. are generated according to the chip enable signal, output enable signal, program signal, high voltage for writing/erasing, and internal X address signal ax supplied to external terminals GE, OB, PGM, and Vpp. internal timing signal, erase signal e r l w e r
A read low voltage Vcc/write layer high voltage Vpp, etc. which are selectively supplied to the n and address decoders are formed.

In a state where the high voltage vpp for writing/erasing is supplied, if the chip enable signal CE is at a low level, the output enable signal OE is at a high level, and the program signal PGM is at a low level, the write mode is set,
The internal signal ce is set to high level. A high voltage Vl)9 is supplied to the address decoder circuits XDCR, YDCR and the data input circuit DIB as their operating voltages.

The voltage of the word line to which writing is performed is the above-mentioned high voltage vpp. Then, the data line connected to the storage element into which electrons are to be injected into the floating gate is set to the same high voltage Vpρ as described above. As a result, a channel saturation current flows through the memory element, and in the pinch-off region near the drain coupled to the data line, electrons accelerated by the high electric field are ionized, generating electrons with acquired energy, so-called hot electrons. On the other hand, the floating gate has a voltage determined by the voltage of the control gate connected to the word line, the drain voltage, the capacitance between the substrate and the floating gate, and the capacitance between the floating gate and the control gate, and attracts hot electrons. Make the potential of the floating gate negative.

As a result, even if the potential of the word line connected to the control gate is set to a selected state, the word line becomes non-conductive.

The drain of the memory element in which electrons are not injected is set to a low level so that hot electrons are not generated in the pinch-off region near the drain.

When the chip enable signal GE is at a low level, the output enable signal OE is at a low level, the program signal PGM is at a high level, and vpp is a high voltage for writing, the verify mode is set and the internal signals SC and ce are set at a high level. In this verify mode, each circuit
DCR, YDCR, and DIB are supplied with their operating voltages switched from the high voltage (pp) to the power supply voltage Vcc.

The chip enable signal CE is low level, the output enable signal OE is low level, the program signal PGM is high level, and vpp is the low voltage for reading (Vc
(same level as c), the read mode is set as described above, and the internal signals SC and ce are set to high level.

If the chip enable signal CE is at a low level, the output enable signal OE is at a high level, the program signal PGM is at a high level, and vpp is at a high voltage, the erase mode is set, the internal signal ce is set at a high level, and the signal 3
C is set to low level. Note that the erase mode may be specified by supplying a control signal instructing the erase operation from an external terminal and setting it to a low level.

In this erase mode, the X decoder circuit DCR sets all word lines to a non-select level such as ground potential. At this time, the supplied X address signal is the control circuit C0N.
T is used to specify the memory block to be erased. In this case, the address signal aX is n
Each bit may be in one-to-one correspondence with the n-divided memory blocks. In other words, each bit of the address signal corresponds to the erase signal er1.
~arn in one-to-one correspondence. By adopting such a configuration, it is possible to erase an arbitrary number of memory blocks among the memory blocks divided into n. That is, the signal erl
By combining ~ern, various partial deletions including batch deletion can be realized.

As mentioned above, in the erase mode, all word lines are at a non-select level such as ground potential, and the address signal a
Depending on the designation of The erasing operation is performed by drawing out the electrons to the source line side by a tunneling phenomenon.

When in erase mode as above, MOSFETQ18,
When Q20 is turned on and a ground potential is applied to the source lines C81 to C3n, the high electric field described above does not act, so the tunneling phenomenon described above does not occur.
Among the divided memory blocks of the memory array M-ARY, only those to which the high voltage Vl)9 is applied to the source line are partially erased.

FIG. 2 shows a circuit diagram of another embodiment of the invention.

In this embodiment, in the same EERROM as described above, the source line of the memory array M-ARY is shared, and the P-channel MO3FETQI7 and the N-channel MOSFE
TQI 8 collectively provides an erase voltage vpp or a ground potential for writing/reading. That is, when the erase mode is instructed by the signal arc, the erase control circuit ERC controls the P-channel MO3FETQI7.
is turned on and the source line C8 is set to high voltage vpp all at once.
Otherwise, the N-channel MO3FET QI 8 is turned on and set to the ground potential of the circuit.

In this case, in order to realize partial erasure of the memory array M-ARY, the X decoder circuit DCR partially sets the word line to the high voltage Vpp/or the circuit ground potential. That is, unlike the operation in which the X-decoder circuit DCR sets one word line to a high voltage selection level as in a write operation and sets all remaining word lines to a non-selection level such as the ground potential of the circuit, the X decoder circuit DCR performs an erase operation. The word lines corresponding to the memory blocks in which the process is to be performed are partially set to a non-select level, and the rest are set to a high voltage vpp.

In this configuration, the high electric field as described above acts on the memory element coupled to the word line set to the non-select level,
Erasing operation is performed by tunneling phenomenon. On the other hand, in a memory element coupled to a word line set to a high voltage vpp, the control gate and source are at the same potential,
Since a high electric field as described above is not applied, an erasing operation using the tunneling phenomenon is not performed.

FIG. 3 shows a circuit diagram of an embodiment of the X-decoder circuit DCR.

Memory array M-ARY is composed of n-divided memory blocks MBI to MBn as shown by dotted lines.

An output signal of a unit decoder circuit UDCR that forms selection signals for word lines Wl, W2, etc. of memory block MBI is supplied to one input of a corresponding NOR gate circuit G2.03, etc. The other input of these NOR gate circuits G2.03, etc. is connected to an AND gate circuit G that receives the signal er.
An address signal a1 is commonly supplied via the address signal a1. That is, the output signal of the AND gate circuit G1 is transmitted to the NOR gate circuit G2. It is treated as one signal under common systems such as G3.

The above NOR gate circuit G2. The output signal of G3 is passed through inverter circuits Nl and N2 to level conversion circuit 1. VC1,
It is supplied to the corresponding word lines Wl, W2, etc. via L, VC2. The level conversion circuit LVC1 is composed of the following circuit elements as shown in the concrete circuit.

The output signal of the inverter circuit N1 is the cut MO3FET Q40 whose gate is constantly supplied with the power supply voltage Vcc.
It is supplied to the gate of P-channel MO3FBTQ41 through. Although not particularly limited, the gate of the N-channel MO3FET Q42 is directly supplied with the output of the inverter circuit N1. Instead of this configuration, N channel M
The gate of O3FETQ42 is connected to the above P channel MO3F.
It may be connected to the gate of ETQ41. Gate of the above P-channel MOS FETQ41 and high voltage terminal Vl)
I) is provided with a P-channel MO3FETQ43 that receives the level-converted output signal. Other level conversion circuits LVC2 and the like are also constructed from circuits similar to those described above.

In this embodiment circuit, the signal e instructing the erase mode is
When r is set to high level (logic "1"), AND gate circuit G1 opens the gate and makes address signals a1 to an valid, and outputs each NOR gate circuit Gl, 02, etc. instead of the decoded output of each unit circuit UDCR. is transmitted to the level conversion circuit via. For example, when the address signal a1 is set to a high level, the output signals of the NOR gate circuits Gl and G2 become low level, and the word lines Wl, W2, etc. of the memory block MHI are set to a low non-selection level, and the memory cells of the memory block MBI are erased. state. At this time, the level conversion circuit LVCI etc. is connected to the inverter circuit N1.
Due to the high level of the output signal of
TQ42 is turned on and the word line W1 is brought to a low level ground potential. P-channel MO3FETQ43 is turned on in response to the low level of the word line WlO, and the gate voltage of P-channel MO3FETQ41 is set to high voltage vpp. This allows P-channel MO3FE
TQ41 is turned off. Then, in response to the gate voltage being set to vpp, the N-channel MO3FE
TQ40 is turned off, and direct current can be prevented from flowing from the high voltage V1) toward the operating voltage VCC of the inverter circuit N1.

Furthermore, when the address signal a1 is set to low level, the output signals of NOR gate circuits Gl and G2 become high level,
Word lines W1, W2, etc. of memory block MBI are set to vpp.
A high level such as That is, in the level conversion circuit L V C1 and the like, the P-channel MO3FET Q41 is turned on by the low level of the output signal of the inverter circuit N1, and the word line W1 is set to the high level of the high voltage vpp. At this time, N-channel MO3FETQ42 is turned off. This means that other memory blocks MB
Address signals a2 to an in one-to-one correspondence corresponding to n, etc.
The same applies to

That is, memory blocks MBI to MBn divided into n
In order to output each address signal consisting of n bits in place of the output of each decoder circuit divided into n for each decoder circuit divided into n corresponding to A pair of address signals can be specified in correspondence with each other. This configuration enables various memory block erasing operations including batch erasing as described above.

Since the signal er is at a low level in a mode other than the erase operation mode, each NOR gate circuit Gl, 02, etc. operates as a mere inverter circuit and transmits the output signal of the corresponding unit of decoder circuit UDCR.

The NOR gate circuits G1 and G2 can also be used in the embodiment shown in FIG. 1 when all word lines are to be unselected.

Note that the X decoder circuit OCR may designate a word line to be set to a non-selection level such as a ground potential by validating only N bits, such as the upper 2 or 3 bits of the address signal, using the signal sr. . In this case, the word line of memory array M-ARY is divided into four,
It is possible to selectively erase memory blocks divided into 1/2N, such as 1/4 or 1/8.

In this way, the circuit that divides the word line of the memory array M-ARY into a plurality of parts and selectively sets the word line to the high voltage Vpp/ground potential can take various embodiments.

Note that when specifying a memory block on a one-to-one basis with the address signal, if the number of bits of the X address signal is insufficient compared to the number of memory blocks, the Y address signal may be used. This also applies to the case where the source line in FIG. 1 is specified.

FIG. 6 shows a circuit diagram of one embodiment of the source line selection circuit.

During erasing, the internal signal er is at a high level, and the block selection signal bsn for the selected block is set at a high level. As a result, the output signal of the Nant gate circuit G1 becomes low level, and a high level output signal is formed through the inverter circuit N2.
TQ42 turns on, and the potential of node v1 gradually decreases in response to MO3FETQ43, which receives an output signal rp from a ramp rate setting circuit to be described later, gradually turns on. In response to the drop in the potential of the node V1, the P-channel MO3FET Q44 outputs a source follower.
gradually turns on. As a result, source line C3n
is a high voltage vpp that changes in accordance with the potential of node v1.
is powered. At this time, MO3F receives the signal passed through the Nant gate circuit G1 and the inverter circuits N1 and N2.
ETQ45 is in an off state.

At the end of erasing or when switching blocks, there is a possibility that a through current will flow between the P-channel load MO3FETQ44 and the drive MO3FETQ45.
Inverter circuits N1 and N2 and capacitor C5 delay approximately 1on3 to the timing when TQ45 turns on.
and 06 are provided to prevent this. A through current may similarly flow during the reverse operation, but in this case there is no problem because there is a sufficient delay due to the ramp rate setting circuit at the timing when MO3FET Q3 turns on.

[Embodiment 2] FIG. 4 shows a circuit diagram of an embodiment of a ramp voltage generation circuit that generates a high voltage for erasing to be supplied to the source line.

When performing an erase operation by supplying a high voltage to the source of a memory element as described above, in a configuration in which an external voltage [Vpp is directly supplied to the source line by a switch MO3FET017, etc., the source line is The potential becomes a high voltage such as high voltage Vpp (about 12V). At this time, the floating gate of the memory element to be erased
Since electrons are stored in the floating gate, the floating gate has a negative potential below the ground potential. Therefore, there is a risk that an excessively high electric field will act between the floating gate and the source, degrading or destroying the insulating film between the floating gate and the source, and causing a risk of deterioration of the retention characteristics of the memory element, for example. There is a problem with the tendency.

Therefore, in this embodiment, the control signal supplied to the gate of the switch MO3FET QI 7 (Ql 9), etc., which performs the erase operation as described above, is formed by the following circuit.

P-channel MO3FETs Q22, Q24, and Q26
and N-channel MO3FETs Q23, Q25 and Q27
constitute a CMOS inverter circuit, and although not particularly limited, the CMOS inverter circuits (Q22 and Q2
The output signal of 3) is sent to the CMOS inverter circuit (Q24 and Q
25). The output signal of this CMOS inverter circuit (Q24 and Q25) is supplied to the input of the CMOS inverter circuit (Q26 and Q27) via a delay circuit consisting of a resistor R2 and a capacitor C2. This commercial
The output signal of the OS inverter II path (Q25 and Q27) is fed back to the input of the CMOS inverter circuit (Q22 and Q23), thereby forming a ring oscillator O3C.

In this embodiment, in order to reduce power consumption, the CM
P-channel MO3FETQ2 of OS inverter circuit
2. The operating voltage supplied to the sources of Q24 and Q26 is the P-channel type power switch MO3FET Q32.
Supplied via. In addition, CMOS inverter circuit (
An N-channel MO5FBT Q21 for reset is provided between the inputs of Q22 and 023) and the ground potential point of the circuit. An erase operation signal er is supplied to the gates of the power switch MO3FETQ32 and the reset MO3FETQ21.

The output signal of the ring oscillator O8C is connected to the P-channel MO3FETQ28. Q30 and N channel MO3
FETQ29. The signals are outputted as periodic complementary pulses CK and CK through the cascade-type CMOS inverter circuits each configured from Q31.

Pulse CK is transmitted to the gate of transmission gate MO3FETQ33, which transmits power supply voltage Vcc to capacitor C3. The pulse CK is a transmission gate (MO3) that transmits the charge amplified in the capacitor C3 to the capacitor C4.
It is transmitted to the gate of FETQ34. Above capacitor C
The capacitance value of capacitor C3 is set to be sufficiently larger than that of capacitor C3. Capacitor C4 is a reset MOS FETQ that receives the above signal er.
37 are provided in parallel.

The holding voltage (1) of the capacitor C4 is transmitted to the gate of the N-channel MO3FETQ36 whose source is supplied with the ground potential. Between the drain of this MO3FETQ36 and the high voltage Vl)p, there is a P-channel MO3F
ETQ35 is connected.

The P-channel MO3FET Q35 acts as a resistance element by having the circuit ground potential constantly applied to its gate. And the above MO3FETQ35 and Q
36(7) The divided voltage v2 is connected to the source line C8 as described above.
This is the drive voltage supplied to the gates of MO3FETQ17 and the like, which apply the erase voltage to the .

Next, the operation of this embodiment circuit will be explained with reference to the operational waveform diagram shown in FIG.

When the signal er is set to low level, the N-channel MO3F
ETQ21 is in off state, power switch MO3FET
Since Q32 is turned on, the ring oscillator starts oscillating, and pulses CK and CK alternately change to high level/low level. When the pulse CK is at a high level, the transmission gate MO3FETQ33 is turned on, and the capacitor C3 becomes the it source voltage Vcc −V th (
V th is charged up to the threshold voltage of MO3FETQ33. When the pulse signal CK becomes high level, the MO3F switches to the transmission gate MO8FETQ33.
Since ETQ34 is turned on, charge dispersion (charge shear) is performed between capacitor C3 and capacitor C4. Since the capacitor C4 is discharged by the MO3FET Q37, which is turned on when the signal er is at a high level, it has a potential 1 corresponding to the charge transmitted by the charge dispersion. The above pulse CK,
Since CK is repeatedly generated, the potential (1) of the capacitor C4 gradually increases to a staircase wave state due to the above-mentioned i load fraction. According to the rise in the potential of this voltage Vl, the MO3FET
The conductance of Q36 gradually increases. Therefore,
The drain output (2) determined by the conductance ratio with the MO3FET Q35 gradually decreases from the high voltage (2)p toward the ground potential. Since the conductance of the MO8FET Q17 is gradually increased in accordance with such a decrease in the voltage (2), the erase voltage supplied to the source line C3 is also increased with a ramp rate corresponding to the step-wave voltage v1.

By supplying such an erase voltage, charge extraction starts when the voltage between the floating gate and the source of the memory element to be erased reaches a high voltage necessary for tunneling. Therefore, the potential of the source will eventually reach the high voltage Vl
), a certain amount of the charge accumulated in the floating gate has already been extracted, so that it is possible to prevent an excessively high electric field from being generated between the floating gate and the source. Thereby, it is possible to prevent deterioration or destruction of the insulating film between the floating gate and the source due to the erase operation, and it is possible to guarantee high reliability of the element.

The effects obtained from the above examples are as follows. In other words, (1) For a memory array in which non-volatile semiconductor memory elements each having a control gate and a floating gate are arranged in a matrix, source lines are divided into multiple blocks, and all word lines are divided into blocks. By selectively supplying a high voltage for erasing to each block in a non-selected state, it is possible to achieve the effect that erasing operation can be performed for each block.

(2) For a memory array in which non-volatile semiconductor memory elements each having a control gate and a floating gate are arranged in a matrix, the word line is divided into multiple blocks and an erasing voltage is applied to the source line of the memory array. By setting the word line of each block to the ground potential level in the supplied state, it is possible to achieve the effect of enabling an erase operation for each block.

(3) By forming a signal that corresponds one-to-one with the address signal as the control signal for erasing each block, it is possible to perform erasing operations using various combinations of blocks, including batch erasing. is obtained.

(4) By providing a ramp rate that gradually increases the potential of the source line to which the source of the nonvolatile semiconductor memory element to be erased is connected from a low voltage to a high voltage, the source voltage reaches the high voltage vpp. Since charge has already been extracted by the tunneling phenomenon, it is possible to prevent an excessively strong electric field from being applied between the floating gate and the source. This provides the effect that high reliability of the element can be guaranteed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the source line and the word line may be divided into separate parts, and the memory block to be erased may be designated by the combination.The memory element may be a stacked gate MOS transistor used in an EPROM, or a combination thereof. The write operation may also be performed using a FLOTOX type nonvolatile memory element that uses a tunneling phenomenon.

The high voltage vpp for writing/erasing is connected to the power supply voltage Vcc as shown in FIG.
A timing pulse CP is generated by an oscillation circuit O8C having a configuration similar to that shown in the figure.

MO3 in diode form receiving CP and power supply voltage Vcc
It may be formed by boosting the power supply voltage Vcc using a charge pump circuit consisting of FETs Q51 to Q66 and capacitors C11 to C18.

The external control B signal supplied to the storage device can take various embodiments. The configuration in which the high voltage supplied to the source of the memory element to be erased has a ramp rate as described above uses, in addition to the charge dispersion circuit described above, a time constant circuit consisting of a capacitor and a resistor, and an operational amplifier circuit. Various embodiments can be adopted, such as an integrating circuit using the above, a counter circuit, and a D/A conversion circuit that receives the counted output. The EEFROM in which erasing is performed using a high voltage having a ramp rate may be one that only waits for the batch erasing mode as in the prior art described above.

The specific circuit configuration of the memory array and its peripheral circuits constituting the EEFROM can take various embodiments. Furthermore, the EEPROM or the like may be built into a digital semiconductor integrated circuit device such as a microcomputer.

The present invention can be widely used in nonvolatile memory elements having a stacked gate structure such as those used in EPROMs, and nonvolatile semiconductor memory devices using FL0TOX type memory elements.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a high voltage is selectively applied between the word line to which the control gate of the nonvolatile semiconductor memory element is coupled and the source line to which the source of the nonvolatile semiconductor memory element is coupled, and the voltage is accumulated in the floating gate. Partial erasing becomes possible by drawing out the accumulated charges toward the source line. In addition, by providing a ramp rate that gradually increases the potential of the source line to which the source of the nonvolatile semiconductor memory element that is erased is connected from a low voltage to a high voltage, it is possible to prevent excessive strength between the floating gate and the source. It is possible to prevent an electric field from acting.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the EEPROM according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of the EEPROM according to the present invention, and FIG. 3 is a decoder circuit of the above EEPROM. FIG. 4 is a circuit diagram showing an example of a lamp voltage generation circuit that generates a high voltage for erasing to be supplied to the source line. FIG. 5 is a lamp voltage generation circuit. 6 is a circuit diagram showing one embodiment of the source line selection circuit. FIG. 7 is a circuit diagram showing one embodiment of the built-in high voltage generation circuit. be. XADB, YADB... address buffer, XDCR...
・X address decoder, UDCR... unit circuit, YDC
R...Y address decoder, M-ARY...memory array, PA...first stage amplifier circuit, SA...sense amplifier, D
IB: Data input cover sofa, DOB: Data output cover sofa, C0NT: Timing control circuit, ERC, E
RCI~ERCn=erase control circuit, MB1~MBn...
Memory block, LVCI, LVC2...level conversion circuit, oSC...ring oscillator, G1...Nant gate circuit, N1-N3...inverter circuit

Claims (1)

[Scope of Claims] 1. A word line including a memory array in which non-volatile semiconductor memory elements each having a control gate and a floating gate are arranged in a matrix, and a word line to which the control gates of the non-volatile semiconductor memory elements are coupled; An erase operation mode is provided in which a high voltage is selectively applied between the source of the nonvolatile semiconductor memory element and the source line to which the source is coupled, and the charge accumulated in the floating gate is drawn out to the source line side. A nonvolatile semiconductor memory device characterized by: 2. The nonvolatile device according to claim 1, wherein the source line is divided into a plurality of blocks, and a high voltage for erasing is supplied to each block. Semiconductor storage device. 3. The source line is shared by the memory array and is supplied with a high voltage for erasing, and the word line is divided into multiple blocks and set to the ground potential level for each block. A nonvolatile semiconductor memory device according to claim 1, characterized in that: 4. It includes a memory array in which non-volatile semiconductor memory elements each having a control gate and a floating gate are arranged in a matrix, and the word line to which the control gate of the non-volatile memory element to be erased is connected is set to a ground potential. This erasing method has a ramp rate that gradually increases the potential of the source line to which the source of the semiconductor memory element is connected from a low voltage to a high voltage, thereby drawing out the charge accumulated in the floating gate toward the source line. A nonvolatile semiconductor memory device characterized by having an operation mode. 5. A high voltage with a ramp rate supplied to the source line transfers charge between at least two capacitors having a relatively large capacitance ratio through a switching element controlled by a periodic pulse signal. 5. The nonvolatile semiconductor memory device according to claim 4, wherein the nonvolatile semiconductor memory device is formed based on a control voltage that gradually rises.