KR0148143B1 - The multiple method and apparatus of packet data - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for multiplexing data transmitted over a plurality of channels in data parallelism. In particular, the present invention relates to a method of integrating packets by varying lengths of packets having a variable length consisting of a code and data indicating the beginning of a packet. The present invention relates to a multiplexing apparatus for transmitting in one channel by combining according to the combination order. The apparatus of the present invention includes a storage unit for storing packet data to which a packet start code is added, a detection unit for detecting a packet start code therefrom, and a read signal and a load signal according to whether the detection unit is detected. Each control unit is applied to the control unit, and each time the packet start code is detected, the control unit for generating a switching signal for changing the channel in a predetermined order, and the switch unit for switching the switch to the corresponding channel in accordance with the switching signal of the controller Is achieved. The packet data multiplexing apparatus of the present invention having such configurations provides an effect of enabling multiplexing accurately even when the length of packet data transmitted from multiple channels is variable.

Description

Packet data multiplexer

1 is a block diagram showing an embodiment of a conventional multiplexing device.

2 is a block diagram showing an embodiment of a multiplexing apparatus according to the present invention.

3 is a detailed circuit diagram of the detector of FIG.

4 is a detailed circuit diagram of the controller of FIG.

* Explanation of symbols for main parts of the drawings

10,20: storage 16,26: controller

19,29 switch 30 detection unit

42: decoder 43: adder

44: channel determiner 45: timing signal generator

46: read / load signal generator

The present invention relates to an apparatus for combining signals transmitted from multiple channels and multiplexing them into a single signal. Particularly, the present invention relates to a packet having a variable length consisting of a code and data indicating a start of a packet, and receiving a packet having a variable length through a plurality of channels. The present invention relates to a multiplexing device for reconfiguring to a single channel.

In general, video signals of current high-definition television are processed in parallel due to signal processing speed of hardware. Therefore, multiplexing is required to reconstruct the parallel-processed video signals back to the original video signals.

FIG. 1 is a block diagram showing an embodiment of a conventional multiplexing device. As shown in FIG. 1, the device of FIG. 1 includes a storage unit 10 having four buffers 11, 12, 13, and 14. FIG. ) And an output control signal (O ₁ to O ₄ ) is applied to each buffer of the switch 19 and the storage unit 10 having a switch terminal 18 switchable to one of the output terminals of each buffer. The switch 19 is composed of a controller 16 by applying a switching signal S.

The conventional multiplexer configured as described above stores data of parallel processed video signals in the buffers 11, 12, 13, and 14, respectively. Data stored in each buffer is output through the output terminal of the buffer in accordance with the output control signal (O ₁ ~ O ₄ ) applied from the controller 16. At this time, the length of the output data is the same for each buffer. The controller 16 sequentially applies an output control signal to the respective buffers in a predetermined order to make the data output from the respective buffers into a combination of original data. In addition, the controller 16 applies a switching signal S for connecting the switch terminal 18 to the output terminal of the buffer to which the output control signal is applied, to the switch 19 to switch the data output from the output terminal of the buffer to the switching terminal. Control to be transmitted through a single channel through (18). Data transmitted on a single channel are combined in the order of transmission to form a data stream.

Thus, multiplexing into one data stream can be realized by the output control signals O ₁ to O ₄ and the switching signal S of the controller 16. By the way, in the conventional multiplexing device, although multiplexing of data having a certain length is possible, there is a problem that it is difficult to accurately multiplex data of a packet having a variable length.

Accordingly, an object of the present invention is to provide an apparatus for multiplexing packet data having a variable length using a packet start code indicating a start of a packet in parallel processing of data.

An object of the present invention is a device for multiplexing packet data transmitted through a plurality of channels into a single channel, the packet including a packet start code for indicating the start of the packet having a plurality of buffers connected to each of the plurality of channels Storage means for storing data and transmitting the stored data each time a read signal of the following controller is applied; Whenever the load signal of the following controller is applied, data outputted from the storage means is received and compared with a preset value corresponding to the packet start code, and the first detection indicating that the packet start code is detected if the comparison does not match. A plurality of detectors connected per buffers of the storage means for applying a second detection signal having a different level to the signal to the following controller; A timing signal generator for outputting a predetermined timing signal delayed as much as the detector detects the packet start code to the channel determination unit and the read / load signal generator, and for each timing signal from the timing signal generator; When the first detection signal is applied, the read signal and the load signal are applied to the buffer and the detector corresponding to the current channel. When the second detection signal is applied, the channel is changed based on the channel information from the channel determiner. A read / load signal generator for applying a read signal load signal to a buffer and a detector, and the first channel is maintained when the first detection signal is applied from the detector for each timing signal from the timing signal generator. When a signal is applied, switch the channel switching signal to switch the switch to the corresponding channel according to the preset channel switching sequence. A controller is provided to the channel determination unit for; And a switch unit for connecting any one of the output terminals of the detectors to the signal output side according to the channel switching signal of the controller.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing an embodiment of a multiplexing device according to the present invention, which is a device for multiplexing video data of a high-definition television with various encoding methods and parallel processing. As shown in FIG. 2, the multiplexing apparatus of the present invention includes a storage unit 20 and a controller 26. The storage unit 20 includes buffers 21 to 24 for storing four channels of data to be transmitted. The detector 30 includes detectors 31 to 34 connected to an output terminal of each buffer to receive an output signal of each buffer. Further configured are a switch 29 for selective connection of the output terminals of each detector and a controller 26 for controlling the above configurations. The controller 26 applies the read signals RD ₁ to RD ₄ to read data from each buffer of the storage unit 20, and receives data output from each buffer from each detector of the detector 3. The load signals LD ₁ to LD ₄ for controlling the output are applied.

In addition, the controller 26 generates a switching signal S by using the detection signals PSC ₁ to PSC ₄ applied from each detector of the detector 30 and the system control signals of the system controller (not shown). Have The switching signal S of the controller 26 is connected to be supplied to the switch 29. Description of the detection signals PSC ₁ to PSC ₄ output from each detector will be described later with reference to FIG. 3. The operation of the packet data multiplexing apparatus of the present invention having such configurations will be described in detail.

First, a packet used in the present invention is composed of data having a packet start code (a code indicating a start of a packet) and an integer multiple of a packet start code length, and the length of data constituting each packet is processed in parallel. It is variable by the characteristics of. Further, in the present invention, the unit length of data transmitted at one time is equal to the length of the packet start code, and the packet start code is located at the beginning of the packet data.

The controller 26 applies the read signal RD ₁ to the first buffer 21 of the first channel so as to read out the stored data by the packet start code length. In addition, the controller 26 applies the load signal LD ₁ to the first detector 31 of the first channel so as to receive data having the same length as the packet start code length read out from the first buffer 21. . The first detector 31 detects whether or not data having the same length as the input packet start code length is the packet start code. If the data input to the first detector 31 is not a packet start code, the controller 26 recognizes the above situation from the first detector 31 and applies the switching signal S to the switch 29. The switch terminal 28 is controlled to be connected to the output terminal of the first detector 31, and this data, not the packet start code, is outputted through the switch terminal 28. With the switch terminal 28 connected to the output terminal of the first detector 31, the controller 26 reads the read signal RD ₁ and the load signal to the first buffer 21 and the first detector 31, respectively. (LD ₁ ) is simultaneously applied to read data having the same length as the packet start code length stored in the first buffer 21, and the first detector 31 is input to control whether the packet start code is detected again. At this time, when this data is not the packet start code, it is output through the switch terminal 28 connected to the output terminal of the detector 31 of the first channel. In the state where the switch terminal 28 is connected to the output terminal of the detector 31 of the first channel, all the data contained in one packet are divided into data having the same length as the packet start code length by the same process. It is output through the switch terminal 28 connected to the output terminal of (31). When all data contained in the packet is output through the output terminal of the first detector 31, the first detector 31 receives a new packet and detects a packet start code. When the packet start code for the new packet is detected, the controller 26 receives the detection signal PSC ₁ from the first detector 31 and sends the switch terminal 28 to the output terminal of the second detector 32 of the second channel. The switching signal S controlling to be connected to is applied to the switch 29. With the switch terminal 28 connected to the output terminal of the second detector 32 of the second channel, the packet data transmitted through the second channel is outputted through the switch terminal 28 as in the first channel. Repeat the same process as it is. This process is also performed in the third and fourth channels under the control of the controller 26.

Therefore, the data of each channel output through the switch terminal 28 by the same repeating process are combined in the order in which they are output to form one data stream so that multiplexing is realized.

3 is a detailed circuit diagram of the detector of FIG. The detector of the present invention is composed of four detectors 31 to 34 as shown in FIG. Since these detectors perform the same function, only the operation of one detector will be described in FIG.

In FIG. 3, the detector has three D flip-flops 301, 302 and 303 and one comparator 304 as shown. The load signal LD applied from the controller 26 of FIG. 2 is applied to the first flip flop 301 and the second flip flop 302. The first D flip-flop 301 is operable by applying the load signal LD, so that the data PD having the same length as the packet start code length output from the corresponding buffer is outputted to the signal output terminal 306 and the comparator 304. In this case, the comparator 304 compares the data PD of the packet applied from the first D flip-flop 301 with the preset reference value SV to detect the packet start code. If the same, the high signal is applied to the 3D flip-flop 303, and if the value is different, the low signal is applied, where the high signal indicates that the packet start code has been detected, and the low signal is vice versa. At this time, the 3D flip-flop 303, which is operated by receiving the delayed load signal LD through the 2D flip-flop 302, receives a high signal indicating that a packet start code has been detected or vice versa. Output detection signal (PSC) This detection signal PSC is applied to the controller 26 of FIG.

4 is a detailed circuit diagram of the controller of FIG. As shown in FIG. 4, the controller applies the timing signal CDS from the timing signal generator 45 and the timing signal generator 45 controlled by the system control signals S ₁ to S ₃ . And a channel determination section 44 which receives a packet start code detection signal from a detector and determines a channel. The channel determiner 44 receives a 2-bit signal S output from the channel determiner 44 and selects one output terminal from among the plurality of output terminals D ₁ to D ₄ according to the signal value ( 42) is connected. In addition, the controller uses load signals LD ₁ to LD ₄ by detection signals PSC ₁ to PSC ₄ applied from the detectors 31, 32, 33, and 34 of FIG. 2 and signals applied to the decoder 42. and the read signal (RD ₁ RD ~ ₄₎ and a reading, the load signal generating section 46 to be applied.

First, when a high level first system control signal S ₁ indicating a controller start is applied from a system controller not shown, the second OR gate 451 of the timing signal generator 45 controls the system. The signal S ₁ enables the D flip-flops 452, 453, and 454 to their operational states. In addition, since a lower level is applied to the first OR gate 450, the first D flip-flop 452 outputs a high signal. In addition, since a high signal is also applied to the first and second AND gates 455 and 456, the second and third D flip-flops 453 and 454 respectively output a low signal. After the high level second system control signal S ₂ applied to determine the initial channel is applied, the first OR gate 450 and the first and the first system control signals S ₁ are received. The 2AND gates 455 and 456 output signals of the same level as signals coming into different input terminals, respectively. Here, the D flip-flops 452, 453, and 454 operate by the high level first and second system control signals S ₁ and S ₂ applied from the second OR gate 451, and the D flip-flops 452, 453, and 454 operate. Whenever the second OR gate 451 is operated simultaneously, a high signal is output to only one D flip-flop.

By the way, the second system control signal S2 remains low after the high level when the initial value is set in the channel determination unit 44, and remains in a low state, and is applied to the third system control signal while the packet data is processed. Only S ₃ is applied to the second OR gate 451 in a high state. As shown in the drawing, when a high signal is output from the first D flip-flop 452 of the timing signal generator 45, the timing signal CDS becomes a high level so that the channel determiner 44 and the read / load signal generator Is applied to (46). In addition, the timing signal generator 45 receives the third system control signal S ₃ having a high level applied after the initial value is set by the channel determiner 44 to receive the timing signal CDS. 44) and the read / load signal generator 46. The controller loads data to the detection unit 30 of FIG. 2 until the timing signal generator 45 applying the timing signal CDS applies the next timing signal CDS. Since the time required for detection is needed, the high signal is rotated using the D flip-flops 452, 453, and 454 to delay the time.

Accordingly, the timing signal CDS applied from the timing signal generator 45 is loaded at the time when the data is loaded and the loaded data is detected to be the packet start code. When the signal is applied, a high signal is output from the first flip-flop 452 to become a high level state.

The channel determiner 44 outputs an initial value 0 through the D flip-flop 427 by the second system control signal S ₂ at the high level and the timing signal CDS applied from the timing signal generator 45. do. The zero output signal becomes the switching signal S applied to the switch 29 of FIG. 2 to select the first channel. Of the system control signals S ₁ , S ₂ , and S ₃ applied after the initial value is determined by the channel determination unit 44, only the third system control signal S ₃ is in a high state, and the remaining signals S ₁ , S ₂ ) are all low. In the state where the initial value 0 is set in the channel determiner 44, the decoder 42 receives the 0 signal from the channel determiner 44 and outputs a high signal through the first output terminal D ₁ .

Further, the read / load signal generator 46 and the channel determiner 44 are the low level detection signals PSC ₁ to PSC ₄ applied from the detector 30 in FIG. 2 and the output terminal D of the decoder 42. ₁ through D ₄ ) together with the signal output (all except the first output terminal (D ₁ ) outputs a low signal) is received together.

The channel determiner 44 determines a channel by the signals input to the AND gates 420, 421, 422, and 423, the first and second system control signals S2, S3, and the timing signal CDS. Since the AND gates 421, 422, and 423 connected to the output terminals D ₂ , D ₃ , and D ₄ of the decoder 42 all output a low signal while the initial value is determined, the D flip-flop 427 according to the output value of the AND gate 420. ) Operation is determined. Therefore, if the detection signal PSC ₁ applied to the AND gate 420 is at a low level, the AND gate 420 outputs a low signal. At this time, the AND gate 426 outputs a low signal due to the low signal applied from the OR gate 424, so that the D flip-flop 427 does not operate and the first channel selected initially is maintained as it is.

However, if the detection signal PSC ₁ applied to the AND gate 420 is at a high level, the AND gate 420 outputs a high signal, which is the opposite of the above, and the AND gate 426 outputs a high signal. D flip-flop 427 is operated. Then, the D flip-flop 427 receives and outputs the one signal obtained by adding one to the initial value 0 through the AND gate 425 by the adder 427. One signal is applied to the switch 29 of FIG. 2 to select the second channel, and also to the decoder 42.

On the other hand, the read / load signal generation section 46 is a signal applied from the output terminals D ₁ to D ₄ of the decoder 42 (all except the first output terminal D ₁ outputs a low signal) and a low level. The detection signals PSC ₁ to PSC ₄ are input to apply the read signal and the load signal to the channel determined by the channel determiner 44.

AND in the AND gates 401-408 of the read / load signal generator 46 which receives the signal output through the output terminals D ₁ -D ₂ of the decoder 42 and the detection signals PSC ₁ -PSC ₄ . Only the gate 401 outputs a high signal. Accordingly, the first D flip-flop 411 connected to the AND gate 401 outputs a high signal to generate the first buffer 21 of the first channel 21 and the detector 30 of the first channel of the storage 20 of FIG. The read signal RD ₁ and the load signal LD ₁ are applied to the first detector 31 of one channel, respectively. The first buffer 21 and the first detector 31 of FIG. 2 receiving the read signal RD ₁ and the load signal LD ₁ read and load packet data, and detect whether a packet start code exists. . When the packet start code is not detected and the detection signal PSC ₁ becomes low, the high signal is output from the first D flip-flop 411.

However, when the packet start code is detected by the first detector 31 of the first channel of FIG. 2 and the detection signal PSC ₁ becomes high level, only the AND gate 403 among the AND gates 401 to 408 is high. Output the signal. Accordingly, the 2D flip-flop 412 connected to the AND gate 403 outputs a high signal so that the second buffer 22 of the second channel and the second channel of the second channel of the storage unit 20 of FIG. The read signal RD ₂ and the load signal LD ₂ are applied to the detector 32.

As described above, when the detection signal PSC ₁ is at the low level, the channel determiner 44 applies a signal S to select the first channel as it is, and the read / load signal generator 46 The read signal RD ₁ and the load signal LD ₁ are applied to the first channel.

However, when the detection signal PSC ₁ is at the high level, the channel determination unit 44 outputs a signal S for causing the adder 43 to change the channel from the first channel to the second channel, and then reads and loads. The signal generator 46 applies the read signal RD ₂ and the load signal LD ₂ to the changed second channel. In addition, the decoder 42 receives the value added by the adder 43. Since the controller of the present invention has the same embodiment as described above in the second, third and fourth channels, description thereof will be omitted.

Accordingly, the packet data multiplexing apparatus according to the present invention having the above configurations provides an effect of accurately multiplexing under the control of the controller even if the length of the packet data transmitted from the multiple channels is changed, and the order of selecting the channels under the control of the controller is provided. It provides a different effect.

Claims (1)

An apparatus for multiplexing packet data transmitted through a plurality of channels into a single channel, comprising: storing packet data including a packet start code indicating a start of a packet by having a plurality of buffers connected to each of the plurality of channels; Storage means for transmitting the stored data each time a read signal of the controller is applied; Whenever the load signal of the controller is applied, the data outputted from the storage means is received and compared with a preset value corresponding to the packet start code. A plurality of detectors connected to the buffers of the storage means for applying a first detection signal to a following controller, the second detection signal having a level different from the first detection signal informing that the packet start code has been detected; A timing signal generator for outputting a predetermined timing signal delayed during the time when the detector detects the packet start code to the channel determination unit and the read / load signal generator, and for each timing signal from the timing signal generator; When the first detection signal is applied, the read signal and the load signal are applied to the buffer and the detector corresponding to the current channel. When the second detection signal is applied, the channel is changed based on the channel information from the channel determiner. A read / load signal generator for applying a read signal and a load signal to a buffer and a detector, and a current channel is maintained when the first detection signal is applied from the detector for each timing signal from the timing signal generator, and the second channel is maintained. When the detection signal is applied, it switches the channel switching signal to switch the switch to the corresponding channel according to the preset channel switching sequence. A controller having a channel determining unit for applying teeth; And a switch unit for connecting any one of output terminals of the detectors to a signal output side according to a channel switching signal of the controller.