KR0147761B1 - Bch coding method and apparatus of error correction - Google Patents

Abstract

The present invention relates to a method and apparatus for decoding a double error correction BCH code among error correction codes that allow a receiver to directly correct a bit error occurring on a communication path of a digital communication system data storage system. By dividing the division in the process of obtaining the position polynomial, the area of the circuit is reduced as compared with the conventional decoder.

Description

Decoding method of double error correction BCH code and its device

1 is a block diagram of a general five calculation circuit.

2 is a block diagram of Chien's error detection circuit.

3 is a block diagram showing a decoder of a conventional double error correction BCH code.

4 is a block diagram showing a decoder of a double error correction BCH code according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11,12: error calculation unit 13,23: error detection unit

12: Error position polynomial calculation circuit 22: Error position calculation unit

The present invention relates to a method and apparatus for decoding error correcting codes that allow a receiver to directly correct a bit error occurring on a communication path of a digital communication system or a data storage system. The present invention relates to a method for decoding a double error correction BCH code that reduces the area of a circuit by using no division in the process of obtaining a position polynomial, and a device thereof.

The error correcting code can be divided into Block Codes and Convolution Codes. The BCH (Bose Chaudhuri Hocquenghem) code is a code that can correct a number of random errors. The number of corrections can be selected relatively freely and the number of check bits is relatively small compared to the number of information bits.

Decoding binary block codes finds the number and location of errors within a block. Correction of an error is necessary by inverting the bit at the error position to 1 if 0 and 1 if 0, that is, inverting the bit. The decoding of binary BCH code (hereinafter referred to as BCH) calculates the syntax from the first received sequence, obtains the error locator polynomial from the second error, and obtains the root of the third error location polynomial. The error location number can be divided into three steps: correcting by inverting the bits in the location.

In the prior art, division was necessary in the process of finding an error position polynomial from misdiagnosis. All operations used to decode the BCH code are performed on the finite field GF (2 ^m ), where the most difficult operation is division. The division between any two elements on the finite field GF (2 ^m ) is generally the product of the inverse element of one element by the other element. Thus, dividers include multipliers and inverse calculators.

First, the decoding of the BCH code will be briefly described.

In the (n, k) BCH code whose code length is n and information length is k, the code polynomial is c (χ), the error polynomial is e (χ), and the reception polynomial is r (χ ), R (χ) can be considered as the error polynomial e (χ) generated on the transmission path to the code polynomial c (χ) sent from the transmitter as shown in the following equation.

The code polynomial of the error correction BCH code is the product of the information polynomial d (χ) and the generated polynomial g (χ). Also, when the primitive element of the finite field GF (2 ^m ) is α, the generated polynomial g (χ) is a polynomial based on α, α ³ , α ⁵ , · ^,, α ^2t-1 .

Becomes Therefore, substituting α, α ³ , α ⁵ , ..., α ^2t-1 into Equation ¹ becomes as follows.

Equation 3 shows that if no error occurs in the transmission path, this expression is 0. If an error occurs, this expression is not 0. Therefore, this expression is defined as Syndrome as follows.

That is, if S _j = 0, no error occurs. If S _j ≠ 0, an error occurs. The proof in Equation 4 can be calculated from the received bits.

Receive polynomial r (χ)

Let α ^j (j = 1,3,5, ..., 2t-1) be substituted for

Becomes Looking at Equation 6, α is applied to incoming bits from higher order.^jMultiply by and add it with the next input bit, and then again α^jTo The multiplication process is repeated until the last input is received.

1 is a circuit that calculates the miscalculation using this equation.

After the testimony is obtained, the error position polynomial is obtained from the testimony. Error polynomial e (χ)

If we assume that u (1≤u≥t) errors occur at i ₁ , i ₂ , .... i _u (i ₁ i ₂ .... i _u ), then the error polynomial

Since the proof S _j in Equation 4 is

Becomes Where error position X _k is

Equation 9 is defined as

i = 1

If you solve this for j = 1, 3, 5, ..., 2t-1, you have the following t equations.

The decoding of the BCH code finds the unknowns X ₁ , X ₂ , X ₃ , ..., X _U from these t equations. However, since these equations are nonlinear equations, direct solutions are very difficult. Peterson first proposed a method of solving this nonlinear equation by introducing an error-position polynomial such as (WW Peterson, Encoding and Error correction Procedure for Bose-Chaudhuri codes, IRE Trans. Inf. Theory, IT-6, PP. 459-470, 1960).

First, the error location polynomial is defined as a polynomial having the inverse of the error location as follows.

The relationship between the coefficient σ _i (1 ≦ _i ≦ u) of the error-position polynomial defined by Eq. 13 and the positive S _j is expressed by Eq. 14 by Newton's identity. The process of deriving Eq. 14 is well described in [5.3] (pp.

In equation (14), the determinant | A | is not 0 when t or t-1 errors occur (non or singular), and 0 when t-2 or less occur. do. This property was first demonstrated by Peterson and is described in detail in [9.6] (pp. 300-301) of Error-Correcting Codes (W. W. Peterson and E. J. Weldin, M.I.T Press, Cambridge, Mass, 1972.).

Therefore, by calculating the determinant | A |, we can find the number of actual errors. In addition, the positive S _j is a known constant, and since this equation is a linear equation, σ _i (1 ≦ _i ≦ u) can be obtained relatively easily. Where S _2j = (S _j ) ² . As described above, the error position polynomial σ (χ) can be constructed by obtaining the coefficient σ _i (1 ≦ _i ≦ u) of the error position polynomial from the equation (14).

Determining the coefficient of error position polynomial from miscalculation is the most difficult and complicated process of decoding the BCH code, and the solution is the most important part in the decoding of the BCH code.

Once you have the error location polynomial, the next step is to find the error location. According to the definition of Eq. 13, the error location X _i is the inverse of the root of the error location polynomial σ (χ), so to find the error location, we need to find the root of the error location polynomial σ (χ) and take the inverse. The root of the error-position polynomial σ (χ) is found by substituting all the elements of finite field GF (2 ^m ) for σ (χ), because finite field GF (2 ^m ) has 2 ^m finite elements. Can be. That is, the element whose value becomes 0 by substituting 1, α, α ² , ..., α ^n-1 (n = 2 ^m −1) into σ (χ) is the root of σ (χ).

Speaking root of GF (2 ^m) of any one element ^{α i (0≤i≤n-1, n} = 2 m -1) , an error locator polynomial σ (χ) on, the error location is defined by α ⁱ The inverse α- ⁱ is obtained. Inverse α ^-i of any one of the element α ⁱ on the GF (2 ^m) is so α ⁿ = 1 is as follows.

Therefore, if α ⁱ is the root of the error position polynomial σ (χ), the error position is α ^n-1 . Therefore, if α ⁱ is the root of σ (χ) in the (n, k) BCH code on GF (2 ^m ), then among the received bits (r ₀ , r ₁ , r ₂ , ...., r _n-1 ) r _n-1 bits become error bits.

Chien implemented the above algorithm in a circuit (RT Chien, Cyclic Decoding Procedure for the Bose Chaudhuri Hocquenghem Codes, IEEE Trans. Inform. Theory, IT-10, pp.357-363, 1964). When the received bit is input from a higher order and decoded in order, to decode the r _n-1 bits, it is checked whether α ^n-1 is an error position, and inverts the r _n-1 bits if it is an error position.

To check whether α ^n-1 is the error position is to check whether α, the inverse of α ^n-1 , is the root of the error position polynomial. In other words, it checks whether σ (α) = 0, and if it is 0, inverts the r _n-1 bit or outputs it as it is. In the same way, whether r _n-2 bits is σ (α ² ) = 0, r _n-3 bits are σ (α ² ) = 0, and r ₀ bits are σ (α ⁿ = 1). If it is 0 and it is 0, it reverses the bit at the position or outputs it as it is.

If you represent this process as an equation,

Becomes

As you look at the expression 16 σ (α) = 0 in expression of the α σ _1, wherein the still is multiplied by the α ^{u 2} in the α σ ₂ wherein σ _{u ...} in this section is to examine the value that is zero . In other words,

Becomes

2 is a circuit of the above algorithm. Here, each register contains σ ₁ , σ ₂ , ....., σ _u as initial values.

The double error correction (n, k) error position polynomial of BCH code that can correct all two or less errors is u = 2 in Equation 14.

And determinant | A | = S ₁ . Therefore, if S ₁ = 0, there are no more than t-2 errors, that is, no errors have occurred, and if S ₁ ≠ 0, t or t-1, that is, 2 or 1 errors have occurred. The coefficient of error position polynomial is

The error polynomial becomes

Therefore, σ (α ^I ) = 0 equal to

Becomes

The double error correction BCH encoder is constructed using FIG. 1, FIG. 2, and Equation 20, as shown in FIG.

FIG. 3 is a block diagram showing a conventional decoder for double error correction BCH code. As shown in Equation 21, a circuit 10 for dividing a positive S ₃ by S ₁ is required.

Since S ₁ and S ₃ are elements on GF (2 ^m ), the division between these two elements has a problem that the circuit becomes more complicated as m increases.

`` Atsuhiro Yamaki-shi, Toru Inoue, Toraguchi Murakami, Ada Kodarou, BCH Decoder for Complex Error Correction, Publication No. 94-2112, March 17, 1994 '' is difficult to implement this division. By converting the testimony to the exponential representation of the primitive source of GF (2 ^m ), the multiplication and division on finite field is handled by addition and subtraction respectively. However, this method has the disadvantage of making it easier to add and divide on the finite field, and it is difficult to add. Also, when m is large, the capacity of the ROM to be converted to exponential is also increased.

`` Kim Young-min, Jeon In-san, Young-su Park, BCH (CODEC) capable of double error correction, Announcement No. 93-11573, 1993.12.11 '', calculates (S ₁ ² + S ₃ S ₁ ^-1 ) of Equation 21 in advance Since we need m x 2 ^m bit ROM, we don't calculate it all at once, we get only the inverse S of S using m x 2 2 ^m bit ROM, then multiply it by S _n and add it with S ₁ ² I'm using the method. However, this method also uses division, which results in a complicated circuit.

Therefore, the object of the present invention is to reduce the circuit area by not using division in the process of finding the error position polynomial from error in the case of the double error correction BCH code that can correct all errors of 2 bits or less occurring within a block. The present invention provides a decoding method of a double error correction BCH code and an apparatus thereof.

Comprising the steps of: In order to achieve the above object, the output obtained ohjeung S ₁ and S ₃ in the decoding method of the error-correcting BCH code of the second of the present invention and store in the buffer, the bits are received at the same time,

And wherein if S ₁ is 0, it is determined that the error did not occur to output as the received bit in the buffer, and the output S ₁ is not zero to calculate the S ₁ ² and ⁽³ S ₁ + S _3),

Converting S ₁ ² to α ⁱ and (S ₁ ³ + S ₃ ) to α ²ⁱ by converting i = 1,2,3, ..., n to multiply these S ₁ by 0 Implement the steps to correct the error by inverting the emerging bits.

In order to achieve the above object, the decoder of the error correcting BCH code of the second of the present invention ohjeung calculation means for obtaining the output ohjeung S ₁ and S ₃ and at the same time storing the bits received in the buffer and,

If S ₁ is 0, it is determined that no error has occurred and the reception bit of the buffer is output as it is. If S ₁ is not 0, error location calculating means for calculating and outputting S ₁ ² and (S ₁ ³ + S ₃ ) and,

S ₁ ² is multiplied by α ⁱ , (S ₁ ³ + S ₃ ) and α ²ⁱ is changed to i = 1,2,3, ..., n and multiplied by these S ₁ is 0 then buffer Error detection means was provided for correcting errors by inverting the bits coming out.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in more detail.

4 is a block diagram illustrating a decoder of a double error correction BCH code according to an embodiment of the present invention, which stores the received bits in a buffer and simultaneously calculates and outputs a testimony S ₁ and S ₃ . Wow,

If S ₁ is 0, it is determined that an error has not occurred, and the received bit of the buffer is output as it is. If S ₁ is not 0, an error position calculation unit for calculating and outputting S ₁ ² and (S ₁ ³ + S ₃ ) With 22,

Converting S ₁ ² to α ⁱ and (S ₁ ³ + S ₃ ) to α ²ⁱ by converting i = 1,2,3, ..., n to multiply these S ₁ by 0 An error detection unit 23 for correcting an error by inverting the output bit was provided.

When double error correction is BCH code, that is, when t = 2, the determinant | A | that determines the number of errors actually occurred is | A | = S _1, so only when there are no more than t-2 errors, that is, no error occurs. When S ₁ = 0 and t or t-1 errors, or 2 or 1 errors, focus on S ₁ ≠ 0 and multiply both sides of Equation 21 by S ₁ .

Equation 22 shows that division is gone. Therefore, the complexity of the circuit can be greatly reduced by not using an inverse calculator.

Indeed, compared to Figure 3, the remainder is the same except that it is changed to an adder instead of an inverse calculator. Therefore, it can be seen that the circuit scale is greatly reduced.

As described above, in case of using the double error correction BCH code decoding method and apparatus of the present invention, the error correction enables the receiver to directly correct a bit error occurring on the communication path of the digital communication system or the data storage system. By omitting division in the process of finding the error position polynomial from the misrepresentation in the code, the area of the circuit is reduced as compared with the conventional decoder.

Claims (2)

A communication error correction code decoding method for the bit error to be directly corrected on the receiving side that occur within a digital communication systems or data storage systems, the received bits at the same time stores in a buffer obtaining a ohjeung S ₁ and S ₃ and outputting, if the S ₁ is 0, it is determined that the error did not occur to output as the received bit in the buffer, S ₁ is 0, or S ₁ ² and (S _{1 ³} + S ³⁾ to calculate the output Multiplying S ₁ ² with α ⁱ and (S ₁ ³ + S ₃ ) by converting α ²ⁱ to i = 1,2,3, ..., n and adding these S ₁ to 0 And then correcting the error by inverting the buffer. In digital communication systems or data storage systems, communications error correction code decoding apparatus for direct correction on the receiving side the bit error occurring in a, the received bit is simultaneously storing and outputting obtain the ohjeung S ₁ and S ₃ If the error calculation means and S ₁ is 0, it is determined that no error has occurred and the buffer's reception bit is output as it is. If S ₁ is not 0, S ₁ ² and (S ₁ ³ + S ₃ ) are calculated and output. an error position calculation means and that, for the α ^{2 i} S _1, ⁽³ S ₁ + S ₃₎ to the α ²ⁱ for i = 1,2,3, ..., while multiplied by conversion to n plus and these S ₁ And an error detecting means for correcting an error while inverting the bits coming out of the buffer if the value is zero.