KR0147406B1 - Non-volatile memory device & its fabrication method - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a structure and a manufacturing method of an EEPROM cell which maximizes the effective capacitor area between a floating gate and a control gate to improve device characteristics and greatly increase reliability.

The nonvolatile semiconductor memory device of the present invention comprises a gate oxide film formed on a channel region on a first conductive semiconductor substrate, a field oxide film formed on a portion other than the channel region, and the gate oxide film and field oxide film. A floating gate formed of a stack structure having a width wider than that of the gate oxide film, a dielectric layer (ONO) formed uniformly on the surface of the floating gate, the dielectric layer, and a box shape surrounding the floating gate on the field oxide film. And forming a buffer oxide film and a first insulating layer in the channel region of the first conductive semiconductor substrate, and using the buffer oxide film and the first insulating layer as masks. And forming a field oxide film, removing the buffer oxide film and the first insulating layer, and forming a gate oxide film; Depositing a silicon layer, a second insulating layer, a second polysilicon layer, and a third insulating layer in order, and selectively etching so that only a portion of the channel region and the field oxide film remain, the first polysilicon layer, the second insulating layer, Forming a polysilicon sidewall on the side of the second polysilicon layer and the third insulating layer and removing the third insulating layer; depositing and etching back the fourth insulating layer to form a nitride sidewall; Etching the second polysilicon layer using the nitride sidewall as a mask and removing the second insulating layer and the nitride sidewall to form a floating gate; and a dielectric layer (Oxide-Nitride-Oxide: ONO) on the floating gate. ) And forming a control gate on the dielectric layer (ONO).

Description

Structure and manufacturing method of nonvolatile semiconductor memory device

1 (a) and (b) are structural cross-sectional views and equivalent circuit diagrams of a general EEPROM cell.

2 (a) and 2 (b) are structural cross-sectional views of a conventional EEPROM cell

3 (a) to (i) are process cross-sectional views of the EEPROM cell of the present invention.

* Explanation of symbols for main parts of the drawings

31: first conductive semiconductor substrate 32: buffer oxide film

33: first insulating layer 34: field oxide film

35 gate insulating film (oxide film) 36 first polysilicon layer

37: second insulating layer 38: second polysilicon layer

39: third insulating layer 40: third polysilicon layer

41: polysilicon sidewall 42: fourth insulating layer

43: night ride side wall 44: floating gate

45: dielectric layer 46: control gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and in particular, to maximize the effective capacitor area between a floating gate and a control gate, thereby improving the characteristics of the device and significantly increasing the reliability thereof. It relates to a structure and a manufacturing method.

As shown in FIGS. 1 (a) and (b) showing the structure cross-sectional view and equivalent circuit of a typical EEPROM cell, the EEPROM cell flows between the first conductive semiconductor substrate 31 and the control gate 46. There is a floating gate 44, and when a voltage Vg is applied to the control gate 46, the capacitance C ₁ between the control gate 46 and the floating gate 44, and the floating gate are provided. The capacitance C ₂ between the 44 and the first conductive semiconductor substrate 31 is divided into voltages of V ₁ and V ₂ and applied (Vg = V ₁ + V ₂ ).

here, Coupling Ratio is Represented by

At this time, the memory and erase characteristics of the EEPROM vary depending on the size of V ₂ .

Therefore, to improve the memory and erase characteristics of the EEPROM, there are a method of increasing the size of V ₂ and a method of increasing the coupling ratio.

However, in order to increase V ₂ , the control voltage of the control gate 46 must be increased, so the power consumption of the device is increased, and there is a problem in the reliability of the insulating material between the floating gate 44 and the control gate 46. do.

Therefore, it is effective to increase the coupling ratio in order to improve the effective capacitance without changing Vg or lowering Vg.

Here, the method of increasing the coupling ratio includes increasing the effective capacitor area between the floating gate and the control gate to increase C ₁ , which is the capacitance between the floating gate and the control gate, and the capacitance between the substrate and the floating gate. There is a way to reduce C ₂ .

Hereinafter, a structure and a manufacturing method of a conventional EEPROM cell for increasing a coupling ratio will be described with reference to the accompanying drawings.

2 (a) and 2 (b) show a structural cross-sectional view of a conventional EEPROM cell. FIG. 2 (a) roughens the surface of the floating gate 44 to form the floating gate 44 and the control gate 46. The capacitance (C ₁ ) between) is improved, and FIG. 2 (b) shows a trench process in a field oxide region adjacent to the cell, thereby forming a floating gate 44 and a trench in the trench. By forming the control gate 46 to form a trench capacitor (Trench Capacitor) to increase the effective capacitor area.

However, in the related arts of FIGS. 2A and 2B, there is a limit to increasing the effective capacitor area, and in particular, in the method of FIG. 2B, a trench for increasing the effective capacitor area is shown. There was a problem that the process is very difficult.

The present invention has been made to solve the above problems of the prior art, the structure and fabrication of a nonvolatile semiconductor memory device that can improve the coupling ratio by effectively increasing the effective capacitor area between the floating gate and the control gate Its purpose is to provide a method.

The structure and manufacturing method of the nonvolatile semiconductor memory device of the present invention for achieving the above object is characterized by increasing the effective capacitor area by forming a floating gate and a control gate in the form of a box (box) of the stack structure do.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 (a) to (i) show a process cross-sectional view of the EEPROM cell of the present invention. First, as shown in FIG. 3 (a), the buffer oxide film 32 is formed on the first conductive semiconductor substrate 31. And the first insulating layer (Nitride) 33 are sequentially deposited, and a photolithography process is performed by using the active mask (not shown) as the first conductive semiconductor substrate 31 as an end-point. The buffer oxide layer 32 and the first insulating layer 33 are selectively removed to remain only in the channel region, and then ion implantation of the second conductive impurity is performed to form source and drain regions.

As shown in FIG. 3 (b), the field oxide film 34 is formed by the oxidation process and the source and drain regions are diffused.

Subsequently, the buffer oxide film 32 and the first insulating layer 33 on the upper side of the channel region are removed, and the gate insulating film (oxide film) 35 is formed on the channel region. Then, as shown in FIG. Polysilicon and nitride are alternately deposited to form a first polysilicon layer 36, a second insulating layer 37, a second polysilicon layer 38, and a third insulating layer 39 in this order. .

As shown in FIG. 3 (d), the first polysilicon layer 36, the second insulating layer 37, and the second polysilicon layer in the field region are formed by a photolithography process using the field oxide film 34 as an end point. (38) The third insulating layer 39 is removed so that only a portion of the channel region and both field oxide films 34 remain, and then polysilicon is deposited on the entire surface to form the third polysilicon layer 40.

Subsequently, as a result of the process 36, the third polysilicon layer 40 is etched back as shown in FIG. 3 (e) to leave only a portion of the channel region and both field oxide layers 34. The polysilicon sidewall 41 is formed so as to remain only on the sidewalls of (37), (38) and (39).

Subsequently, the third insulating layer 39 is removed as shown in FIG. 3 (f), and a nitride film is deposited on the entire surface as shown in FIG. 3 (g) to form the fourth insulating layer 42. As shown in (h), the fourth insulating layer 42 is etched by an etch back process to form the nitride sidewall 43.

After the second polysilicon layer 38 is used as a mask and the second insulating layer 37 is used as an end point by using the nitride sidewalls 43 inside the polysilicon sidewalls 41 as the mask, As shown in FIG. 3 (i), the second insulating layer 37 and the fourth insulating layer 42 are removed to form the floating gate 44.

Subsequently, an oxide layer and a nitride layer are sequentially deposited on the surface of the floating gate 44 to uniformly form a dielectric layer (Oxide-Nitride-Oxide: ONO) 45 and deposit polysilicon to control it. The gate 46 is formed.

EEPROM of the present invention configured as described above is a method of increasing the effective capacitor area by forming a floating gate and a control gate in the form of a box (box) of a stack structure to increase the capacitance C ₁ , which is the capacitance between the floating gate and the control gate. In order to improve the characteristics of the device, it is possible to solve the difficulty of the process, which is a problem of the trench type nonvolatile semiconductor memory device, and in particular, to increase the value of C ₁ by 3 to 4 times or more. In order to maintain a constant voltage on the floating gate 44, the voltage applied from the outside can be greatly reduced, thereby greatly increasing the reliability of the dielectric layer (ONO) 45 between the control gate 46 and the floating gate 44. It is effective to improve.

Claims (2)

A first insulating layer formed on the substrate having a source and a drain; A floating gate formed of a first conductive layer formed on the first insulating layer, a second conductive layer formed on both sides of the first conductive layer, and a third conductive layer protruding in a direction facing each other on the second conductive layer; A dielectric film formed on the floating gate; And a control gate formed on the dielectric film. Sequentially forming a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer on the substrate; Forming first conductive side walls on both sides of the first and second conductive layers; Removing a portion of the second insulating layer and the second conductive layer; Removing the first insulating layer to form a first gate; Forming a dielectric film over the first gate; A method of manufacturing a nonvolatile semiconductor memory device having a source and a drain, which are formed by forming a second gate on the dielectric film.