KR0146559B1 - Matching device using t1 link of communication - Google Patents

Abstract

The present invention relates to a matching device for processing packet data using a T1 link in a communication network. The present invention relates to a system for transmitting packet data between systems installed at a remote location without limitation by using a T1 transmission path and a transmission device in a public communication network and a mobile communication network. The present invention relates to a matching device for processing packet data using a T1 link that can transmit and receive as long as the performance of a transmission channel is allowed, regardless of the amount. Applicable to interlinks.

Accordingly, the T1 PCM link can be used to configure a network without limitation of distance in public communication networks, mobile communication networks, packet communication networks, and the like, and thus an economical network can be constructed.

Description

Matching device using T1 link of communication in the communication network

1 is a diagram illustrating a connection configuration between a T1 link matching device and an external block in a communication network of the present invention.

2 is an internal block diagram of the present invention.

3 is a circuit diagram of a crystal clock generator for IPC matching.

4 is a timing analysis diagram of a clock output from each part of FIG.

5 is a modified clock timing analysis diagram for matching with a node board.

* Explanation of symbols for main parts of the drawings

110: digital phase locked loop circuit 120: processor matching circuit

130: IPC matching circuit 140: T1 framer

150: time switch 211: clock dispenser

212: counter driving unit 213: counter

214: clock distribution unit 230: processor control signal unit

240: Board decoder 250: IPC data transmission and reception unit

The present invention relates to a matching device for processing packet data using a T1 link in a communication network. In particular, the present invention relates to a channel-specific communication between a base station and a control station in a CDMA mobile communication network by applying a T1 1544 Kbps transmission method used in an existing communication network. A matching device for processing packet data using a T1 link for transmitting and receiving in the form of unnecessary packets.

Due to the rapid development of communication networks, the use of data networks for data communication and packet networks for computer communication is increasing in general telephone network-oriented communication networks, and various technologies for this are being actively progressed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a T1 link matching device in a communication network for transmitting and receiving packet data of a remote subscriber matching device and a home office switching period in a PSTN and ISDN network as well as a mobile communication network.

The present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a connection configuration between a T1 matching device for packet transmission and an external block of the present invention.

The packet communication node controller 101 is a high-capacity processor communication node control board that provides each node with a bus arbitration clock and a frame synchronization signal used for bus arbitration at the processor node, and monitors each node status and performs periodic tests. Maintenance function to perform the operation, redundancy control function to perform node switching, node matching device switching and data bus switching according to the scope of the failure if it is determined as a failure state, and if necessary, during startup or operation. This function initializes address, attribute, and property values, and monitors the status of initialization of T1 link matching board and maintenance of transmission path.

The packet communication node matching device 102 may be connected to up to eight nodes per board, and may be connected to the T1 link matching device 103 to perform interprocessor communication.

In addition, the T1 link matching device 103 matches the packet type data received from the packet communication node matching device 102 with a T1 frame type using a MT8980 256x256 time slot time switch and a MH89760 T1 framer element of Mitel Corporation. It is connected and operated without any distance limitation, and performs maintenance function under the control of processor communication node control device.

2 is a detailed internal block configuration connected to the T1 link matching device 103 of the present invention, and includes a digital phase locked loop circuit 110, a processor matching circuit 120, an IPC matching circuit 130, and T1. The framer 140, the time switch 150, and the T1 transmit / receive circuits 145 and 146 are connected to the T1 link matching device 103, and the T1 link matching device 103 supplies a correction clock for IPC matching. The crystal clock generator 210, the clock divider 220, the framing synchronization signal distributor 225, the processor control signal 230, the board decoder 240, and the IPC data transmitter / receiver 250 are included. .

The T1 link matching device 103 may be configured to distribute the clock supplied from the digital phase locked loop circuit 110 to a desired clock and supply the same to the T1 framer 140 or the time switch 150. A clock divider 220 composed of first to third clock dividers 221 to 223, a frame sync signal divider 225 for supplying a framing sync signal supplied from the digital phase locked loop circuit 110, and a digital A time clock for a read / write signal received from a processor and a correction clock generator 210 which is generated by correcting a predetermined clock supplied from the phase locked loop circuit 110 to a transmission clock of the IPC matching circuit 130. A processor control signal to transmit to the processor matching circuit 120 by generating a signal for controlling the address gate of the processor matching circuit 120 using the transmission to the 150 and the read / write signal. The 230 and the board address received from the processor matching circuit 120 to decode the T1 board, select the time switch 150 for accessing the T1 link in the T1 board, the corresponding T1 The board decoder 240 selects the alarm state control of the link, and the IPC data transmitter / receiver 250 transmits and receives IPC data, a clock, and an alarm between the T1 framer 140 and the IPC matching circuit 130.

Referring to the operation of the present invention configured as described above, the digital phase locked loop circuit 110 is a circuit for supplying a clock required for the T1 link matching device 103, and for driving the T1 framer 140 and the time switch 150. The frame synchronization signal, the 1.544 MHz, 2.048 MHz, and 4.096 MHz clocks are operated by the oscillation frequency of the digital phase locked loop unit 110 to supply the sources of all the clocks in the T1 link matching device 103.

In this case, the data itself has a form of a high-level data link control (HDLC) in the form of a packet, and the T1 link matching device 103 sends data with the transmission clock, and the nodeboard transmits the data using the received clock. By transmitting to 103, the system synchronization problem is solved by patching data with the same clock source.

However, even in this case, since the clock and data transmission methods are transmitted using the ELA-422 method, delay factors due to the transfer delay of the ELA-422 matching element and the pattern on the back board are generated.

In consideration of the delay factor, various clocks are supplied through the first to third clock dividers 221, 222, and 223 in order to have sufficient timing margin in the T1 link matching device 103.

The processor matching circuit 120 sends a read / write signal received from the processor to the processor control signal unit 230 and the board decoder 240, and the processor control signal unit 230 and the board decoder 240 receive the received signals. The read / write signal is controlled to send a read / write signal to the corresponding time switch 150.

On the other hand, when the time switch 150 receives a predetermined signal from the processor, the processor matching circuit 120 informs the processor that the signal has been decoded and performs the inverse of processor matching.

The processor control signal unit 230 and the board decoder 240 have a decoding logic function that decodes the board address received from the processor matching circuit 120 to select not only a board but also two time switches 150 and a remote alarm and low. There is a decoder function to select curl alerts.

The board selection function of the board decoder 240 allows the processor of the node control board to select a board to be accessed from among six T1 boards as an address.

In addition, eight T1 links in the T1 board are controlled by two time switches. Since each time switch 150 controls four T1 links, the time switch 150 for accessing the corresponding T1 link is used as a board address. Make a choice.

On the other hand, the status of the corresponding T1 link can be monitored and the alarm status can be controlled by the board address.

The IPC matching circuit 130 transmits the received IPC data, clock, and alarm to the T1 framer 140 through the IPC data transmitting / receiving unit 250, and transmits the data, clock, and alarm received from the T1 framer 140 to the IPC. The data transmission / reception unit 250 transmits to the IPC matching circuit 130.

The T1 framer 140 is matched with the T1 transmit / receive circuits 145 and 146 in the T1 framing form recommended by the ITU-T, connected to the transmission path, and receives the data received by the IPC match circuit 130 from the T1 transmit circuit 145. Send via

Data received through the T1 receiving circuit 146 is also transmitted to the IPC matching circuit 130 via the T1 framer 140.

The T1 framer 140 is initialized through a time switch by a control processor in the node control board, and has a structure of continuously reporting its status to the processor through the processor matching circuit 120.

The T1 transmission circuit 145 transmits the unipolar data output from the T1 framer 140 to the transmission line by making the bipolar pulse waveform recommended by the ITU-T, and provides an equalization function according to the distance between the relays (O / R). To perform.

The T1 receiving circuit 146 reproduces the bipolar data input through the inter-station repeater as unipolar pulses and inputs them to the T1 framer 140.

The time switch 150 is a 256x256 non-blocking time switch and is a circuit capable of switching between input and output channels. It is configured using the MT8980 device of Mitel Corporation. In the present invention, the time switch 150 is used as a circuit for matching between the T1 framer 140 and the control processor. It was.

In addition, the time switch 150 monitors the state of the T1 framer 140 and reports the abnormal condition to the data processor through the processor control signal unit 230, the board decoder 240, and the processor matching circuit 120. It plays a role.

The correction clock generator 210 receives a 2.048 MHz clock from the digital phase locked loop circuit 110 and makes a modified clock as shown in FIG. 5 to provide a transmission clock of the IPC matching circuit 130.

In order to map T1 transmission method and Mitel's ST-bus, meaningless data is output at time slots 0, 4, 8, 12, 16, 20, 24 and 28. Therefore, the data must be ignored and configured in the system. .

For this operation, the system clock was modified so that the clock was not sent out during the timeslot in every frame so that data during this period would not be read.

The first clock divider 221 in the clock divider 220 receives the 1.544 MHz clock from the digital phase locked loop circuit 110 and supplies clocks to eight T1 link matching device framers 140 in consideration of fan out. Since the modified 2.048MNz clock transmitted to the packet node board is delayed than the original 2.048MNz clock, the first clock divider 221 also adjusts the delay of the clock equally.

The second clock divider 222 receives the 2.048 MNz clock from the digital phase locked loop circuit 110 and supplies the clock to eight T1 framers 140 in consideration of fan out and transmits the clock to the packet node board. Since the MNz clock is delayed than the original 2.048 MNz clock, the second clock divider 222 also adjusts the delay of the clock equally.

The third clock divider 223 receives the 4.096 MHz clock from the digital phase locked loop circuit 110 and supplies the clocks to the two time switches 150, in order to synchronize with the 2.048 MNz clock and the frame synchronization signal. It also performs the function of having the same delay.

The frame synchronizing signal distributor 225 supplies the framing signals received from the digital phase locked loop circuit 110 to the two time switches 150 and the eight T1 framers 140 in consideration of their neighbors.

This signal also performs the function of having the same delay to synchronize the clocks.

The processor control signal unit 230 transmits a read / write signal received from the processor to the time switch 150.

In addition, a signal for controlling the address gate of the processor matching circuit 120 is generated using this read / write signal and transmitted to the processor matching circuit 120.

The board decoder 240 allows the processor to select a board among six T1 boards as a board address for board selection, and also controls eight links in the T1 board through two time switches 150. Each time switch 150 controls four T1 links.

Therefore, the time switch 150 for accessing the corresponding T1 link can be selected as the board address.

On the other hand, monitoring the status of the link to inform the alarm status and controlling it can also be selected as the board address.

FIG. 3 is a detailed circuit of the IPC matching correction clock generator 210 for processing IPC packet data, and divides a predetermined clock (2.048MNz) supplied from the digital phase locked loop circuit 110 into a predetermined clock (256MHz). A clock divider 211 for generating a), a counter driver 212 for delaying and outputting a counter driving signal externally inputted according to a predetermined clock output from the clock divider 211 for a predetermined time, and A counter 213 driven according to a drive signal of the counter driver 212 to output a signal for generating a mask waveform for a predetermined channel period, and the counter 213 according to a different clock (4 MHz) input from the predetermined clock; The phase of the mask waveform generation unit 214 for generating a mask waveform by delaying the signal outputted by the predetermined time and the predetermined clock supplied from the digital phase locked loop circuit 110 Depending on the type and the logical product of the masked waveform generated by the waveform generating unit mask 214 is comprised of a logical operation unit 215 for supplying a clock for matching IPC.

The clock divider 211 may include a first inverter 211a which phase-inverts a predetermined clock supplied from the digital phase locked loop circuit 110, and a phase inverted signal from the first inverter 211a. A NAND gate 211b for controlling a preset of a plurality of flip-flops 211f, 211g, and 211h according to an output signal obtained by negatively multiplying a signal in which an input counter driving signal is phase inverted, and the first inverter A plurality of flip-flops 211f, 211g and 211h which are driven according to a clock signal inverted through phase 211a to divide a predetermined clock into a predetermined clock, and the plurality of di-D flip-flops 211f and 211g. 2, 3, and 4 inverters 211c, 211d, and 211e for reversing and outputting the clock signals outputted from, 211h), respectively.

In addition, the counter driver 212 logically multiplies the fifth inverter 212a for inverting the counter driving signal input from the outside with the phase inverted signal and the delayed feedback output signal through the fifth inverter 212a. A de-flop flop that delays and outputs a signal multiplied by the first and gate 212b and the first and second gates 212b according to a clock output from the de-flop 211g of the clock divider 211. 212d, and a sixth inverter 212e for reversing the phase of the signal output through the flip-flop 212d.

The mask waveform generation unit 214 is a NOR gate 214a and a seventh inverter 214b for stabilizing and outputting a signal output from the counter 213, and a predetermined clock 4M supplied from the outside. Outputs a mask waveform by delaying a signal through the eighth inverter 214c and the buffer 214d and the seventh inverter 214b according to a clock supplied from the buffer 214d. The flip-flop 214e is comprised.

In addition, the logic operation unit 215 may include a ninth inverter 215a for reversing a predetermined clock (2.048 MNz) supplied from the digital phase locked loop circuit 110, and a clock through the ninth inverter 215a. The mask waveforms 214b and 215c generate a predetermined clock by logically multiplying the mask waveforms output from the mask waveform generator 214.

The operation of the modified clock generator 210 configured as described above is as follows.

In the process of processing T1 transmission data as IPC data, channels 0, 4, 8, 12, 16, 20, 24, and 28 are not IPC data but contain a meaningless data on the ST bus. Do not let it.

Therefore, the second clock divider 222 divides the 2.048 MNz clock into 256 MHz clock to form an 8-bit x 32 channel, and the period of channels 0, 4, 8, 12, 16, 20, 24, 28 through the counter 213. The MASK waveform is created so that the output will be low during the rest and high during the rest of the channel.

On the other hand, after inverting the 2.048MNz clock through the ninth inverter 215a, the mask waveform output from the mask waveform generator 214 is logically multiplied by the second and third end gates 215b and 215c, thereby increasing the high ( The clock is supplied while the channel is masked high, and the clock is not supplied during the period masked low.

4 is a timing analysis diagram.

First, the framing signal always has a cycle of 125usec, and 8000 framing signals are generated per second.

The period during which the framing signal goes to zero is 488 nsec, and the start of the 2.048 MNz clock starts at 244 nsec after the framing signal goes to zero.

The clock has a 2.48 Mbit / sec rate, with 256 cycles of 32 channels x 8 bits.

The start of the 4.096 MHz clock is the point at which the framing signal is zero, the clock rate is 4.096 Mbit / sce, and the cycle is 512 cycles.

The start of data starts at 244 nsec after the framing signal goes to zero.

5 is a timing analysis diagram of the correction clock.

The data starts at 244 nsec after the framing signal goes to zero, and 32 channels of data are continuously input until the next framing signal.

On the other hand, the start of the 2.048 MNz clock also starts at 244 nsec after the framing signal drops to 0, so data cannot be read using this clock.

Therefore, the clock is modified to delay the clock for half a period so that data can be read from the rising edge of the clock.

In addition, 24 channels among 32 channels can be used for the T1 method, which is because channels 0, 4, 8, 2.048 MNz 12, 16, 20, 24, 28 are not IPC data and are excluded as unused for T1 transmission. By not sending out the clock for IPC matching during the period, it is possible to generate a clock for IPC matching to enable IPC matching.

As described above, the present invention can be applied to processor communication between a base station and a control station in a mobile communication network, and is currently applied to a network interworking between a base station and a control station in a CDMA mobile communication network, and a remote subscriber in a PSTN and ISDN network as well as a mobile communication network. It can be applied to the connection between the matching device and the exchange period of the home country, and also can be operated by using the existing T1 transmission line and transmission equipment, thereby enabling economical network operation without being limited by distance.

Claims (2)

A clock divider 220 for distributing a clock supplied from the digital phase locked loop circuit 110 to a desired clock and supplying the clock to the T1 framer 140 or the time switch 150 and the digital phase locked loop circuit 110. A correction clock generated by modifying the frame synchronization signal distribution unit 225 for supplying the framing synchronization signal and the predetermined clock supplied from the digital phase locked loop circuit 110 to the transmission clock of the IPC matching circuit 130. A processor matching circuit by generating a signal for controlling the address gate of the processor matching circuit 120 by transmitting the read / write signal received from the generator 210 and the processor to the time switch 150 and using the read / write signal. Decodes the processor control signal unit 230 transmitted to the 120 and the board address received from the processor matching circuit 120 to select the corresponding T1 board, A board decoder 240 for selecting a time switch 150 for accessing a T1 link in the T1 board, and selecting an alarm state control of the T1 link, the T1 framer 140 and the IPC matching circuit 130; Packet data processing using a T1 link in a communication network comprising an IPC data transmitting / receiving unit 250 for transmitting and receiving IPC data, a clock, and an alarm between the packets, and transmitting and receiving packet data in a packet form that does not require channel classification in a communication network. Matching device for. The clock distribution unit 220 receives a plurality of predetermined clocks supplied from the digital phase locked loop circuit 110 and equalizes a delay of a clock to synchronize a modified clock with an original clock. A matching device for processing packet data using a T1 link in a communication network, characterized by comprising a plurality of clock dividers (221-223) to adjust.