KR0143117B1 - Cut-off apparatus of d.c. off-set for hdtv receiving using vsb - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

It is a device to remove DC offset remaining after data demodulation in HDTV receiver using VSB modulation.

2. Technical problem to be solved by the invention

This solves the problem that the demodulation data error occurs because the DC offset value is not completely removed due to noise in multipath signal interference.

3. Summary of the solution of the invention

When demodulating in HDTV receiver using VBS modulation, obtain DC average value for channel equalizer input signal during field synchronization during the field synchronization, and then remove the offset.If offset still exists, average the output value of channel equalizer and estimate the offset. Eliminate the DC offset.

4. Important uses of the invention

It is applied to the offset elimination device in HDTV receiver using V B S modulation.

Description

DC Offset Elimination Device for High Definition Television Receiver Using Residual Sideband Modulation

1 is a conventional DC offset elimination circuit diagram

2 is a DC offset cancellation circuit diagram according to the present invention.

* Explanation of the major signs among the reference signs in the drawings

30: tuner 32: carrier recovery

34: A / D converter 36, 44: Adder

38: Field synchronous detector 40: Channel equalization performance predictor

42,50: first-second DC value measuring instrument 46: latch

48, 52: first-second switch 54: channel equalizer

The present invention relates to a DC offset removing apparatus for HDTV receivers using a residual side band (VSB0) modulation, and more particularly, to an apparatus for removing DC offset remaining after data demodulation in an HDTV receiver using VSB modulation. will be.

In general, the HDTV method using VSB modulation may be a representative example of 8-level HDTV, which is a standard of the United States, and this method applies a pilot signal corresponding to a carrier to a transmission signal for carrier recovery of a receiver. It will be loaded and sent. However, even though the carrier recovery was perfect at the receiver stage, the carrier recovery could not be done correctly in synchronization with the pilot signal in the main path. This is because in the multipath situation, a signal that is not only the main path but also the subpaths causing the interference is added to the receiver. That is, since the pilot signal at the receiver stage is shown as a sum of vectors of a plurality of pilot signals passing through the multipath, the carrier recoverer synchronizes with this. However, since the signal to be received at the receiving end passes only the main path, a constant phase difference always occurs between the phase of the pilot signal of the main path and the vector sum signal of the pilot signal input from the receiver. This phase difference must induce dc offset, and this generated DC offset has to seriously affect the performance of the channel equalizer, so it must be removed.

FIG. 1 is a conventional DC offset elimination circuit diagram, in which a high frequency signal received through an antenna is tuned to a desired channel through a newner 10, converted into an intermediate frequency band, and output to a carrier north flag 12. The carrier recoverer 12 demodulates the signal converted into the intermediate frequency band into a baseband signal and outputs the demodulated signal to the A / D converter 14. The A / D converter 14 converts the signal demodulated to the baseband signal into a digital signal and outputs the digital signal to the adder 18 and the field synchronous detector 16. However, the FCC ACATS (Advisory Committee on Advanced Television Service) recommendation, which enacted the US HDTV standard, transmits the field synchronization signal transmitted to adjust the channel equalizer inserted every 24.2ms. Therefore, the field synchronous detector 16 detects the field synchronous signal from the signal digitally converted from the A / D converter 14 and outputs it to the control terminal of the switch 22. At this time, the switch 22 is turned on every time a field synchronization signal is detected from the field synchronization detector 16. When the switch 22 is turned on, the DC value measuring device 20 measures the DC value output from the adder 18 and applies it to the adder 18. Therefore, the adder 18 subtracts the measured DC value from the digitally converted signal from the A / D converter 14. This removes the DC offset value. The channel equalizer 24 removes the existing signal interference on the reception path from the value from which the DC offset is removed from the adder 14.

However, the conventional DC offset elimination circuit as described above has a problem in that an error of demodulation data is generated because the DC offset value is not completely removed due to noise in the multipath signal interference.

Accordingly, an object of the present invention is to provide a DC offset elimination circuit for preventing an error of demodulation data as described above.

Another object of the present invention is to provide a DC offset removing apparatus for removing a DC offset in an HDTV receiver using VSB modulation.

The present invention for achieving the above object is a tuner for converting the high-frequency signal received through the antenna to a desired channel to convert to the intermediate frequency band and outputs, and demodulated to the baseband signal to output the signal converted to the intermediate frequency band A DC offset canceller for a high-definition television receiver using a residual sideband modulation comprising a carrier recoverer and an A / D converter for converting a signal demodulated to the baseband signal into a digital signal and outputting the digital signal. A first adder which adds and outputs a predetermined DC measurement value from the digitally converted signal, a channel equalizer which removes and outputs an existing signal interference on a reception path from a value from which the DC offset is removed from the first adder; A first DC value measuring device for measuring and outputting an average DC value of several signals output from one adder; 1 a latch for storing an output value of the DC value measuring instrument, a field synchronous detector for detecting and outputting a field synchronous signal from a signal digitally converted from the A / D converter, and a period during which a field synchronous signal is detected from the field synchronous detector. A channel equalization performance predictor for outputting a channel equalization convergence or divergence determination signal by comparing an error value between the signal output from the channel equalizer and a known transmission signal with a predetermined signal, and switching on by the channel equalization convergence signal; A first switch for latching an output signal of the first DC meter, a second switch switched on by the channel equalization convergence signal, and applying an output signal of the channel equalizer to a second DC value meter; Receive the field sync detection signal from the detector and measure the DC average value of several signals output from the channel equalizer. And a second adder for outputting a second DC value measurer and a signal output from the latch or a signal output from the second DC value measurer to an adder first adder.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a DC offset elimination circuit diagram according to the present invention. The neuter 30 tunes a high frequency signal received through an antenna to a desired channel, converts it into an intermediate frequency band, and outputs the intermediate frequency band to the carrier recoverer 32. The carrier recoverer 32 demodulates the signal converted into the intermediate frequency band into a baseband signal and outputs it to the A / D converter 34. The A / D converter 34 converts the signal demodulated to the baseband signal into a digital signal and outputs the digital signal to the adder 36 and the field synchronous detector 38. The adder 36 adds and outputs a predetermined DC measurement value from the signal digitally converted from the A / D converter 34. The channel equalizer 54 removes and outputs an existing signal interference on the reception path from the value from which the DC offset is removed from the adder 36. The first DC value measurer 50 measures an average DC value of several signals output from the adder 36 and applies it to the latch 46. The latch 46 stores the output value of the first DC value measuring device 50. The field synchronization detector 38 detects the field synchronization signal from the digitally converted signal from the A / D converter 34 and outputs the field synchronization signal to the channel equalization predictor 40 and the second DC value measuring instrument 42. The channel equalization performance predictor 40 compares an error value between a signal output from the channel equalizer 54 and a known transmission signal with a predetermined signal during a period in which the field synchronization signal is detected from the field synchronization detector 16. The channel equalization convergence or divergence determination signals are output to the first to second switches 48 and 52, respectively. The first switch 48 is switched on by the channel equalization divergence signal to apply the output signal of the first DC meter 50 to the latch 46. At this time, the second switch is turned off and the output of the second DC meter 42 is zero. The divergence here represents the period before the equalizer converges. The second switch 52 is switched on by the channel equalization divergence signal to apply the output signal of the channel equalizer 54 to the second DC value measurer 42. At this time, the first switch 48 is turned off. The second DC value measuring unit 42 receives the field synchronizing detection signal from the field synchronizing detector 38, measures the DC average value of several signals output from the channel equalizer 54, and outputs the DC average value to the adder 44. The adder 44 applies the sum of the signal output from the latch 46 and the signal output from the second DC value measuring instrument 42 to the adder 36.

The operation of the preferred embodiment for removing the DC offset proposed in the present invention will be described in detail.

The signal received through the antenna is tuned to a desired channel via the tuner 30, and then converted into an intermediate frequency band and output to the carrier recoverer 32. The carrier recoverer 32 demodulates the signal converted into the intermediate frequency band into a baseband signal and outputs the demodulated signal. At this time, the signal demodulated by the carrier recoverer 32 has an interference DC offset between signals due to noise and a multipath phenomenon. This is converted into a digital signal by the A / D converter 34. At this time, the digitally converted signal is output to the channel equalizer 54 through the adder 36. Therefore, the channel equalizer 54 removes and outputs the interference between signals generated by the multiple paths existing on the communication path in the transmission and reception period. The first DC value measurer 50 simply receives an output signal from the adder 36, obtains a DC average value for several input signals, and estimates a rough DC offset. The latch is an element for storing the output value of the first DC value measuring device 50. The second DC value measuring unit 42 measures a residual DC offset by inputting a signal from which the channel equalization is completed from the channel equalizer 54 and the interference between signals is removed to some extent. In this case, the DC offset measurement method may use an average value of just how many signals, as in the first DC value measuring device 50, or the field synchronization signal sent from the transmitter has already been promised which signal is sent. Since it is known, the DC offset is estimated from the average of the error signals by comparing the output signal of the channel equalizer 54 with a known signal. To this end, the field synchronization detector 38 should detect this signal and accurately inform the second DC value measuring unit 42 of the section in which the field synchronization signal exists. The channel equalization performance predictor 40 compares an error value between a signal output from the channel equalizer 54 and a known transmission signal with a predetermined signal during a period in which the field synchronization signal is detected from the field synchronization detector 38. The channel equalization convergence or divergence plate signals are output to the first to second switches 48 and 52, respectively. The channel equalization convergence or divergence signals X are calculated by Equation 1 below.

Where y1 is an output signal of the channel equalizer 54, Z1 is a known transmission signal, and ε is a preset value. That is, it is possible to determine that the channel equalizer 54 has converged by monitoring the error signal for the field synchronous good sync interval from the field synchronous detector 38. On the contrary, if the error is more than ε, it can be judged as divergence. Accordingly, the first switch 48 is switched on by the channel equalization divergence signal to apply the output signal of the first DC measuring device 50 to the latch 46. The second switch 52 is switched on by the channel equalization convergence signal to apply the output signal of the channel equalizer 54 to the second DC value measuring instrument 42. That is, if there is a signal from the carrier recoverer 32 that carrier recovery is completed initially, the first DC value measurer 50 is turned on and the second DC value measurer 42 is turned off. Thereafter, if there is a signal from the channel equalization performance predictor 40 indicating that the equalization is completed, the first DC value measurer 50 is turned off and the second DC value measurer 42 is turned on. If the channel condition is changed, the output error of the channel equalizer 54 increases. In this case, if there is a divergence determination of the channel equalizer 54 in the channel equalization performance predictor 40, the system is initialized and the above operation is repeated. To maintain stable reception performance.

As described above, the present invention obtains a DC average value for the channel equalizer input signal during field synchronization during the demodulation in an HDTV receiver using VBS modulation, removes the offset, and then averages the output value of the channel equalizer when there is an offset. By removing the residual DC offset by estimating the offset and estimating the offset, the error of the demodulated signal can be prevented and the performance of the receiver can be improved.

Claims (1)

A tuner that tunes a high frequency signal received through an antenna to a desired channel, converts it into an intermediate frequency band, and outputs it; a carrier recoverer that demodulates and outputs a signal converted into the intermediate frequency band to a baseband signal; A DC offset canceling device for a high-definition television receiver using a residual sideband modulation having an A / D converter for converting a demodulated signal into a digital signal and outputting the digital signal, wherein a predetermined DC measurement is performed from a signal digitally converted from the A / D converter. A first adder that adds and outputs a value, a channel equalizer that removes and outputs an existing signal interference on a reception path from a value from which the DC offset is removed from the first adder, and a plurality of signals output from the first adder A first DC value measuring device for measuring and outputting a mean DC value for the first DC value measuring device, and an output value of the first DC value measuring device A field synchronization detector for detecting and outputting a field synchronization signal from the digitally converted signal from the A / D converter, a signal output from the channel equalizer during a period in which the field synchronization signal is detected from the field synchronization detector; A channel equalization performance predictor for outputting a channel equalization convergence or divergence determination signal by comparing an error value with a previously known transmission signal to a set signal, and switching on by the channel equalization convergence signal to output an output signal of the first DC measuring device A first switch for applying a latch, a second switch that is switched on by the channel equalization divergence signal, and applies an output signal of the channel equalizer to a second DC value measuring device, and receives a field synchronous detection signal from the field synchronous detector A second DC value measuring device for measuring and outputting a DC average value of several signals output from the channel equalizer; Apparatus characterized in that the configuration of a signal or signals output from the second DC value output from the measuring value to a second adder which is applied to an adder a first adder.