KR0142527B1 - Bus interface circuit for interfacing two bus system - Google Patents

Abstract

The present invention relates to a bus interface circuit for mutually matching two bus systems, and in particular, two bus systems without affecting each other in communication between each system connected to two different types of buses, in particular, an electronic switch and other systems connected thereto. To a bus interface circuit for mutual matching.

A bus interface circuit for mutually matching two bus systems of the present invention includes a first bus system, a second bus system that is different from the first bus system, and a transmission for transmission from the first bus system to the second bus system. Reception means for receiving a reception signal, transmission means for receiving a transmission signal for transmission from the second bus system to the first bus system, reception assert signals from the reception means and transmission assert signals from the transmission means. Therefore, the signal receiving means blocks the transmitting means and operates the means, and when the signal is transmitted, it comprises a transmission / reception control means for blocking the receiving means and operating the transmitting means.

Description

Bus Interface Circuitry for Matching Two Bus Systems Together

1 is a block diagram of a bus interface circuit for mutually matching two bus systems according to a preferred embodiment of the present invention;

2 is a detailed circuit diagram of the bus interface circuit shown in FIG. 1;

3 is a waveform diagram of the signal for the main part.

* Explanation of symbols for main parts of the drawings

11: Receiver 13: Receiver Control Circuit

15: transmitter 17: transmitter control circuit

19: transmission signal monitoring circuit

The present invention relates to a bus interface circuit for mutually matching two bus systems, and in particular, two bus systems without affecting each other in communication between each system connected to two different types of buses, in particular, an electronic switch and other systems connected thereto. To a bus interface circuit for mutual matching.

In some situations, it may be necessary to match two bus systems in order to exchange information between two bus systems that operate separately.

In such a bus system, a deadlock condition may occur when two systems connected to two bus systems attempt to communicate at almost the same time through the same communication line.

A proposal to avoid this situation is disclosed in US Pat. No. 4,234,919.

This technology sets all information transfers to master / slave type, including master unit and slave unit. Therefore, when the system is powered on, the user must first determine the master and slave.

However, it was difficult and impractical to establish rules or procedures for initiating another system in one system.

In order to solve this problem, Korean Patent Publication No. 92-5284 includes at least one synchronous device that transmits asynchronous control signals scheduled in two directions between two bus systems under a bidirectional control signaling bus interface device name. The apparatus disclosed a structure having a pair of synchronizer elements.

However, the problem is that the technology must be very complex and expensive to provide.

It is an object of the present invention to provide a bus interface circuit which is simple in structure and inexpensive to match two bus systems without affecting each other in communication between two systems connected to two different types of buses.

In order to achieve the above object, the present invention provides a first bus system, a second bus system that is different from the first bus system, and a reception signal for transmitting from the first bus system to the second bus system. At the time of signal reception in accordance with a receiving means, a transmitting means for receiving a transmission signal for transmission from the second bus system to the first sus system, and a receiving assert signal from the fishery means and a transmitting assert signal from the transmitting means. Blocking the transmission means and operating the reception means, and when transmitting a signal, a transmission / reception control means for blocking the reception means and operating the transmission means for mutually matching two bus systems. Provides a bus interface circuit.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

The bus interface circuit of the present invention is effective for effectively connecting a system using a communication system different from the switch system, for example, an RS-422 bus, for example, a smart system, when developing and connecting an additional function to an all-electronic exchange. useful.

1 is a block diagram of a bus interface circuit for mutually matching two bus systems according to one preferred embodiment of the present invention.

In FIG. 1, one bus is, for example, a system bus (SYS-BUS) of an electronic switchboard, and the other bus is, for example, an RS-422 bus (RS-BUS) capable of high-speed long-distance transmission. Is connected to a data processing device.

The present invention receives a signal sent from the system bus (SYS-BUS) of the exchange, and receives from the receiver 11 and the system bus (SYS-BUS) of the exchange carrying the received signal on the RS-422 bus (RS-BUS) A receiver control circuit 13 for generating a reception control signal R × CNTL for connecting or disconnecting the receiver 11 according to a combination of one signal and a signal to be transmitted to the system bus (SYS-BUS) of the exchange; And a transmitter 15 for transmitting a signal received from the RS-422 bus to the exchange via the system bus SYS-BUS, and responding to a signal received from the RS-422 bus. And the transmitter control circuit 17 which cuts off the operation of the receiver 11 and generates a transmission control signal T × CNTL for operating only the transmission 15.

In addition, the transmitter control circuit 17 has a transmission signal monitoring circuit 19 to block the transmitter 15, even during transmission, in the event of a failure in the transmission signal to exclude the effect that may have an effect on the exchange system by abnormal operation.

That is, the transmission signal monitoring circuit 19 receives the signal TXASSERRT, which is the output signal of the transmitter comparator 23, from the detailed circuit shown in FIG. 2 and transmits the signal to the exchange. In the case where the abnormal exchange is held, the exchange cannot perform other operations, and after a predetermined time, it sends an assert fault signal (ASSERT FAULT) to the transmitter control circuit 17 to block the transmitter 15.

The present invention configured as described above allows the receiver 11 to operate only when there is a received signal and is designed to be in a transmission priority state so that the transmitter 15 always operates.

That is, when a transmission signal from the smart system via the RS-422 bus is applied to the transmitter 15 and the transmitter control circuit 17, the transmitter control circuit transmits the transmission control signal T × CNTL to the transmitter 15. And a signal received by the transmitter 15 on the exchanger system bus SYS-BUS, and the receiver control circuit 13 is adapted to the reception of the transmission control signal T × CNTL. Therefore, the receiver 11 is blocked.

On the other hand, when a signal is received from the exchange through the exchange system bus (SYS-BUS), the receiver control circuit 13 outputs the reception control signal (R × CNTL) to the receiver 11 so that the signal received at the receiver 11 is RS. Get on the -422 bus.

In this case, the receiver 11 has a structure that can prevent the output of the receiver 11 from being fed back to the exchange system through the transmitter 15 (see FIG. 2).

Hereinafter, a specific circuit of the present invention will be described with reference to FIGS. 2 and 3.

A personal computer (PC) that creates and provides an operating system (O / S) program of the exchange system, for example, to send signals to the exchange system via the RS-422 bus connected to the smart system. The high level (+) signal is applied to the terminal (ASSERT (+)) and the low level (L) signal is applied to the assert terminal (ASSERT (-)).

The signal is applied to the resistors R1, R2, and R3 constituting the reference voltage generator 21 so that the voltage V2 applied to the non-inverting terminal of the comparator 23 is applied to the inverting terminal. Make it bigger than

Therefore, the comparator 23 outputs a high level (H) signal to the output when the transmission signal is received. This signal forms a transmission assert signal T x Assert as an output signal of the transmitter 15 (Fig. 3 (a)).

The transmit assert signal TxASSERT operates the comparator 23 forming the transmitter via the OR gate 25 (FIG. 3d), and on the other hand, the inverter 27 through the OR gate 25. ) Is applied to one terminal of the AND gate 29 after being inverted to the low level (L). Therefore, the low level (L) signal is output to the output terminal of the AND gate 29 as the reception control signal (R x CNTL) to the buffer amplifier 31 constituting the receiver 11 (Fig. 3 (e)). The operation of 31 is interrupted.

On the other hand, the transmit assert signal T × ASSEERT is applied to the input of the resistor R4 and the inverter 33 whose one terminal is grounded, is inverted to the low level L by the inverter 33, and then again the inverter ( Inverted by 35, the high level (H) signal is applied to one terminal of the NAND gate 37.

On the other hand, a high level (H) transmit assert signal (T × ASSERT) is applied to the other terminal of the NAND gate 37, so that the signal transmission from the exchange system bus (SYS-BUS) is allowed to the output of the NAND gate 37. When the signal ASSERT * becomes the low level L, a transmission signal is output.

On the other hand, in the case of receiving a signal from the electronic exchange system via the system bus (SYS-BUS), when the signal (ASSERT *) from the system bus (SYS-BUS) goes to the low level (L), the high level through the inverter 39 (H) The signal is output. This signal becomes the receive assert signal R × CNTL and becomes the low level L through the inverter 4 and drops the transmission control signal T × CNTL to the low level L through the OR gate 25. Drop.

As a result, the operation of the comparator 23 serving as a transmitter is interrupted.

In addition, the low level (L) transmission control signal outputs a high level (H) signal to one terminal of the AND gate 29 through the inverter 27, and a high level (H) to the other terminal of the AND gate 29. Is applied to the RXASSERT. As a result, the reception control signal R × CNTL of the high level H is generated from the output of the AND gate 29 so that the buffer amplifier 31 constituting the receiver is operated so that the reception signal carries the RS-422 bus.

In this case, since the transmission and reception signals use a common bus, the reception signals can be returned through the transmitter. Accordingly, when only the signal is received from the exchange, the voltage V1 applied to the non-inverting terminal of the comparator 23 is smaller than the voltage V2 applied to the inverting terminal, so that the output of the low level L is less than the comparator 23. ) And this signal forms a high level H blocking signal BLOCK * via the inverter 33. By this signal, the feedback of the received signal through the NAND gate 37 is cut off, while the comparator 23 is cut off because the transmission control signal T × CNTL is at the low level L at the time of signal reception.

As described above, according to the present invention, two different buses are matched by a simple configuration, and the system does not affect the systems connected to each bus.

Although the above-described embodiment has been described in relation to the transmission and reception of signals for the electronic exchange and the RS-422 bus, those skilled in the art will understand that it is applicable to other systems and other buses without departing from the spirit of the present invention.

Claims (3)

A first bus system, a second bus system that is different from the first bus system, receiving means for receiving a reception signal for transmission from the first bus system to the second bus system, and from the second bus system. Transmitting means for receiving a transmission signal for transmission to the first bus system, and when the signal is received in accordance with a reception assert signal from the reception means and a damage assert signal from the transmission means, the transmission means is blocked and the means is operated. And transmitting / receiving control means for blocking the receiving means and operating the transmitting means when transmitting a signal. 2. The bus interface circuit of claim 1 wherein the first bus system is a system bus of an electronic exchange and the second bus system is an RS-422 bus. 2. The bus interface circuit of claim 1, further comprising transmission signal monitoring means for receiving the transmission assertion signal and blocking transmission means when a transmission signal fails.