KR0142470B1 - Synchronous counter circuit - Google Patents

Abstract

Since the number of logic gates used in the basic logic circuit that can realize the count operation is reduced, in order to provide a counter circuit that can optimize the design area when designing the count circuit, a high level H signal is input to the input terminal. Counter means for outputting a first signal OUTO to the second output terminal 01; The signal of the third output terminal 02 of the counter means of the preceding stage is input to the input terminal, and the signal OUTI of the corresponding bit is output to the second output terminal 01 to constitute a plurality of synchronization counters.

Description

Synchronous counter circuit

1 is a 3 bit down sync counter circuit according to an embodiment of the present invention;

2 is a basic logic circuit diagram of a synchronization counter according to an embodiment of the present invention;

3 is an operation timing diagram of a 3-bit down sync counter circuit according to an embodiment of the present invention;

4 is a circuit diagram of a conventional 4-bit synchronous counter,

5 is a circuit diagram of a conventional JK flip flop.

The present invention relates to a counter circuit, and more particularly, to a counter circuit that can realize an optimization of the design area when designing an n-bit counter circuit because it is designed by significantly reducing the number of transistors used to design the basic logic circuit. will be.

As the control operation of all electronic devices is being digitalized, the use of counter circuits is frequently made.

In order to design an n-bit synchronous counter circuit, conventionally, as shown in FIG. 4, whenever the corresponding pulse signal CP is applied to the clock terminal using n JK flip flops, the input terminals J and K are applied. Output signals A1 to An corresponding to the state of the input signal are output.

Therefore, n-bit output signals A1 to An are sequentially counted and output in synchronization with the pulse signal CP.

However, in order to design the n-bit counter circuit as described above, it is necessary to use n JK flip flops made up of a plurality of logic gates as shown in FIG. 5, so that the number of transistors used when designing the counter circuit increases.

When designing a NAND gate in which two signals are input, four transistors are required and a three-input NAND gate requires six transistors. Thus, a total of 40 transistors are required to design the JK flip flop as shown in FIG. Do.

Therefore, when designing a 4-bit synchronous counter circuit using four JK flip flops, a total of 168 transistors are required.

Each time the number of bits in a synchronous counter circuit is increased, at least 40 transistors are increased, so designing with one chip increases the product cycle and causes a lot of difficulty to optimize the area.

Therefore, an object of the present invention is to solve the above-described problems, and reduces the number of logic gates used in the basic logic circuit that can realize the counting operation. Therefore, the synchronization can be optimized when designing the count circuit. It is to provide a counter circuit.

A structure of this invention for achieving the above object comprises: a counter means for inputting a high level H signal to an input terminal and outputting a first signal to a second output terminal;

The signal of the third output terminal of the counter means of the preceding stage is input to the input terminal, and consists of a plurality of counter means for outputting the signal of the corresponding bit to the second output terminal.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a 3 bit down sync counter circuit diagram according to an embodiment of the present invention, FIG. 2 is a basic logic circuit diagram of a sync counter according to an embodiment of the present invention, and FIG. 3 is a 3 bit down sync counter according to an embodiment of the present invention. Fig. Is an operation timing diagram of the counter circuit.

Referring to FIG. 1, a configuration of an embodiment of the present invention is described with reference to a power supply Vcc connected to an input terminal D1 and a clock signal CKI,-to clock terminals C11, -C11, C31, and -C31. A first counter unit 10 to which CKI, CK3 and -CK3 are input to output the first bit output signal OUTO to the second output terminal Q11,

The input terminal D2 is connected to the third output terminal Q21 of the first counter unit 10 and the clock signals CKI, -CKI, CK3, and C2 are connected to the clock terminals C12, -C12, C32, and -C32. A second counter unit 20 for inputting CK3 to output the second bit output signal OUT1 to the second output terminal Q12;

An input terminal D3 is connected to the third output terminal Q22 of the second counter unit 30, and the clock signals CK1, -CK1, CK3, and C3 are connected to the clock terminals C13, -C13, C33, and -C33. -CK3) is input to the third output unit (30) for outputting the output signal OUT2 of the third bit to the second output terminal (Q13).

Since the first to third counter units 10 to 30 are all configured in the same configuration, the configuration of the first to third counter units 10 to 30 will be described with reference to FIG.

Inverter G1 to which input terminals D1 to D3 are connected, and an NOR gate G2 that is connected to an output terminal of the inverter G1 with one input terminal and outputs a second output signal 02 as an output terminal. ), AND gate G3 having one input terminal connected to an output terminal of the inverter G1, and a first input terminal connected to an output terminal of the NOR gate G2, and reset to a second input terminal. A NOR gate G4 having a signal R input and an output terminal of the AND gate G3 connected to a third input terminal, and an input terminal connected to an output terminal of the NOR gate G4, and having an inverted gate terminal. A first tri-state gate G5 to which clock signals CK1 and -CK1 are input to (-C1) and the gate terminal C1, and the first tri-state gate G5; The input terminal is connected to the output terminal of the output terminal and the clock signals CK3 and -CK3 are input to the inverting gate terminal (-C3) and the gate terminal C3. An inverter G7 connected to a second tri-state gate G6, an output terminal of the second tri-state gate G6, and outputting a second output signal Q1; and An input terminal is connected to an output terminal of the inverter G7 and the inverter G8 outputs the first output signal Q0, and an input terminal is connected to the output terminal of the second buffer G6. An inverter G9 having an output terminal connected to the other input terminal of G2) and the other input terminal of the AND gate G3.

The operation of the present invention made as described above is as follows.

First, the operation of the counters 10 to 30 used in the embodiment of the present invention is varied according to the state of the reset signal R as shown in Table 1 below.

That is, clock signals CK1, -CK1, CK3, and -CK3 applied to the gates and inverted gate terminals C1, -C1, C3, and -C3 of the first and second buffers G5 and G6 of FIG. When the signal input to the reset terminal R is H when the low level L is changed from the low level L to the high level H, the first to third output terminals 00 to 3 are independent of the state of the signal applied to the input terminal D. The state of the signal output to 02) maintains the value of OIO.

However, when the value of the reset terminal R is low level, the state of the signal output to the first to third output terminals Q0 to Q2 is not only the signal state input to the input terminal D but also the first output terminal. It varies depending on the state of the signal output to (Q0).

Accordingly, when the state of the signal applied to the reset terminal R is L, the state of the signal output to the first to third output terminals Q0 to Q2 is shown in Table 2 above.

Since the counters 10 to 30 operate as described above, the operation of the 3-bit synchronous counter circuit shown in FIG. 1 is as follows.

First, the power supply Vcc is connected to the input terminal D1 of the first counter unit 10, and the state of the signal applied to the reset terminal R1 is L which is low level after initializing at the high level.

In addition, the clock signals applied to the gate terminals C11 and C31 of the first and second tri-strip gates G6 and G6 of FIG. 2 and the clock signals applied to the inverting gate terminals -C11 and -C31 are inverted with each other. The clock signals CK1, -CK1, CK3, and -CK3 applied to the first tristate gate G5 and the second tristate gate G6 are maintained as shown in FIG. As shown in (b), a predetermined time delay is generated and input.

Therefore, as described above, the signal output to the first to third output terminals Q01, Q11, and Q21 of the first counter unit 10 is equal to 10 depending on the state of the clock signals CK1, -CK1, CKC3, and -CK3. Repeat 101.

As shown in FIG. 3A, clock signals CK1 and -CK1 applied to the gate terminal C11 and the inverted gate terminal -C11 of the first tri-state gate G5 are the second tri-state. A predetermined time is applied before the clock signals CK3 and -CK3 applied to the gate terminal C31 and the inverted gate terminal -C31 of the gate G6.

Therefore, the state of the output signal of the second tri-state gate G6 is independent of the output state of the first tri-state gate G5 until the clock signal CK3 as shown in FIG. 3B is applied. It becomes L state which is low level.

Therefore, the output signal of the third output terminal Q21 becomes L, which is a low level, and the signal state of the first to third output terminals Q01, Q11, and Q21 becomes ten.

However, as shown in FIG. 3B, when the clock signals CK3 and -CK3 having the corresponding state are applied to the gate terminal C31 and the inverted gate terminal -C31 of the second tri-state gate G6, the high level is applied. Since the output signal of the first tri-state gate G5 in a state is output via the second tri-state gate G6, the output states of the first to third output terminals Q01, Q11, and Q21 are all Inverted to the state of 101.

As described above, the clock terminals CK1 and CK3 applied to the gate terminals C1 and C3 of the first and second tri-state gates G5 and G6, which are applied as shown in FIG. In response to the signal, the first to third output terminals Q01, Q11, and Q21 of the first counter unit 10 repeat 10 and 101 as shown in (c)-(e) of FIG.

Therefore, the operations of the second and third counter parts 20 and 30 vary depending on the state of the output signals of the second output terminals Q21 and Q22 of the counter part of the front end.

According to the operation of the first counter unit 10, signals of the corresponding state are sequentially input to the input terminals D of the second and third counter units 20 and 30, and pulses of the clock signals CK1 and CK3 are applied. The signal output to the first to third output terminals Q02 to Q22 and Q03 to Q23 of the counter units 20 and 30 according to the state of the signal applied to each of the input terminals D2 and D3 each time is applied. The change in is as shown in (b) to (ka) in FIG.

Therefore, each time the clock signals CK1 and CK3 are applied, a signal that is counted down by one is output to each of the second output terminals Q11, Q12, and Q13 of the first to third counter units 10 to 30, and the down count is output. Execute the action.

On the contrary, in order to obtain a signal that is counted up by one each time the clock signal is applied, the first to third counter units 10 to 30 which maintain the inverted state with the signals of the second output terminals Q11, Q12, and Q13. By using the signals output from the one output terminal Q01, Q02, Q03, three-bit signals that increase sequentially can be obtained.

When using a simple basic logic circuit as described above to design a basic counter circuit capable of performing a count operation and to design a synchronous counting circuit of a desired bit, a transistor that is used when designing a count using a conventional flip flop Since the number of circuits can be significantly reduced, miniaturization of the product can be easily realized when the design area is reduced to form a single chip.

Claims (5)

N output signals including a first output terminal, a second output terminal, and a third output terminal are synchronized with an input terminal to which a power voltage is connected, a clock terminal to which a clock signal is input, a reset terminal to which a reset signal is input, and a clock signal. When the clock signal is changed from low level to high level, if the signal input to the reset terminal is high level, the signals output to the n output terminals are returned to a specific state regardless of the signal state applied to the input terminal. If the signal input to the reset terminal is at a low level, the signals output to the n output terminals are output to the n output terminals according to the input signal of the input terminal and the output signal of the first output terminal. Variable counter means; Of the n output terminals of the counter means, the second output terminal is an output signal of one bit, and the third output terminal is connected to an input terminal of a counter means connected next to the counter means, thereby And a plurality of counter means in which signals output to the n output terminals of the counter means connected next to the counter means are varied according to the output signal of the third output terminal. The inverter of claim 1, further comprising: an inverter (Gl) for inverting an input signal; One input terminal is connected to an output terminal of the inverter G1, and a NOR gate G2 for outputting a second output signal 02 as an output terminal, and one input terminal is connected to an output terminal of the inverter Gl. The AND gate G3; A NOR gate having a first input terminal connected to an output terminal of the NOR gate G2, a reset signal R being input to a second input terminal, and an output terminal of the AND gate G3 connected to a third input terminal ( G4) and; A first tri-state gate G5 having an input terminal connected to an output terminal of the NOR gate G4 and a clock signal being input to an inverting gate terminal and a gate terminal; A second tri-state gate G6 having an input terminal connected to an output terminal of the first tri-state gate G5 and a clock signal being input to the inverting gate terminal and the gate terminal; An inverter (G7) connected to an output terminal of the second tri-state gate (G6) and outputting a second output signal (01); An inverter G8 connected to an output terminal of the inverter G7 and outputting a first output signal Q0; Inverter G9 having an input terminal connected to an output terminal of the second tri-state gate G6 and an output terminal connected to the other input terminal of the NOR gate G2 and the other input terminal of the AND gate G3. Synchronous counter circuit, characterized in that consisting of. 3. The predetermined time period according to claim 2, wherein the clock signal is applied to the gate terminal of the first and second tri-state gates G5 and G6 and the clock signal is applied to the inverted gate terminal. A delay counter circuit, characterized in that a delay occurs. 2. The synchronization counter according to claim 1, wherein the down count operation can be executed by using an output signal of the first output terminal Q0 which maintains the state of the output signal of the second output terminal Q1 and the inverted state. Circuit. First inverting means for inverting an input signal, and first negative logic sum means connected with one input terminal to an output terminal of the inverter and outputting a second output signal to the output terminal; First logical multiplication means having one input terminal connected to an output terminal of the first reversing means; A first input terminal is connected to an output terminal of the first negative logic sum means, a reset signal is input to a second input terminal, and an output terminal of the first logical multiplication means is connected to a third input terminal and receives a third output signal. Second negative AND logic means for outputting; First buffer means connected to an output terminal of the second negative logic sum means and a clock signal is input to an inverted gate terminal and a gate terminal; A second buffer means having an input terminal connected to an output terminal of the first buffer means and a clock signal input to an inverted gate terminal and a gate terminal; Second inverting means connected to an output terminal of the second buffer means and outputting a second output signal Q1; Third inverting means connected to an output terminal of the second inverting means and outputting a first output signal Q0; An input terminal connected to an output terminal of the second buffer means and a fourth inverting means connected to an input terminal of the other side of the first negative logic unit and an input terminal of the other side of the first logical unit; Synchronous counter circuit.