KR0140701B1 - Nmos transistor using the multilevel poly gate - Google Patents

Nmos transistor using the multilevel poly gate

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Publication number
KR0140701B1
KR0140701B1 KR1019890012025A KR890012025A KR0140701B1 KR 0140701 B1 KR0140701 B1 KR 0140701B1 KR 1019890012025 A KR1019890012025 A KR 1019890012025A KR 890012025 A KR890012025 A KR 890012025A KR 0140701 B1 KR0140701 B1 KR 0140701B1
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South Korea
Prior art keywords
poly
gate
nmos transistor
oxide film
multilevel
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KR1019890012025A
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Korean (ko)
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KR910005479A (en
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황이연
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문정환
엘지반도체주식회사
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Priority to KR1019890012025A priority Critical patent/KR0140701B1/en
Publication of KR910005479A publication Critical patent/KR910005479A/en
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Publication of KR0140701B1 publication Critical patent/KR0140701B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용없음No content

Description

다층폴리 게이트를 이용한 NMOS 트랜지스터 제조방법NMOS transistor manufacturing method using multilayer poly gate

제 1도는 종래의 공정순서도1 is a conventional process flowchart

제 2도는 본 발명의 공정순서도2 is a process flow chart of the present invention

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10 : P형기판 20 : 산화막10: P-type substrate 20: oxide film

30 : 폴리 1 40 : 폴리 230: Poly 1 40: Poly 2

50 : 폴리 350: Poly 3

본 발명은 공정을 간단하게 개선시킨 다층폴리 게이트를 이용한 NMOS 트랜지스터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing an NMOS transistor using a multi-layer poly gate which is a simple improvement of the process.

종래의 측벽(SideWall)을 이용한 NMOS 트랜지스터의 공정은 제 1도에 도시된 바와같이 P형 실리콘 기판(10)위에 게이트 산화막(20)을 형성하고 폴리(poly)(70)를 디포지션(deposition) 하였으며 이후 (나)와 같이 폴리(70)를 포토 리지스트(photoresist)(이하에서 PR이라고 함)(60)를 이용한 사진식각 기술로 게이트 산화막(20) 및 폴리(70)를 패터닝하여 게이트를 형성한후 N-이온 주입한다.A conventional process of an NMOS transistor using sidewalls (SideWall) forms a gate oxide film 20 on a P-type silicon substrate 10 and deposits a poly 70 as shown in FIG. After that, the gate is formed by patterning the gate oxide layer 20 and the poly 70 using a photolithography technique using a poly 70 as a photoresist (hereinafter referred to as PR) 60 as shown in (b). N-ion is then injected.

(다)와 같이전면에 저온산화막을 증착하고 건식식각하여 측벽(80)을 형성하고 최종적으로N+이온을 주입하여 서서히 식힘으로 (라)와 같이 N+영역과 N-로 된 소오스/드레인영역을 형성하였다.As shown in (C), a low-temperature oxide film is deposited on the front surface and dry-etched to form sidewalls 80, and finally, N + ions are injected to gradually cool to form N + regions and N-source / drain regions as shown in (D). It was.

상기의 (라)와 같은 구조에서 NMOS의 동작은 체널끝에서의 N-영역(도핑농도가 다소 낮은 영역)에 의해 높은 전장을 감소시켜 항복전압을 향상시키는 한편 고전장영역은 N-영역을 지나 N+영역내에 존재하게 되어 열전자의 트랩(trap)이 게이트 가장자리에서 일어나게 되므로 수행능력을 개선시킬수 있었다.In the structure as described above, the operation of NMOS reduces the high electric field by the N-region (a somewhat low doping concentration) at the channel end to improve the breakdown voltage, while the high-field region passes through the N-region to N +. The presence in the region allows traps of hot electrons to occur at the gate edge, improving performance.

그러나, 상기한 바와같은 종래의 제조방법은 측벽(80)을 형성하기 위한 공정이 복잡하고 상당히 까다롭게 때문에 제조하기가 매우 어려운 결점이 있었다.However, the conventional manufacturing method as described above has a drawback that is very difficult to manufacture because the process for forming the side wall 80 is complicated and considerably difficult.

본 발명은 이와같은 종래의 결점을 감안하여 안출한 것으로 이를 첨부된 도면 제 2도에 의하여 상세히 설명하면 다음과 같다.The present invention has been made in view of the above-mentioned conventional drawbacks and will be described in detail with reference to FIG.

본 발명은 먼저(가)와 같이 P형 기판(10)위에 게이트 산화막(20)을 형성하고 이 산화막(20)위에 그레인(grain) 크기가 작은 폴리 1(30), 그 다음 그레인 크기가 큰 폴리 2(40), 및 그레 인 크기가 가장 큰 폴리 3(50)를 차례로 형성시킨다.According to the present invention, as shown in (a), a gate oxide film 20 is formed on a P-type substrate 10, and a grain 1 having a small grain size is formed on the oxide film 20, and then a poly having a large grain size. 2 (40), and poly (50) with the largest grain size are formed in turn.

(나)와 같이 PR(60)을 이용한 사진식각 기술로 상기 폴리 1,2,3를 식각한다.The poly 1,2,3 is etched by the photolithography technique using the PR 60 as shown in (b).

이때, 폴리는 그레인 크기가 폴리 3(50) 폴리 2(40) 폴리1(30)이라 할 때 에치율의 크기는 폴리3(50) 폴리2(40) 폴리 1(30)이 되어 에치후의 단면은 (나)와 같이 된다.In this case, when the grain size is poly 3 (50) poly 2 (40) poly 1 (30), the size of the etch rate is poly 3 (50), poly 2 (40) poly 1 (30), and the cross section Becomes like (B).

이후, 상기 게이트전극으로 패터닝된 폴리 1,2,3을 마스크로 이용하여 N+이온을 주입하게 되면(다)와 같은 구조를 얻게 된다.Subsequently, when N + ions are implanted using poly 1,2,3 patterned as the gate electrode as a mask, the structure is obtained (C).

상기와 같은 본 발명의 다층폴리 NMOS 트랜지스터의 동작은 채널끝에서의 도핑농도가 낮은 N-영역에 의해 높은 전장을 감소시킬수 있어 항복전압을 향상시키고 고전장 영역은 형성이 N-영역을 지나 N+ 영역내에 존재하게 되므로 열전자의 트랩이 게이트 가장자리에서 일어나게 되어 수행능력이 개선되는 것이다.The operation of the multi-layer poly NMOS transistor of the present invention as described above can reduce the high electric field by the N-region with low doping concentration at the channel end, thereby improving breakdown voltage, and the high-field region is formed in the N + region through the N- region. The presence of a trap of hot electrons occurs at the gate edge, improving performance.

이상과 같은 본 발명은 종래와 같이 측벽을 형성하기 위한 복잡한 과정을 거치지 않고도 다층폴리 게이트에서 폴리의 에치율을 이용하여 NMOS 트랜지스터를 제조하므로 종래에 비해 제조공정이 간단해지고 이에 따라 원가절감을 가져올수 있는 효과가 있다.As described above, the present invention manufactures an NMOS transistor using poly etch rate in a multi-layer poly gate without having to go through a complicated process of forming sidewalls as in the prior art, thereby simplifying the manufacturing process and thus reducing costs. It has an effect.

Claims (2)

(정정) P형 기판(10)위에 게이트 산화막(20)을 형성하고 이 산화막(20)위에 그레인 크기가 작은 순서로 폴리 1(30), 폴리 2(40), 폴리 3(50)을 형성하는 공정과, 게이트영역을 정의하여 상기 폴리 1,2,3층과 게이트 산화막(20)을 계단모양으로 식각하여 게이트전극을 형성하는 공정과,(Correction) A gate oxide film 20 is formed on a P-type substrate 10, and poly 1 (30), poly 2 (40), and poly 3 (50) are formed on the oxide film 20 in the order of smallest grain size. Forming a gate electrode by defining a gate region to etch the poly 1,2,3 layer and the gate oxide film 20 in a step shape; 상기 계단형 게이트전극을 마스크로 하여 N+이온 주입하여 소오스/드레인영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 다층폴리 게이트를 이용한 NMOS 트랜지스터 제조방법.And forming a source / drain region by implanting N + ions using the stepped gate electrode as a mask. (정정) 제 1항에 있어서,(Correction) The method of claim 1, 계단형의 게이트전극에 의해 소오스/드레인영역이 N+영역과 N-영역으로 형성되게 함을 특징으로 하는 다층폴리 게이트를 이용한 NMOS 트랜지스터 제조방법.A method for fabricating an NMOS transistor using a multilayer poly gate, characterized in that the source / drain regions are formed into N + regions and N − regions by stepped gate electrodes.
KR1019890012025A 1989-08-23 1989-08-23 Nmos transistor using the multilevel poly gate KR0140701B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890012025A KR0140701B1 (en) 1989-08-23 1989-08-23 Nmos transistor using the multilevel poly gate

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Application Number Priority Date Filing Date Title
KR1019890012025A KR0140701B1 (en) 1989-08-23 1989-08-23 Nmos transistor using the multilevel poly gate

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KR910005479A KR910005479A (en) 1991-03-30
KR0140701B1 true KR0140701B1 (en) 1998-06-01

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