KR0139151B1 - Signal processing apparatus and method of l.c.d projector - Google Patents

Abstract

According to the present invention, the sampling time of the image signal supplied to the liquid crystal signal electrode is changed according to the even / odd field or the even / odd performance to eliminate the deterioration of image quality that appears on the screen and to obtain a natural screen. An apparatus and a method thereof are provided. The present invention makes a horizontal clock signal using a phase-locked loop circuit and a divider circuit, and counts the horizontal clock signal in a CKH / STH decoder to produce first and second start clock signals that differ by 1/2 pixel. do. The switching unit selectively supplies one of the two start clock signals to the sample / hold driver according to the output signals of the field and the line determination unit. When the video signal is an odd field, the switching unit always samples at a certain point of time, and in the even field, the start clock. By changing the signal, the even row video signal and the odd row video signal are sampled at different time points by 1/2 pixel. Therefore, the image quality can be improved.

Description

Signal processing device and method of liquid crystal projector

Figure 1 is an embodiment of a screen reproduction state according to the prior art.

2 is another embodiment of a screen reproduction state according to the prior art.

3 is a block diagram of a signal processing device of a liquid crystal projector according to the prior art.

4 is a screen reproduction state diagram of the radix field city according to the present invention.

5 is a screen reproduction state diagram of the excellent field city according to the present invention.

6 is an actual screen reproduction state diagram according to the present invention.

FIG. 7 is a block diagram showing a signal processing device of the liquid crystal projector of the present invention for reproducing a screen as shown in FIG.

8 is a timing diagram showing clock signal waveforms and sampling time points according to fields and lines of an image signal.

Explanation of symbols on the main parts of the drawings

1, 11: phase comparator 3, 13: voltage controlled oscillator

4, 14, 20: division circuit 5, 50: switching unit

10: phase locked loop circuit 30: CKH / STH decoder

40: field and line judgment

According to the present invention, when the pixel structure of the liquid crystal display panel is delta type, the sampling time of the image signal supplied to the liquid crystal signal electrode is changed according to the even / odd number field and the row, thereby eliminating the deterioration of the image quality that appears in the form of irregularities on the screen. The present invention relates to a signal processing device for a liquid crystal projector and a method thereof.

In general, in a television or a projector using a liquid crystal display panel, the pixel structure of the liquid crystal display panel has a delta pixel array (triangle structure). Appears and the picture quality deteriorates.

FIG. 1 is a view illustrating a screen reproduction state according to the prior art, in which an image signal input to a signal electrode of a liquid crystal display panel is always sampled at a certain time regardless of whether it is a good row or an odd row. Here, a sample / hold driver is connected to a source line of the liquid crystal display panel, and a clock signal applied to the sample / hold driver, that is, a horizontal clock signal (CKH) and a start clock signal (Start Horizontal) ; STH) can be adjusted to adjust the sampling time of the video signal. As shown in FIG. 1, the pixel structure of the liquid crystal display panel has a good row and odd row deviated by 1/2 pixel so that the image signal supplied thereto is generated at the same time for the good row and the odd row. When flinging, irregularities appear on the vertical line and the inclined surface of the screen. Therefore, the uneven part becomes annoying to the user, and in the case of the large screen, this phenomenon is more pronounced, and there is a problem in that the image quality is lowered.

FIG. 2 is another embodiment of a screen reproduction state according to the prior art, and is intended to solve the problem of vertical smoothness and inclined surfaces occurring in the pixel structure itself of the liquid crystal display panel as described above. This is a case where the sampling time of the even row video signal is sampled 1/2 pixel earlier than the odd row by controlling the phase of the horizontal clock signal or the start clock signal applied to the sample / hold driver of the liquid crystal display panel.

3 is a block diagram showing a signal processing apparatus of a conventional liquid crystal projector for reproducing a screen as shown in FIG. As shown, the low pass filter 2 is provided at the output of the phase comparator 1 which detects the phase difference between the two signals by comparing the input horizontal clock signal CKH with the phase of the signal fed back from the division circuit 4. The low pass filter 2 removes unnecessary components from the input signal and outputs a signal for the phase difference between the two signals. The frequency divider circuit 4 is connected between the output terminal of the voltage controlled oscillator 3 and the phase comparator 1 whose oscillation frequency is varied according to the output voltage of the low pass filter 2, and the frequency divider circuit 4 A signal obtained by dividing the output signal of the control oscillator 3 at a predetermined ratio is fed back to the phase comparator 1. Two horizontal clock signals having a phase difference output from the division circuit 4 are applied to the switching unit 5, and one of the horizontal clock signals is applied to the STH compensator 6. The switching unit 5 is switched according to the even row switching signal to select one of the two horizontal clock signals and supply the selected signal to the sample / hold driver. The STH compensator 6 divides the horizontal clock signal applied from the frequency divider circuit and supplies the start clock signal STH to the sample / hold driver.

In the conventional circuit configured as described above, when the horizontal clock signal CKH and the feedback signal from the frequency dividing circuit 4 are input to the phase comparator 1, the phase comparator 1 detects the phase difference between the two signals and the low pass filter 2 ) The control signal from which unnecessary components are removed from the low pass filter 2 is applied to the voltage controlled oscillator 3, and when the input horizontal clock signal CKH and the divided signal have the same phase, the control signal becomes zero. When a phase difference between the input signal and the divided signal occurs, a DC voltage according to the phase difference is applied to the voltage controlled oscillator 3. The voltage controlled oscillator 3 varies the oscillation frequency, that is, the frequency of the output signal in proportion to the input DC voltage, and the signal output from the voltage controlled oscillator 3 is applied to the frequency divider circuit 4 and divided at a set ratio. . The generated horizontal clock signal is fed back to the phase comparator 1 and compared with the input horizontal clock signal CKH.

On the other hand, the frequency divider circuit 4 generates two types of horizontal clock signals having different phases. One of the horizontal clock signals output from the frequency divider circuit 4 is applied to the STH compensator 6 to start the clock signal. Used to create (STH). The good row switching signal for controlling the switching operation of the switching unit 5 changes the state of the signal every time the row is changed, and according to this good row switching signal, the switching unit 5 selects one of the two horizontal clock signals. The signal is selected and output to the sample / hold driver. Here, the horizontal synchronization signal and the vertical synchronization signal are used to determine whether the current image signal applied to the signal electrode of the liquid crystal display panel is an even row or an odd row, and the state of the even row switching signal is determined according to the determination result. In addition, the STH compensator 6 supplies a start clock signal STH generated by dividing the horizontal clock signal applied from the division circuit 4 to the sample / hold driver. Therefore, the start clock signal STH is the same signal irrespective of the even row or odd row, and the horizontal clock signal CKH is applied to the sample / hold driver with a different phase signal each time the row is changed so that the even row video signal. Will be sampled 1/2 pixel earlier than the base row.

As described above, when the sampling time of the image signal input to the signal electrode of the liquid crystal display panel is different from the even row and the odd row, the inclined plane appears smoothly on the screen. However, in the case of the vertical line, as shown in the exemplary embodiment, the uneven shape appears as it is, in fact, only the position of the pixel is changed and there is a problem in that the image quality improvement effect is not greatly felt.

The present invention is to solve the above-mentioned problems, the object of the present invention is to change the sampling time of the image signal supplied to the signal electrode of the liquid crystal display panel according to the field and rain or odd performance irregularities on the screen The present invention provides a signal processing device and a method of a liquid crystal projector capable of eliminating the phenomenon and improving image quality.

It is another object of the present invention to improve a problem that vertical lines and inclined surfaces are not smooth due to the delta type pixel structure of the liquid crystal display panel, and thus, a signal processing device of the liquid crystal projector and a method thereof so as to obtain a natural screen unobtrusive to the user. To provide.

The signal processing apparatus of the liquid crystal projector of the present invention for achieving the above object is provided with a phase synchronization loop circuit for generating a clock signal of a predetermined frequency synchronized with the horizontal synchronization signal of the video signal. The clock signal output from the phase-locked loop circuit is applied to the divider circuit, and the divider circuit divides the input signal at a predetermined ratio to form a horizontal clock signal to be supplied to the sample / hold driver. The CKH / STH decoder counts the horizontal clock signal applied from the dividing circuit using the vertical synchronization signal to generate the first and second start clock signals that differ by 1/2 pixel for each horizontal scanning period, and output them to the switching unit. A field connected to the output terminal of the field judgment unit and a field determining whether the video signal currently inputted using the horizontal synchronization signal and the vertical synchronization signal is an excellent / odd field or an excellent / executive performance. The start signal is applied from the CKH / STH decoder. One signal is selected and fed to the sample / hold driver.

In addition, the signal processing method of the liquid crystal projector of the present invention for achieving the above object is the step of determining whether the video signal is even field or odd field, and whether it is even row or odd row, and the field of the determined video signal and The step of determining the sampling time of the video signal by selectively supplying one of the two start clock signal differs by a predetermined phase along the line. Thus, the video signal is always sampled at a certain point in time, and if the video signal is an even field, the start clock signal applied to the sample / hold driver is changed so that the good row signal and the odd row video signal differ by 1/2 pixel. Will be sampled.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 8 as follows. 4 shows a screen reproduction state in the case of the odd field according to the present invention. The image signal input to the signal electrode of the liquid crystal display panel is always sampled at a certain time point regardless of whether it is an even row or an odd row. Since the pixel structure of the liquid crystal display panel has a deviation of the even row and the odd row as much as 1/2 pixel, when the even row and the odd row image signals are sampled at the same time, irregularities appear on the vertical line and the slope of the screen.

5 is a diagram illustrating a screen reproduction state in the case of an even field according to the present invention. The timing of start clock signals applied to a sample / hold driver of a liquid crystal display panel is controlled to determine the sampling time of even and odd row image signals. It's as different as 2 pixels. As described above, when the sampling time of the image signal is changed to compensate for misalignment of 1/2 pixel with respect to the even row, the inclined plane appears smooth, but since the even row is shifted to the left by 1/2 pixel, irregularities appear on the vertical line.

FIG. 6 shows the actual screen reproduction state according to the present invention, which is a result of combining the radix field screen and the even field screen. Since a complete screen is actually reproduced by two fields, the radix field screen and the even field screen are displayed. It is possible to obtain a natural screen as shown by combining.

FIG. 7 is an exemplary circuit diagram for reproducing a screen as shown in FIG. 6, and is a block diagram showing the configuration of the signal processing apparatus of the liquid crystal projector of the present invention. As shown, a low pass filter 12 is provided at an output of the phase comparator 11 which detects the phase difference between the two signals by comparing the input horizontal synchronization signal H with the phase of the signal fed back from the frequency divider 14. The low pass filter 12 removes unnecessary components from the input signal and outputs a signal for the phase difference between the two signals. The frequency divider circuit 14 is connected between the output terminal of the voltage controlled oscillator 13 and the phase comparator 11 whose oscillation frequency is varied according to the output voltage of the low pass filter 12, and the frequency divider circuit 14 The output signal of the control oscillator 13 is divided by 1 / N times and fed back to the phase comparator 11. The phase synchronous loop circuit 10 configured as described above generates a clock signal synchronized with the horizontal synchronous signal H of the video signal.

The clock signal output from the voltage controlled oscillator 13 is applied to the division circuit 20, and the division circuit 20 divides the input signal by 1 / M times to generate a horizontal clock signal CKH. The CKH / STH decoder 30 connected to the output terminal of the dividing circuit 20 receives the vertical synchronizing signal V and counts the horizontal clock signal CKH applied from the dividing circuit 20 so that the horizontal clock signal CKH is 1 / every horizontal scanning period. Two start clock signals STH1 and STH2 that differ by two pixels are generated and output to the switching unit 5. In addition, the horizontal clock signal CKH output from the CKH / STH decoder 30 is applied to the sample / hold driver. On the other hand, the signal processing apparatus of the present invention determines whether the video signal currently input to the liquid crystal signal electrode is an even field or an odd field by using the input horizontal synchronous signal H and the vertical synchronous signal V. The switching unit 5 connected to the output terminal of the field determining unit 40 and the field determining unit 40 determines whether or not the driving is performed. The two start clock signals STH1 and STH2 are switched according to the output signals of the field and line determining unit 40. One signal is selected and applied to the sample / hold driver.

When the horizontal synchronizing signal (H) and the vertical synchronizing signal (V) are input to the signal processing apparatus of the present invention configured as described above, the phase comparator 11 feeds back from the horizontal synchronizing signal (H) and the division circuit (14). The phase difference of the received signal is detected and output to the low pass filter 12. The control signal from which the unnecessary components are removed from the low pass filter 12 is applied to the voltage controlled oscillator 13, and when the input horizontal synchronous signal H and the divided signal have the same phase, the control signal becomes zero. When a phase difference between the input signal and the divided signal occurs, a DC voltage according to the phase difference is applied to the voltage controlled oscillator 13. The voltage controlled oscillator 13 varies the oscillation frequency in proportion to the input DC voltage, and the signals output from the voltage controlled oscillator 13 are applied to the frequency divider circuits 14 and 20, respectively. The division circuit 14 divides the clock signal oscillated and output from the voltage controlled oscillator 13 by 1 / N times and returns it to the phase comparator 11, and the returned signal is compared with the input horizontal synchronizing signal H again. .

The phase synchronous loop circuit 10 operating as described above generates a clock signal of a predetermined frequency synchronized with the horizontal synchronous signal H of the image signal, wherein the voltage controlled oscillator ( The oscillation frequency of 13) is determined. The clock signal output from the voltage controlled oscillator 13 is applied to the frequency divider circuit 20, where it is divided by 1 / M times to generate the horizontal clock signal CKH actually required. The horizontal clock signal CKH and the vertical synchronization signal V output from the division circuit 20 are input to the CKH / STH decoder 30, and the CKH / STH decoder 30 is the horizontal clock signal CKH. Counts to generate a start clock signal for each horizontal scanning period. At this time, two start clock signals STH1 and STH2 are output to the switching unit 5 so as to deviate by 1/2 pixel from each other. In addition, the horizontal clock signal CKH output from the CKH / STH decoder 30 is applied to the sample / hold driver.

On the other hand, the field and line determiner 40 determines whether the video signal input to the signal electrode of the ubiquitous liquid crystal display panel is an even field or an odd field using the input horizontal synchronous signal H and the vertical synchronous signal V. In addition, it is determined whether it is an excellent row or an odd row. If the input video signal is an odd field, a high potential signal is output regardless of whether it is even row or odd row. If the input video signal is an even field, high potential signal is used if it is odd row. Output low potential signals, respectively. The output signal of the field and line determination unit 40 is applied to the control terminal of the switching unit 5, and the switching unit 5 selects the start clock signal STH1 among the two input signals when the control signal has a high potential. When the control signal is low potential, another start clock signal STH2 is selected and supplied to the sample / hold driver.

8 is a timing diagram showing clock signal waveforms CKH, STH1, and STH2 waveforms and sampling time points corresponding to fields and lines of an image signal. The sampling time is determined by the horizontal clock signal CKH and the start clock signals STH1 and STH2 supplied to the signal electrode of the liquid crystal display panel. 8A is a clock signal waveform and a sampling timing diagram supplied to a sample / hold driver when an image signal is an odd field or an odd row, and sampling time is determined by the horizontal clock signal CKH and the start clock signal STH1. Is determined. (B) of FIG. 8 is a clock signal waveform and sampling timing diagram when the video signal is an even field and even row, and FIG. 8 (c) is a clock signal waveform and sampling timing diagram when an image signal is an even field and even row. As a result, the sampling time point is determined by the horizontal clock signal CKH and the start clock signal STH1. (D) of FIG. 8 is a clock signal waveform and sampling timing diagram when the video signal is the even field and the even row, and the same horizontal clock signal (CKH) and start clock signal ((c) as shown in (a) to (c) of FIG. Since the sampling time is determined by the start clock signal CKH2 that is 1/2 pixel ahead of STH1), the video signal is sampled earlier than in the case described above.

As described above, the present invention changes the start clock signal supplied to the sample / hold driver of the liquid crystal panel to change the sampling time of the image signal input to the signal electrode according to the even / odd field and the even / odd. Due to the pixel structure, irregularities appear on the screen. Therefore, the image quality can be improved, and the vertical lines and the inclined planes appear smoothly, so that a natural screen that is unobtrusive to the user can be obtained.

Claims (9)

In the signal processing apparatus of the liquid crystal display panel, the sampling time of the image signal input to the signal electrode of the liquid crystal display panel is varied by varying the clock signal applied to the sample / hold driver. A phase synchronous loop circuit for generating a clock signal of a predetermined frequency synchronized with the horizontal synchronous signal of the video signal; A divider circuit for dividing the clock signal output from the phase locked loop circuit at a predetermined ratio to produce a horizontal clock signal to be supplied to the sample / hold driver; A CKH / STH decoder for generating a first and second start clock signal which is less than 1/2 pixel per horizontal scanning period by counting the horizontal clock signal applied from the division circuit using the vertical synchronization signal; A field and line judging unit determining whether an image signal currently inputted is an even / odd field or an even / executive performance using a horizontal synchronous signal and a vertical synchronous signal; Signal processing of the liquid crystal projector characterized in that it comprises a switching unit is selected according to the output signal of the field and line determination unit and selects one signal from the two start clock signal applied from the CKH / STH decoder to supply to the sample / hold driver Device. 2. The apparatus of claim 1, wherein the phase synchronization loop circuit comprises: a phase comparator for detecting a phase difference between the two signals by comparing a phase of an input horizontal synchronization signal with a signal fed back from the division circuit; A low pass filter for removing unnecessary components from the output signal of the phase comparator and outputting a signal for the phase difference between the two signals; A voltage controlled oscillator for varying the oscillation frequency in proportion to the output voltage of the low pass filter; A signal processing device for a liquid crystal projector comprising: a division circuit for dividing an oscillation output signal from a voltage controlled oscillator at a constant ratio and feeding it back to a phase comparator. 2. The switching unit of claim 1, wherein the switching unit outputs a zestart clock signal to a sample / hold driver when the video signal is an odd field or an odd row, and is output by a horizontal synchronization signal output from a CKH / STH decoder and the first start clock signal. A signal processing apparatus of a liquid crystal projector characterized in that the sampling time of the image signal is determined. According to claim 1, wherein the switching unit outputs the first start clock signal to the sample / hold driver when the video signal is the odd field and even row to the horizontal clock signal and the first start clock signal output from the CKH / STH decoder And a sampling time point of the image signal is determined by the liquid crystal projector. According to claim 1, wherein the switching unit outputs the first start clock signal to the sample / hold driver when the video signal is an even field and odd run to the horizontal clock signal and the first start clock signal output from the CKH / STH decoder And a sampling time point of the image signal is determined by the liquid crystal projector. The method of claim 1, wherein the switching unit outputs a second start clock signal to the sample / hold driver when the video signal is an even field or odd run, and is in phase with the horizontal clock signal and the first start clock signal output from the CKH / STH decoder. A signal processing device for a liquid crystal projector, characterized in that the sampling time point of the video signal is determined by the second start clock signal advanced by 1/2 pixel. A signal processing method of a liquid crystal display panel in which a sampling time of an image signal input to a signal electrode of a liquid crystal display panel is varied by varying a clock signal applied to a sample / hold driver. Creating two horizontal clock signals to be supplied to the sample / hold driver and two start clock signals different from each other by a predetermined phase; Determining whether the video signal is an even field or an odd field and determining whether it is an outer even row or an odd row; And selectively supplying one of the two start clock signals according to the determined field and line of the image signal to determine a sampling time point of the image signal. 8. The liquid crystal projector signal processing method according to claim 7, wherein the video signal is always sampled at a certain point in time regardless of whether it is an even row or an odd row. 8. The method of claim 7, wherein when the video signal is an even field, the start clock signal applied to the sample / hold driver is changed to sample the even row video signal and the odd row video signal at different time points by 1/2 pixel. A signal processing method for a liquid crystal projector.