KR0137989B1 - Sense amplifier driving circuit - Google Patents

Abstract

The present invention reduces the noise generated in the sensing process by shifting the phase of the maximum instantaneous current flowing inside the memory device by adjusting the operation order of the PMOS latch and the NMOS latch in driving the array of the sense amplifier of the memory device. In order to provide a driving circuit, the sensing amplifier driving circuit includes a memory block including a plurality of memory cell arrays, a first sensing amplifier group for sensing and amplifying data on bit lines corresponding to one half of the memory block; A first driving unit for driving the operating power to be supplied to the first sense amplifier group, first switching means for switching a first power voltage to be supplied to the first sense amplifier group, and a first sense amplifier group Second switching means for switching the second power supply voltage to be supplied, and a ratio corresponding to the remaining half of the memory block; Switching a second sense amplifier block for sensing and amplifying data on the lines, a second driver for operating power to be supplied to the second sense amplifier group, and a first power voltage to be supplied to the second sense amplifier group And a third switching means for switching the second power supply voltage to be supplied to the second sense amplifier group.

Description

Sense Amplifier Drive Circuit

1 is a conventional sense amplifier circuit diagram.

2 is a conventional sense amplifier array driving circuit diagram.

3 is a diagram illustrating a branch amplifier driving circuit and a principle of minimizing current movement according to the first embodiment.

4 is a timing diagram of a drive signal applied to a sense amplifier driving circuit.

5 is a layout view of a drive signal unit.

6 is a sense amplifier driving circuit diagram according to a second embodiment of the present invention.

7 is a sense amplifier driving circuit diagram according to a third embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: precharge part 20: amplification part

30: output unit 40: input unit

50: first drive unit 60: second drive unit

12, 32, 21, 22: input lines 42, 44: control lines

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a driving circuit of a sense amplifier capable of amplifying a memory cell data transmitted on a bit line and quickly reading the memory cell. Particularly, a plurality of sense amplifiers simultaneously operate. A driving circuit of a sense amplifier reduces noise generated.

In the process of amplifying and reading memory cell data transmitted in a conventional bit line, a large amount of current flows instantaneously into the sense amplifier array due to the operation of several sense amplifiers, causing noise throughout the memory device. I had a problem.

1 shows a sense amplifier circuit diagram in a general case.

The sense amplifier includes an input unit 40 for inputting a signal from a memory cell (not shown), an amplifier 20 for amplifying and outputting a signal from the input unit 40, and the sense amplifier operates. Before this, the precharge section 10 which maintains the voltage level at [(1/2) Vcc] and the line 23 (hereinafter, RTO) which supplies the first power supply voltage Vcc to the inside of the circuit are described. And a line 24 for supplying the second power supply voltage Vss (hereinafter, SN).

The input unit 40 includes MOS transistors S1, S2, S3, and S4 for switching signals from the memory cells, and control lines 42 and 44 for controlling the operation of the MOS transistors by inputting signals from the outside. ) Was composed.

The signal from the memory cell is input via the MOS transistors S1 and S2 or through the MOS transistors S3 and S4.

Thus, two memory cell arrays share one sense amplifier.

The amplifying unit 20 amplifies the bit lines L1 and L2 for inputting and outputting signals from memory cells to the outside, and amplifies the signals from the bit lines L1 and L2 to the bit lines L1 and L2. It includes NMOS LATCH and PMOS LATCH to be output.

In the case where a low level signal is input from the memory cell to the authentic bit line L1, and a high level signal is input to the complementary bit line L2, the PMOS transistor. (Q5, Q6) operates to output the high level signal amplified by the RTO 23 to the complementary bit line L2 and the low level signal amplified by the SN 24 to the authentic bit line L1.

The precharge unit 10 includes an input line 12 for inputting a signal from BIT LINE EQUALIZATION (not shown), and three yen for inputting a signal from the input line 12. The MOS transistors Q1, Q2, and Q3 are included.

In the time domain in which the sense amplifier does not operate, since the high level signal from the outside is applied to the BLEQ 12, the MOS transistors Q1, Q2, Q3 operate to the node N1 [(1/2) Vcc] is output.

In the time domain, the potentials of the bit lines L1 and L2, which are the same as those of the internode N1, are held at [(1/2) Vcc].

In the time domain in which the sense amplifier does not operate, the RTO 23 and the SN 24 maintain a precharge state at [(1/2 Vcc) by external control.

The sense amplifier further includes an output unit 30 for inputting the amplified signals from the bit lines L1 and L2 and outputting them to the data bus line 34.

The output unit 30 has an input line 32 for inputting an output from a decoder (not shown), and a signal from the amplifying unit 20 by a signal on the input line. And the MOS transistors Q8 and Q9 to be transmitted.

A typical memory device drives the array ARRAY of the sense amplifier described above to increase the efficiency by sensing data in the memory array.

2 is a driving circuit of a conventional sense amplifier array, and as shown in FIG. 2, a power supply line RTO 23 and SN 24 and a PMOS for driving the RTO 23 and SN 24. Transistors Q1 and NMOS transistor Q2, input lines 21 and 22 for inputting signals driving PMOS transistor Q1 and NMOS transistor Q2, and N sense amplifiers SA. A sense amplifier array SAi (1 ≦ i ≦ n) and a memory cell array.

A signal from the memory cell array is applied, a low logic signal is applied to the PMOS transistor Q1 from the outside, and a high logic signal is applied to the NMOS transistor Q2.

At this time, a high logic signal such as the first power supply voltage Vcc is applied to the RTO 23 by a first power supply voltage Vcc, and a low logic signal such as a second power supply voltage Vcc is applied to the RTO 23. do.

However, in the conventional sense amplifier driving circuit, when the potential of the RTO 23 is induced to the first power supply voltage Vcc and the potential of the SN 24 to the second power supply voltage Vss, the authenticity of the RTO 23 is true. As a large amount of current flows instantaneously to the bit line of the bit line and the complement bit line, and from the above bit line and the complement bit line to the SN 24, the operation of the memory element is caused. Will adversely affect.

In the case of the conventional driving method for improving this, referring to FIG. 2 and FIG. 4A, a signal RTOE for driving the PMOS transistor Q1 from the outside is used to determine the NMOS transistor Q2. By adjusting the activation time of the driving signal SNE (the time it takes to change from logic low to logic high or the time it takes to change from logic high to logic low), the maximum instantaneous current flowing inside the memory element at the time of sensing data is too high. Adjust so that it does not grow.

However, as shown in FIG. 4A, when the activation time of the driving signals RTOE and SNE becomes long, the detection speed is slowed, and thus a trade-off between the maximum instantaneous current and the detection speed is required.

Therefore, the conventional sense amplifier driving method has a limitation in reducing the maximum instantaneous current flowing in the memory device.

Accordingly, an object of the present invention is to provide a sense amplifier driving circuit which reduces the noise generated during the sensing process while maintaining the detection speed of the sense amplifier fast.

In order to achieve the above object, the present invention provides a memory block comprising a plurality of memory cell arrays having a plurality of bit lines; A first sense amplifier group for sensing and amplifying data on bit lines corresponding to one half of the memory block; A first driver for driving operation power to be supplied to the first sense amplifier group; Second switching means for switching a second power supply voltage to be supplied to said first sense amplifier group; A second sense amplifier block for sensing and amplifying data on bit lines corresponding to the other half of the memory block; A second driver for driving operation power to be supplied to the second sense amplifier group; Third switching means for switching a first power supply voltage to be supplied to said second sense amplifier group; And a fourth switching means for switching the second power supply voltage to be supplied to the second sense amplifier group.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A includes a sense amplifier array and a first driver 10 and a second driver 20 for driving the same.

The first driver 50 includes an RTO 54 and an SN 56, and an RTO driver 52 and an SN driver 56 for driving the RTO 54 and the SN 56.

The second driver 60 may include an RTO 64 and an SN 68 and an activation signal RTOE1 of the RTO driver 62 and the SN driver 66 that drives the RTO 64 and the SN 66. The activation signal SNE2 of the SN driver 66 of the second driver 60 is first activated, and then the activation signal RTOE2 of the RTO driver 62 of the second driver 60 and the SN driver of the first driver 50 are activated. The activation signal SNE1 of 56 is activated later.

When the sense amplifier array is driven in this manner, the current 11 flowing through the RTO driver 52 of the first driver 50 and the current flowing through the TRO driver 62 of the second driver 60 as shown in FIG. 3B. There is a phase difference between (13).

Similarly, a phase difference is generated between the current 12 flowing in the SN driver 56 of the first driver 50 and the current 14 flowing in the SN driver 66 of the second driver 60, which flows into the memory device. Maximum instantaneous current will be significantly reduced.

In addition, the current flowing directly from the first power supply voltage Vcc to the second power supply voltage Vcc is also reduced, thereby reducing the total amount of current consumption.

However, in the sense amplifier driving method of the present invention, in the case of a driving unit in which the Phumus transistor operates first, a problem is that the sensing speed is slower than that of the remaining driving unit in which the NMOS transistor operates first, which adjusts the channel width of the MOS transistor. Alternatively, by adjusting the active time of the control signal, the same detection speed as the conventional driving method can be obtained.

4B to 4D are timing diagrams of driving signals applicable to the present invention.

5A and 5B are block diagrams showing the arrangement of NMOS transistors and PMOS transistors for driving the RTO 54, 64 and the SN 58, 68 of FIG.

The transistors may be disposed on the left and right sides of the sense amplifier array, respectively, as shown in FIG. 5A, or above and below the sense amplifier array, respectively, as shown in FIG. 5B.

FIG. 6 is a concept in which the PMOS transistor inducing the RTOs 54 and 64 of FIG. 3A is replaced with an NMOS transistor in the present invention, and the layout area of the memory element is reduced by using only the NMOS transistor. You can.

However, at this time, since the driving signal of the NMOS transistor is at a high level and the potential difference with the RTO is small, the driving signal of the NMOS does not play a sufficient high level.

Therefore, the NMOS transistors Q1 and Q3 are controlled by converting the driving signal of the NMOS into a boosted voltage Vpp.

7 is a block diagram in which the technical principles of the present invention are applied differently. When there are several sense amplifier arrays driven in an operation of reading a plurality of memory cell arrays, two sense amplifier arrays may be paired, and the principles of the present invention may be applied as it is.

That is, the driving method of the MOS transistor with respect to the sense amplifier array (A) and the sense amplifier array (B) can be applied to Figure 4B, 4C or 4D.

As described above, the present invention adjusts the activation time of the sense amplifier driver in driving the branch amplifier array of the memory device, while maintaining the sense amplifier basic operation. After the PMOS transistor operates and the remaining amplifier arrays, on the contrary, the NMOS transistor operates after the PMOS transistor operates, thereby providing an advantage of reducing the maximum instantaneous current causing noise inside the memory device.

Claims (4)

A memory block consisting of a plurality of memory cell arrays having a plurality of bit lines; A first sense amplifier group for sense amplifying data on bit lines corresponding to one half of said memory block; A first driver for driving operation power to be supplied to the first sense amplifier group; First switching means for switching a first power supply voltage to be supplied to the first sense amplifier group to be supplied to the first sense amplifier group; Second switching means for switching a second power supply voltage to be supplied to the first sense amplifier group; A second sense amplifier block for sensing and amplifying data on bit lines corresponding to the other half of the memory block; A second driver for driving operation power to be supplied to the second sense amplifier group; Third switching means for switching a first power supply voltage to be supplied to said second sense amplifier group; And a fourth switching means for switching a second power supply voltage to be supplied to said second sense amplifier group. The method of claim 1, wherein the first switching means and the fourth switching means are operated first by adjusting the activation time of the switching means of the first driving part and the second driving part, and then operating the second switching means and the third switching means. Alternatively, the second switching means and the third switching means are operated first, and then the first switching means and the fourth switching means are operated to reduce the maximum instantaneous current causing noise to the power supply voltage. Sense amplifier drive circuit. 2. The method according to claim 1, wherein when the first switching means of the first driving part and the third switching means of the second driving part are used as an NMOS transistor, the potential of the switching signal of the first switching means is raised to a boosted high level signal. And a sense amplifier drive circuit configured to convert. When there are several sense amplifier arrays driven in the operation of a plurality of memory cell arrays, the PMOS switching means of one sense amplifier array may be adjusted by adjusting the activation time when driving the sense amplifier array by pairing two sense amplifier arrays. And the NMOS switching means of another sense amplifier array are operated first, and then the NMOS switching means of one sense amplifier array and another sense amplifier array PMOS switching means are operated to reduce the power supply voltage. A sense amplifier drive circuit, configured to reduce the maximum instantaneous current induced.