KR0137973B1 - Free decoder circuit of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pre-decoder circuit of a semiconductor memory device, in which column addresses are changed sequentially with certain rules, not randomly changing operations, or only least significant bit addresses are changed and most significant bir addresses are changed. When the pulse signal is transmitted to the output signal of the column decoder in the unchanged operation, the pulse address signal of the input signal changes every clock (clk), so that the remaining address signals operate only when the address signal changes, thereby reducing the power. It works.

Description

Predecoder Circuit of Semiconductor Memory

1 is a diagram illustrating an exemplary embodiment of a conventional predecoder circuit and its peripheral circuits.

2 is a circuit diagram of FIG.

3 is a diagram illustrating a free decoder and a peripheral circuit thereof according to a first embodiment of the present invention.

4 is another embodiment of the pre-decoder circuit used in the present invention

5 is another embodiment of a decoder circuit used in the present invention.

6 is an operation timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

100, 101, 200, 201: first pre decoder unit

102 to 105, 202 to 205: Address input buffer section

106,206: First pulse signal generator

107,207: second pulse signal generator

108,208: Decoder part

110, 111, 210, 211: delay circuit

112,212: address strobe part 113,213: latch circuit part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pre-decoder circuit of a semiconductor memory device, and more particularly, to a pre-decoder that outputs a pulse signal that turns on only for a predetermined delay time as a signal for operating a column decoder of a synchronous DRAM. It is about.

FIG. 1 is a conventional predecoder and a peripheral circuit diagram thereof. The address input buffer unit 120 to 105 strobing an address signal input from the outside at the instant of change of the clock signal using a clock signal input from the outside. ), A pre decoder unit 100 to 101 for generating a predecoder signal using output signals of two or more address buffers, and a column decoder unit for generating a signal for selecting a column using the output signal of the pre decoder unit. It consists of 108.

In particular, when the device does not require a read modify write operation, only the read or write operation is performed. Therefore, the column decoder does not need to be turned on all the time during the clock (clk) period. For this operation, a pulse signal has been used for the input address signal of the column decoder.

In this case, a pulse signal is sent to the input signal of the column decoder. When all the lines are pulse signals, address lines must be toggled every clock clk, which causes a large power consumption problem.

In order to achieve the above object, the pre-decoder circuit of the semiconductor device of the present invention outputs a pulse signal even if all input signals of the column decoder are not pulse signals, i.e., only one pulse signal, and therefore the input signal of the column decoder. The circuit is implemented so that only one of the input signals carries the pulse signal and the remaining signals change only when the input signal of the decoder changes.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in more detail.

3 is a predecoder and a peripheral circuit diagram according to a first embodiment of the present invention, and includes first and second pulse signal generation circuits 206 and 207 for inputting a clock signal to generate a pulse signal having a constant delay time. ,

An address strobe unit for inputting a pulse signal and an address signal output from the second pulse signal issuing circuit unit 207 to receive the address signal input when the pulse signal changes from a first state to a second state in a feature operation ( 212) and at least two or more address input buffer sections 202 to 205, each of which comprises a latch circuit section 213 which changes the state of the output signal only when the address signal received from the outside is different from the previous state;

A first predecoder unit 200 for generating an address signal having a constant pulse width by using the output signal of the address input buffer unit 202 and the pulse signal from the first pulse signal generation circuit unit 206 as input signals. Wow,

A second predecoder unit 201 for converting an output signal when an input signal is changed by using output signals of the at least two address input buffer units as input signals;

And a decoder unit 208 for outputting an output signal having a constant pulse width only at a selected decoder using the output signals of the first and second predecoder as input signals.

The first pulse signal generation unit 206 includes a node N42 for outputting a clock signal clk, a delay circuit unit 210 connected between the node N42 and the node N43, and the node N43. ) And a delay circuit 211 connected between the node N44, an inverter G45 connected between the node N44 and the node N45, and the node N43 and the node N45. And a NAND gate G46 for outputting a logically combined signal to the node N46, and an inverter G47 connected between the node N46 and the node N47, wherein the second pulse signal generation circuit portion ( 207 inputs the inverters G48 to G50 connected in series between the node N42 and the node N50 and the node N42 and the node N50 to logically combine a signal to the node N51. NAND gate G51 to output, and the inverter G52 connected between the said node N51 and the node N52.

The address strobe unit 212 inputs a signal of the second pulse signal output node N52 and a node N53 that inputs an address signal, and outputs a logically combined signal to the node N55. And a NAND gate G43 for inputting a signal of the node N52 and the inverted address signal N54 and outputting the signal to the node N43, wherein the latch circuit 213 is configured as the node N52. It is connected between (55, N56) and (N57, N58) to form the first address input buffer unit 202. And a second address buffer unit 203 for inputting the second address, a node N59 for inputting the second address, and an output to the nodes N60 and N61, a jod N62 for inputting the third address, and A second address buffer unit 204 for inputting the node N52 and outputting it to the nodes N63 and N64, a node N65 for inputting a fourth address, and the node N52 for inputting the node N66, And a fourth address buffer section 205 for outputting to N67).

The first predecoder unit 200 outputs an output pulse signal N47 of the first pulse signal generation circuit unit 206 and an output signal N57 or N60 of the first and second address input buffer units 202 and 203. NAND gate G24 for outputting the logically combined signal to the node N68 by inputting the node, and the logically combined signal for the logically combined signal by inputting the nodes N47, N57, and M61 to the node N69. A NAND gate G26 for outputting a signal to the node N70, a NAND gate G27 for inputting the nodes N47, N58, and N60 to output a logically combined signal to the node N71, and the node ( N68) and an inverter G28 connected between the node N72, an inverter G29 connected between the node N69 and the node N73, and a connection between the node N70 and the node N74. The inverter G30, the inverter G31 connected between the node N71 and the node N75, and the nodes N73 to N75 for outputting an address signal. The second predecoder 201 is configured to input and output an output node N63 of the third address input buffer 204 and an output node N67 of the fourth address input buffer 205. A NAND gate G32 for outputting a signal to the node N76, a NAND gate G33 for inputting the nodes N63 and N67 to output a logically combined signal to the node N77, and the nodes N64 and NAND gate G34 for inputting N66 to output the logically combined signal to the node N78, and NAND gate G35 for inputting the nodes N64 and N67 to output the logically combined signal to the node N79. ), An inverter G37 connected between the node N76 and the node N81, an inverter G36 connected between the node N77 and the node N81, the node N78 and a node. Inverter G38 connected between N82, inverter G39 connected between the node N79 and node N83, and the nodes N81 to N8 for outputting an address signal. 3) consists of.

Finally, the decoder unit 208 inputs the nodes N72 and N80 and the node N84 to output a logically combined signal to the node N85, and the node N85 and the node. It consists of the inverter G54 connected between N86.

In operation, one of the first second predecoder units 200 and 201 outputs a pre-decoded pulse signal every clock clk, and the other predecoder unit outputs the previous signal. The output signal is changed only when the address is changed in comparison with the state of. The decoder unit 208, which uses the output signals of the predecoder, outputs a pulse signal, and only a pair of address lines of the input signals are toggled at every clock, and the remaining address lines Power consumption is reduced in continuous operation only when the address changes.

4 is a diagram showing another embodiment of the predecoder circuit used in the present invention, in which the output signal of the address input buffer unit 202 and the output signal of the internal address generator are identified as input signals with a pulse signal having a constant delay time. In operation, a first predecoder generates an address signal having a constant pulse width by using an externally input address signal, and in another specific operation, generates an address signal having a constant pulse width by using an address signal of an internal address generator. (G55), and

An output signal is generated using an externally input address signal in a specific operation using output signals of two or more address input buffer units and output signals of two or more internal address generators, and in another specific operation, an output signal of the internal address generator. A second predecoder unit G56 converts the output signal only when the input signal is changed during the operation conversion or the address conversion using the address signal.

The first predecoder G55 has predecodig having a constant pulse width by using an output signal of at least two address input buffer units, an output signal of at least two internal address generators, and a pulse signal having a constant delay time as an input signal. The address signal of the internal address generator may be generated in another specific operation, and a pre-decoded address signal having a constant pulse width may be generated.

The circuit inputs the nodes N87 to M89 to output the logically combined signal to the node N93 and inputs the nodes N90, N91, and N92 to output the logically combined signal to the node N94. A NAND gate G56 and a NAND gate G57 for inputting the node N93 and the node N94 to output a logically combined signal to the node N95.

5 is a diagram illustrating another embodiment of the decoder circuit used in the present invention, wherein a PMOS transistor connected between a power supply voltage Vdd_ and a node N99 and an output signal of the first predecoder unit 200 is input to a gate thereof. QN), an NMOS transistor Q2 connected between the node N99 and the node N100 and the output signal of the first predecoder unit 200 is input to a gate, and the node N100 and the node ( NMOS transistor Q3, which is connected between N101 and the output signal of the second predecoder unit 201 is input to the gate, is connected between the node N101 and the ground voltage Vss, and is connected to the gate. An NMOS transistor Q4 to which the output signal of the second predecoder unit 201 is input, and inverters G58 to G60 connected in series between the node N99 and the node N104 are configured.

For reference, the predecoder circuit of the present invention includes an address input buffer to assist in the operation of the claim 1 of the back side.

When the predecoder circuit of the present invention described above is implemented in the semiconductor memory device, the column addresses are sequentially changed according to a predetermined rule, not randomly changing operations, or only the least significant bit address is changed and the most significant bit is changed. (most significant bit) transfers the pulse signal to the output signal of the column decoder in an operation where there is no change of addresses, while the pulse address signal of the input signal changes every clock (clk) so that the remaining address signals operate only when the signal changes. This reduces the power.

Claims (10)

1. A semiconductor memory device, comprising: first and second pulse signal generating means for generating a pulse signal having a predetermined delay time from a clock signal, and a signal output from the second pulse signal generating means in a second state in a first state; At least two address input buffer means comprising: address strobe means for accepting the address signal input when it is changed to; and latch means for changing the state of the output signal only when the address signal received externally is different from the previous state; First predecoder means for generating an address signal having a constant pulse width using an output signal of said address input buffer means and a pulse signal from said first pulse signal generating means as input signals, and said at least two or more addresses; Input signal using the signal of the input buffer section as an output signal And a second predecoder means for converting an output signal when it changes, and a decoder means for outputting an output signal having a constant pulse width only in a selected decoder using the output signals of the first and second predecoder means as input signals. A predecoder circuit of a semiconductor memory device. The address synthesizer according to claim 1, wherein the first predecoder means uses an output signal of the address input buffer means and the internal address generator as a pulse signal having a constant delay time as an input signal and is externally input in a specific operation. To generate a predecoded address signal having a constant pulse width, and to precode the address signal having a predetermined pulse width by using the address signal of the internal address generator only in another specific operation. Decoder circuit. 2. The apparatus of claim 1, wherein the second predecoder means inputs a pulse signal having a constant delay time from an output signal of the address input buffer means and the internal address generator, and receives an externally input address signal in a wrong operation. To generate a pre-decoded address signal having a constant pulse width, and in other specific operations, to generate a pre-decoded address signal having a constant pulse width using an address signal of an internal address generator. Decoder circuit. 2. The apparatus of claim 1, wherein the decoder means comprises one pull-up device and two or more pull-down devices as components, and the output signal of the first predecoder is a gate input of the pull-up device and the pull-down device. And a output signal of the second predecoder is used as a gate input signal of the pull-down device. The predecoder circuit of claim 1, wherein the least significant bit address is used among the input signals of the decoder means as an address used as an input signal of the first predecoder means. 1. A semiconductor memory device comprising: first and second pulse signal issuing means for inputting a clock signal to generate a pulse signal having a constant delay time, and a pulse signal and an address signal output from the second pulse signal generating means; First address strobe means for receiving the address signal input when the pulse signal changes from the first state to the second state in a specific operation, and outputting an address signal having a constant pulse width using the input address. Inputting a first address input buffer means and a pulse signal and an address signal output from the second pulse signal generating means to receive the address signal input when the pulse signal changes from a first state to a second state in a specific operation; Second address strobe means to accept and the address signal to accept externally A second address input buffer means consisting of latch means for changing the state of the output signal only when different from the previous state and an output signal from the at least two first address input buffer means or the first address input Predecoder means for generating an address signal having a constant pulse width by using an output signal of the device and an output signal of the second address input buffer or an output signal of the at least two second address input devices as input signals, and the predecoder means; And a decoder means for outputting an output signal having a constant pulse width only in the decoder selected as the output signal of the decoder means. 7. The apparatus of claim 6, wherein the first address input buffer means and the second address input buffer means have a multiplex function between the external address input signal and an address signal generated therein so that an externally input address is specified in a specific operation. A predecoder circuit of a semiconductor memory device, characterized in that it accepts a signal and accepts an address signal output from an internal address generator in another specific operation. 7. The method of claim 6, wherein the first address input buffer means and the second address input buffer means accept an address new hole at a rising edge and a falling edge when a clock signal changes in a specific operation. And a predecoder circuit of a semiconductor memory device. 7. The predecoder circuit of claim 6, wherein the input signal of the first address input buffer means is a least significant bit address. The PMOS transistor (Q1) of claim 6, wherein the decoder means is connected between a power supply voltage (Vdd) and a node (N99) and the output signal of the first predecoder unit 200 is input to a gate. An NMOS transistor Q2 connected between a node N99 and a node N100 and the output signal of the first pre-decoder unit 200 is input to a gate, and connected between the node N100 and a node N101. And an NMOS transistor Q3 through which the output signal of the second predecoder unit 201 is input to the gate, and is connected between the node N101 and the ground voltage Vss, and the second predecoder unit 201 is connected to the gate. And an inverter (G58 to G60) connected in series between the node (N99) and the node (N104).