KR0135013B1 - Multichannel data concurrent processing apparatus in pcm system - Google Patents

Abstract

According to the present invention, a plurality of dedicated processors serve as functions of an upper processor in order to carry data processed at a higher speed by an internal upper processor to an external PCM path, and conversely, a higher processor can process data received at a PCM path at higher speed. In addition to performing the communication function through the PCM path, the arbitration processor relates to a parallel processing structure for processing multi-channel data of the PCM path to perform the communication function between the upper processor and the dedicated processor.

In the present invention, the load of function performance is very large (30-40 mega-instructions per second), but when the data transmitted and received between each function is considerably small (8 kbps or less), the effect of economically implementing the above two functions simultaneously is achieved. There is.

Description

Multichannel Data Concurrent Processing Apparatus in PCM System

1 is a block diagram schematically showing the configuration of a conventional multi-channel data processing apparatus.

2 is a block diagram showing a configuration of the present invention.

3 is a detailed diagram of a decoder and a multifunction processor of a higher processor.

4 is an embodiment of the arbitration and state management unit.

5 is an embodiment of a dedicated processor unit.

6 is an embodiment of a use clock generator.

7 is an embodiment of an arbitration processor state management unit.

According to the present invention, a plurality of dedicated processors are used to load data processed at a high speed by an internal upper processor to an external pulse code modulation (PCM) path and to process data received at a PCM path at a higher speed by the higher processor. Not only divides the functions of the upper processor but also performs a communication function through the PCM path, and the arbitration processor relates to a parallel processing structure for processing multi-channel data of the PCM path that performs the communication function between the upper processor and the dedicated processor. .

The host processor sends the packet data input through the external bus to the dedicated processor through the arbitration processor, and the dedicated processor processes the packet data with the predetermined algorithm, and then processes the PCM data with the above algorithm and then through the arbitration processor. Send to. The arbitration processor controls the data flow between one host processor and multiple dedicated processors.

Mobile communication network is different from existing fixed telephone network in that it uses wireless channel instead of subscriber line and subscriber moves. Since the radio frequency used by a mobile communication network is limited, a large area is divided into a small area called a cell, and a specific frequency used in one cell is repeatedly used in another cell. Thus, wireless communication is performed between a base station and a mobile station (mobile station or subscriber) with a base station in one or more cells, and the call continues without interruption even when moving between cells during a call. In order to do so, a special service called hand-off is needed. In order to implement a hand-off service, a selecting function for selecting voice data from two or more cells is required.

For the advantage of the frequency utilization efficiency of the wireless channel, the 64kbps PCM coding method used in the fixed telephone network is not applied to the coding of the voice signal of the mobile communication network, and the bandwidth of the lower bandwidth (for example, about 8kbps or less) The coding scheme is applied. However, since the encoding scheme is different in this way, a function (transcoding function) for converting the encoding scheme is required for the mobile subscriber and the fixed subscriber (refering to a subscriber using an existing general telephone) to communicate.

In order to simultaneously implement the above-described selection function and transcoding function, a structure different from the existing structure (Patent Application 93-16053 (1993.8.18)) is required. If the existing structure is simplified, it can be represented as shown in FIG. This structure is broadly divided so that the upper processor unit and the dedicated processor unit are directly connected through the communication unit so that the main functions of the upper processor control the dedicated processor, that is, the case where the load of the upper processor is low. The existing structure is suitable for performing any one of the two functions described above (selecting and transcoding).

In the present invention, as in the above example, when the load of individual functions is very large (30-40 mega-instructions per second), but the transmission data between each function is very small (8 kbps or less), the above two functions The purpose is to present an economic structure that implements both.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 shows the configuration of the present invention.

The upper processor unit unpacketizes the packet data delivered by the external next-level processor through the external server, and executes the contents corresponding to itself and the matters to be performed by the dedicated processor unit (hereinafter, referred to as dedicated processor data) through the upper communication unit. Send the packet to the arbitration processor unit and, in the opposite direction, receive the dedicated processor data sent by the arbitration processor unit through the upper communication unit to generate packet data or perform some action (for example, state management) at its own discretion. It receives the signal from and gives reset signal directly to the arbitration processor.

The arbitration processor unit sends the status of the dedicated processor unit read from the arbitration and state management unit to the upper processor unit through the upper communication unit, or allows the dedicated processors constituting the dedicated processor unit to access the lower communication unit to communicate with the arbitration processor unit. Arbitration processor section for arbitration Connects the address bus and data bus to the arbitration and status management section, sends and receives serial data to and from the dedicated processor section through the arbitration and status management section, and arbitrates individual interrupt signals sent by the dedicated processor of the dedicated processor section. And if the state management unit collects and sends the arbitration processor directly receives the aggregated interrupt signal, and the lower communication unit and the arbitration and state management unit collects and sends the dedicated processor unit and dedicated processor data.

The arbitration processor state management unit sends to the upper processor unit a normal state presence signal generated by receiving the specific signal from the arbitration processor unit from the arbitration and state management department.

The arbitration and status management unit selects the upper communication unit under the control of the arbitration processor unit or selects the lower communication unit so that the arbitration processor unit can access the upper and lower communication units. Similarly, the dedicated processor unit can access the lower communication unit under the control of the arbitration processor unit. Arbitrary processor unit and dedicated processor unit to arbitrate serial communication.

The dedicated processor unit processes the dedicated processor data received from the arbitration and state management unit into the PCM data by sending it to the PCM matching unit, and processes the PCM data received from the PCM matching unit according to the defined method into the dedicated processor data. Send to Mediation and State Management.

The PCM matching unit allows the external time switch and the dedicated processor to transmit and receive PCM data, and sends the PCM data communication clocks received from the external time switch to the use clock generator.

The clock generator generates clocks that can be used by the dedicated processor unit and the arbitration processor unit by using the clocks for PCM data communication received from the PCM matching unit.

The connection structure of the external next higher processor and the upper processor unit is the same as the connection structure between the upper processor unit and the arbitration processor unit described below. The upper processor part refers to the existing structure described above, but the general purpose microprocessor of the existing structure is replaced with the upper processor in the present invention, and the upper communication part and the connection structure refer to the existing structure as well. The signals added according to the invention are as shown in FIG.

3 as a turning part of the top processor section decoder and the multi-function processing, the decoder adds the multi-function selection of the element is MFP1 signal (MFPCS1 _-) Contributions key generate, MFP1 are mediated processor status management arbitration processor malfunction signal from the (CDSPfail _-) a receive reset signal (CRS _-) to arbitration processor unit according to the determination of the parent processor sends.

For the structure of the upper communication unit, the arbitration processor, and the lower communication unit, see 'Editing Control Device for Editable Recording Guide Device of Electronic Switch (Patent Registration No. 63089, 1993.6.28). However, in the present invention, the arbitration processor replaces the existing one-chip processor of the upper and lower communication structure, the chip selection signal of the upper and lower communication unit comes from the arbitration and state management unit, and the arbitration processor is the PCM from the use clock generation unit. It receives the data communication clock (HCLK, HFS _- C) and communicates PCM serially with PCM matching unit.

4 illustrates an embodiment of the arbitration and state management unit, which is implemented as an electrically programmable logic device (EPLD), and has an address bus (DAB 15 to 0), a data bus (CDB 15 to 0), and an arbitration. The control signal of the processor is connected to the serial communication signal line, and the lower communication unit is connected to the data bus (DDB 7 to 0), the address bus (DAB 10 to 0), the lower communication control signal line, and the dedicated processor unit is connected to the address bus ( DAB _- 0 15,8,5-0, DAB _- 1 15,8,5-0), data bus (DDB _- 0 7-0, DDB _- 1 7-0), first and second dedicated processor control signal lines, It is connected by a serial communication signal line.

5 is a view illustrating an embodiment of a dedicated processor unit, and may include a plurality of dedicated processors. Here, an example of using two dedicated processors will be described. The first dedicated processor is connected to the arbitration and state management unit by an address bus (DAB _- 0 15, 8, 5 to 0), a data bus (DDB _- 0 7 to 0), a first dedicated processor control signal line and a serial communication signal line. It receives serial communication signals (HCLK, HFS _- 0) from the clock generator, and is connected to the PCM matching unit and PCM data transmission / reception line (HDX, HDR) at the same time. However, PCM data can be transmitted and received only in the timeslots allowed to it. The second dedicated processor is also connected to the arbitration and state management unit and signal lines (DAB _- 1 15,8,5-0, DDB _- 1 7-0, second dedicated processor control signal line), and serial communication to the use clock generation unit. Receive signals HCLK, HFS _- 1. For the description of the PCM matching unit, refer to the existing PCM matching unit (Patent Registration No. 63089, 1993.6.28).

FIG. 6 illustrates an embodiment of a use clock generation unit, which is implemented as an EPLD, receives clocks CLK and FS from a PCM matching unit, and transmits PCM data communication clocks HCLK and HFS _- 0 to an arbitration processor and dedicated processors. , HFS _- 1, HFS _- C).

7 is an embodiment of the arbitration processor state management unit, which may be implemented as 74LS123 or EPLD, and detects when a periodic signal does not occur for several cycles and generates a signal. That is, if the arbitration processor malfunction signal (CDSPfail ₋ ) is activated when a few cycles of the arbitration processor operation signal are lost from the arbitration and status management unit, the second multifunction device MFP1 of the upper processor unit converts the signal into an interrupt. receiving higher processor is determined by arbitration processor reset signal (CRS _-) and to the action, such as resetting the processor to start the arbitration.

Claims (1)

PCM matching means for transmitting and receiving to and from an external time switch for the two types of processors to perform the functions of each load independently and at the same time smooth communication with each other, A use clock generating means for receiving the PCM data communication clocks from the PCM matching means and generating clocks used by the dedicated processor means and the arbitration processor means and sending them to each of the clocks; Performs related functions when analyzing or assembling packet data while transmitting and receiving packet data with an external next-order processor, and receiving status-related data that controls the arbitration processor means by receiving mediation processor operation signals from the arbitration processor state management means. A higher processor means for sending to, Arbitration to control the arbitration and status management means to transmit dedicated processor data up and down, to access the upper and lower communication means, and to arbitrate the serial communication signal line to transfer the program to be executed by the dedicated processor means. And control the status management means and read the operation status data of the dedicated processor means from the arbitration and status management means according to the operation maintenance data from the upper communication means and send it to the upper communication means, and the PCM data from the use clock generation means. An arbitration processor means for receiving communication clocks and transmitting and receiving PCM data to PCM matching means; An upper communication means for transferring dedicated processor data and operation maintenance data between the upper processor means and the arbitration processor means; Sub-communication means for transferring dedicated processor data between the arbitration and status management means and the arbitration processor means; Under the control of the arbitration processor means, select the higher communication means or lower communication means to allow the arbitration processor means to access the upper and lower communication means, and to arbitrate serial communication between the arbitration processor means and the dedicated processor means. Mediation and status management measures, An arbitration processor state management means for sending a signal of a normal state of the arbitration processor means generated by receiving a specific signal of the arbitration processor means from the arbitration and state management means, and Dedicated processor data received from mediation and state management means are processed into PCM data, and the clock received by the use clock means is loaded into the time slot assigned to each dedicated processor and transmitted to PCM matching means. On the contrary, a multi-channel data parallel processing apparatus of a PCM path comprising a dedicated processor means for processing the PCM data received from the PCM matching means according to a predetermined method to make the dedicated processor data to be sent to the mediation and state management means.