KR0135007B1 - Parallel processor system - Google Patents

Abstract

The present invention relates to a control signal adjusting apparatus capable of adjusting timing characteristics of a control signal between two processors having different pulse rates. The apparatus includes: a first D flip-flop (60) for inputting a first control signal output from the link adapter, the signal input terminal being connected to a base potential, and outputting a signal in synchronization with the input clock signal; A first control signal output from the link adapter is input to a preset terminal, a second control signal generated in synchronization with the first control signal of the high speed signal processor is input to a signal input terminal, and a clock signal to be input. A second flip-flop 65 which outputs a signal synchronously; A first NAND gate 70 that inputs a second output signal of the first flip-flop and a first output signal of the second flip-flop, and outputs an output signal to a first control signal input terminal of the high speed signal processor; )Wow; And a pulse delay unit for inputting the second control signal of the high speed signal processor to the clear terminal and outputting the pulse signal to the second control signal input terminal of the link adapter for a predetermined time when the second control signal is input. It is done.

Description

Control signal conditioner between two processors with different pulse rates.

1 is a block diagram showing a state of use according to the prior art.

2 is an operation timing diagram of FIG.

3 is a block diagram illustrating an apparatus according to the present invention.

4 is a detailed circuit diagram of a control signal controller shown in FIG.

5 is an operation timing diagram of FIG.

6 is an operation timing diagram of FIG.

The present invention relates to a parallel processing system for high-speed signal processing of multiprocessing, and more particularly, to a control signal adjusting apparatus capable of adjusting timing characteristics of control signals between two processors having different pulse rates.

In order to construct a parallel processing system for high-speed signal processing of multiprocessing, a parallel processing system, TRANSPUTER (T805-20 from INMOS) and TMS320C40 (Texas Instruments), a high-speed digital signal processor, are connected to each other. It is used.

In other words, when a parallel processing system is implemented by connecting two processors, a smooth communication capability between the two processors becomes a factor that determines the performance of the system.

However, the high-speed signal processor TMS320C40 supports 8-bit parallel communication through the communication port, and the parallel processor TRANSPUTER supports 8-bit serial communication through the serial link.

Therefore, in order to facilitate communication between two processors having different communication methods, IMSC011 (INMOS), a link adapter for converting serial data into 8-bit parallel data, is connected between the two processors.

The use state by the above description will be described in detail with reference to FIGS. 1 and 2 which are conventional circuit diagrams.

In the configuration, the 8-bit serial data is converted into 8-bit parallel data between the parallel processing processor 30 supporting the 8-bit serial communication method and the high speed signal processing processor 10 supporting the 8-bit parallel communication method. The link adapter 20 which converts is connected.

In addition, since the timing characteristics of the control signal for communication are defined differently between the link adapter 20 and the high speed signal processing processor 10, in order to adjust the characteristics, the first control of the link adapter 20 is performed. The first inverter 40 is connected between the output terminal of the signal Qvalid and the input terminal of the first control signal / STRB of the high speed signal processing processor 10.

A second inverter 45 is connected between an output terminal of the second control signal / RDY of the high speed signal processing processor 10 and an input terminal of the second control signal Qack of the link adapter 20. It is. In addition, the high speed signal processor 10 is a 32-bit device, which is 2.5 times faster than the clock speed of the link adapter 20.

The process by which signals are transmitted by the conventional circuit having the above configuration will be described with reference to the timing diagram shown in FIG.

The 8-bit serial signal output from the parallel processor 30 is input to the link adapter 20 and converted into an 8-bit parallel signal.

The signal converted into a parallel signal by the link adapter 20 is output to the high speed signal processor 10. Since the high speed signal processor 10 is a 32-bit processor, 8 bits of parallel data are input four times. To combine and output into one 32-bit data.

The first 8-bit data output from the link adapter 20 to the high speed signal processing processor 10 first outputs a high signal at the first control signal Qvalid output terminal of the link adapter 20. The high signal is inverted through the inverter 40 and input as a low signal to the first control signal / STRB input terminal of the processor 10. (I))

When the first control signal in the low logic state is input, the processor 10 reads data from the link adapter 20 ((d) in FIG. 2), and synchronizes the second control signal with the second control signal. The low signal is output to the control signal (/ RDY) output terminal.

On the other hand, when the first control signal of the link adapter 20 is changed from a high signal to a low signal, a high signal is input to the first control signal input terminal of the processor 10. The processor 10 completes 1-byte transmission while outputting a high signal to the second control signal / RDY output terminal in synchronization with the input of the high signal to the first control signal / STRB input terminal. .

That is, the processor 10 inputs data in synchronization with a low signal being input to a first control signal (/ STRB) input terminal, and is converted into a high signal from a low signal to the first control signal input terminal. The data entry is completed in synchronization with the.

When the four-byte transmission is completed by the above process and the first control signal of the processor 10 is converted into a high signal, the 32-bit data transmission is completed and the preparation step for the next 32-bit data transmission is completed.

However, the high speed signal processor 10 should convert the first control signal / STRB to a high signal within a predetermined time Tmax immediately after completion of 4 bytes. If this condition is not satisfied, the processor As the clock speed of 10 is 2.5 times faster than the clock speed of the link adapter 20, the fourth byte is input once more. That is, an error of always adding one byte occurs.

That is, in the conventional circuit, although the timing characteristics of the control signal for data transmission are different from each other, an error occurs during data transmission by directly connecting the processor 10 and the link adapter 20.

Accordingly, an object of the present invention is to provide a control signal adjusting apparatus for adjusting a control signal between two processors having different pulse rates.

In order to achieve the above object, the present invention connects a link adapter having a pulse rate slower than that of the high speed signal processor between a high speed signal processor and a parallel processor, and controls the timing of a control signal between the high speed signal processor and the link adapter. A parallel processing system connected with a control signal adjusting unit for adjusting; The control signal controller is configured to input a first control signal output from the link adapter to a preset terminal, a signal input terminal to a ground potential, and a first D flip-flop to output a signal in synchronization with the input clock signal. 60; A first control signal output from the link adapter is input to a preset terminal, a second control signal generated in synchronization with the first control signal of the high speed processor is input to a signal input terminal, and synchronized with an input clock signal. A second flip-flop 65 outputting a signal; A first NAND gate 70 configured to input a second output signal of the first flip-flop and a first output signal of the second flip-flop, and output an output signal to a first control signal input terminal of the high speed processor; Wow; And a pulse delay unit for inputting a second control signal of the high speed processor to a clear terminal and outputting a pulse signal to a second control signal input terminal of a link adapter for a predetermined time when the second control signal is input. It is done.

Hereinafter, a control signal adjusting apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 3, the overall circuit block configuration will be described. The 8-bit between the parallel processor 31 supporting the 8-bit serial communication method and the high speed signal processor 11 supporting the 8-bit parallel communication method will be described. The link adapter 21 which converts serial data into 8-bit parallel data is connected.

Since the link adapter 21 and the high speed signal processing processor 11 have different timing characteristics of control signals for communication, the link adapter 21 and the high speed signal processing are used to adjust the characteristics. The control signal adjusting unit 50 is connected between the processors 11.

A detailed circuit diagram of the control signal adjusting unit 50 is shown in FIG.

In the connection relationship, the first control signal Qvalid of the link adapter 21 is input to the preset terminal PR of the first and second D flip-flops 60 and 65, and the first D flip-flop 60 is connected. Signal input terminal (D) is connected to the ground potential. The clock terminal CP of the flip-flops 60 and 65 inputs an operation clock signal of the high speed processor 11, and the clear terminal CLR of the flip-flops 60 and 65 is a supply power supply VCC. ) Is connected.

The second output terminal Q of the D flip-flop 60 and the first output terminal Q of the D flip-flop 65 are connected to two input terminals of the first NAND gate 70. The first output terminal Q of the 2D flip-flop 65 is also connected to the second input terminal of the second NAND gate 73. The output terminal of the first NAND gate 70 is connected to the first control signal (/ STRB) input terminal of the high speed processor 11.

The output terminal of the second control signal / RDY is connected to the first input terminal of the second NAND gate 73 in the high speed signal processor 11. The output terminal of the second NAND gate 73 is connected to the input terminal of the fourth NAND gate 77, and the output terminal of the fourth NAND gate 77 is the signal input terminal D of the second D flip-flop 65. ).

The second control signal of the high speed signal processor 11 is input to the clear terminal CLR of the third flip-flop 63, and the signal input terminal of the third flip-flop 63 supplies the supply power supply VCC. Enter it. The output terminal Q of the flip-flop 63 is connected to the signal input terminal of the fourth flip-flop 67, and the preset terminals PR of the third and fourth flip-flops 63 and 67 are reset. Input the signal.

The output terminal Q of the third flip-flops 63 and 67 is connected to the input terminal of the third NAND gate 75, and the output terminal of the third NAND gate 77 is formed of the link adapter 21. 2 Connect with control signal input terminal. The clear terminal CLR of the fourth flip-flop 67 receives a supply power supply VCC.

The operation and effect of the present invention by the above configuration will be described in detail with reference to the attached timing chart.

The 8-bit serial signal output to the parallel processor 31 is input to the link adapter 20 and converted into an 8-bit parallel signal.

The signal converted into a parallel signal by the link adapter 21 is output to the high speed signal processor 11. Since the high speed signal processor 11 is a 32-bit processor, 8 bits of parallel data are input four times. To combine and output into one 32-bit data.

The 8-bit data output from the link adapter 21 to the high speed signal processing processor 11 is performed according to the control signal of the control signal adjusting unit 50 to be described later. The clock signal used here is an operating clock signal of the high speed signal processor 11. (CLOCK waveform diagram of FIG. 5)

5 is a timing diagram when the first control signal / STRB is input to the high speed signal processing processor and the second control signal / RDY is output before the one clock signal ends. The second control signal of the processing processor 11 is a signal generated in synchronization with the first control signal.

When the link adapter 21 outputs a high logic first control signal Qvalid, the high logic signal is input to the preset terminals of the first and second D flip-flops 60 and 65. (Qvalid waveform diagram of FIG. 5)

During this operation, the second output terminal Q of the first flip-flop 60 outputs a high logic signal at the rising edge of the first clock signal. The high signal is converted into a low signal through the first NAND gate 70 and is input to the first control signal / STRB input terminal of the high speed signal processor 11 (step 1 in FIG. 5).

When the first control signal of the low signal is input, the high speed signal processor 11 outputs the second control signal / RDY of the low signal. (Step 2 of FIG. 5)

The second control signal output from the high speed signal processor 11 outputs a pulse signal in a low state, and the output terminal Q of the third and fourth flip-flops 63 and 67 outputs a low pulse signal. The signal is converted to a high signal through the NAND gate 75 and input to the second control signal Qack input terminal of the link adapter 21 (the U9 output of FIG. 5).

The second control signal is applied to the first input terminal of the second NAND gate 73, the second NAND gate 73 outputs a high signal, and the high output of the second NAND gate 73 is It is input to the fourth NAND gate 77 to output a low signal. This low signal is applied to the signal input terminal of the second D flip-flop 65.

When the second control signal is generated in the high speed signal processor 11, the first D flip-flop 60 is in a high logic state and the second D flip-flop 65 is in a low logic signal at the rising edge of the next clock signal. Outputs The low logic signal is inputted to the first NAND gate 70, converted into a high signal, and outputted. (Step 3 of FIG. 5)

When the first control signal of the high speed signal processor 11 is converted into a high signal, the second control signal is soon converted into a high signal (step 4 in FIG. 5).

When the second control signal of the high speed signal processor 11 is converted into a high signal, the second control signal of the link adapter 21 is also switched, and the second control signal of the link adapter 21 is switched. After the second control signal of the high-speed signal processing processor 11 is converted to a high signal, the switching is performed after being maintained for at least one clock and a maximum of two clocks, which are the third and fourth flip-flops 63 and 67. This is because there is a delay for a certain time. (Step 5 of FIG. 5)

Accordingly, the control signal adjusting circuit is configured to input the first control signal / STRB to the high speed signal processing processor and output the second control signal / RDY before the first clock signal ends.

In this way, when the high signal is input to the first control signal input terminal, the processor 11 converts the output of the second control signal to the high signal and completes data input of 1 byte.

6 illustrates a case in which the second control signal / RDY is generated after the first clock signal is input to the processor 11 after the first control signal / STRB is input.

Before the high signal is output to the first control signal output terminal of the link adapter 21, the first control signal of the high speed signal processor 11 maintains a state in which a high signal is input. )

When the high signal is output to the first control signal output terminal of the link adapter 21 in the above state (Qvalid flatness diagram of FIG. 6). This high output is input to the preset terminal PR of the first and second D flip-flops 60 and 65.

When the clock signal is input to the clock terminal during this process, the second output terminal Q of the first D flip-flop 60 outputs a high signal. The high signal is converted into a low signal through the first NAND gate 70 and input to the first control signal input terminal of the high speed signal processor 70. (Step 2 of FIG. 6)

The high speed signal processing processor 11 maintains a low state until a second control signal is generated, and after the first control signal is input and the next clock signal is input, the high speed signal processing processor ( In 11), the second control signal output terminal outputs a low signal. (Step 3 of FIG. 6)

The second control signal output from the high speed signal processor 11 is applied to the clear terminals of the third and fourth flip-flops 63 and 67 and the output terminals of the third and fourth flip-flops 63 and 67. Q outputs a low pulse signal, which is converted into a high signal through the third NAND gate 75 and input to the second control signal input terminal of the link adapter 21. That is, the second control signal of the high speed signal processor 11 is generated and the second control signal input pulse signal of the link adapter 21 is generated. (U9 output of FIG. 6)

The low signal of the second control signal is input to the signal input terminal D of the second D flip-flop 65 through the second and fourth NAND gates 73 and 77.

At this time, when the clock signal is input, at the rising edge of the input clock signal, the first flip-flop 60 outputs a high signal and the second flip-flop outputs a low signal, so that the output of the NAND gate 70 is a high signal. do. This signal is applied to the first control signal input terminal of the high speed signal processing processor 11. (4 steps in FIG. 6)

When the first control signal of the high-speed signal processing processor 11 is converted to a high signal, the second control signal is maintained at a low logic state for 1/2 clock time and then converted to a high signal. (Step 5 of FIG. )

When the second control signal of the high speed signal processor 11 is converted into a high signal, the second control signal of the link adapter 21 is also switched, and the second control signal of the link adapter 21 is switched. After the second control signal of the high-speed signal processing processor 11 is converted to a high signal, the switching is performed after being maintained for at least one clock and a maximum of two clocks, which is the third and fourth flip-flops 63 and 67. This is because there is a delay for a certain time. (Step 6 of FIG. 6)

In the above two cases, the second control signal is generated after the first control signal is input from the processor 11 but before the first clock signal passes. The first clock signal is input after the first control signal is input from the processor 11. In the case where the second control signal is generated after the last time, the first control signal / STRB of the processor 11 remains within a predetermined time Tmax even immediately after the 4 bytes are transmitted to the processor 11 by the same process. By switching to the high signal, the 32-bit data transfer is completed and the preparation for the next 32-bit data transfer is made.

That is, conventionally, the first control signal (/ STRB) of the first processor 10 is synchronized with the first control signal (Qvalid) of the link adapter 20, the pulse signal is switched, thereby preventing the generated error To this end, in the present invention, the time when the first control signal / STRB of the first processor 11 is switched to the high signal is synchronized with the time when the second control signal / RDY is turned to the low signal. .

Accordingly, the first control signal Qvalid of the link adapter 21 is adjusted to have a small pulse width so as to be suitable for the first control signal / STRB of the high speed signal processor 11, and the high speed signal processor 11 The second control signal / RDY of) is largely adjusted in pulse width so as to fit the second control signal Qack of the link adapter 21.

As described above, the control signal adjusting device according to the present invention uses the link adapter IMSC011 to communicate with the high speed signal processor TMS320C40 and the parallel processor TRANSPUTER when the high speed processor and the link adapter have different pulse rates. By controlling the pulse rate of, it is possible to prevent the error of entering unnecessary data once more.

Claims (3)

A parallel connection between the high speed processor and the parallel processor, the link adapter having a slower pulse rate than the high speed signal processor, and a control signal controller for controlling the timing of the control signal between the high speed signal processor and the link adapter. In a processing system; The control signal adjusting unit, A first D flip-flop (60) for inputting a first control signal output from the link adapter to a preset terminal, the signal input terminal being connected to a ground potential, and outputting a signal in synchronization with the input clock signal; The first control signal output from the link adapter is input to the preset terminal, the second control signal generated in synchronization with the first control signal of the high speed signal processor is input to the signal input terminal, and the clock signal to be input. A first D flip-flop (60) for synchronously outputting a signal; A first NAND gate 70 that inputs a second output signal of the first flip-flop and a first output signal of a fraudulent second flip-flop, and outputs an output signal to a first control signal input terminal of the high speed signal processor; )Wow; And a pulse delay unit for inputting a second control signal of the high speed signal processor to a clear terminal and outputting a pulse signal to a second control signal input terminal of a link adapter for a predetermined time when the second control signal is input. Control signal control device between two processors with different pulse rates. The method of claim 1; The pulse delay unit includes: a third flip-flop (63) for inputting a supply power supply to a signal input terminal and a second control signal of the high speed signal processor to a clear terminal; A fourth flip flop (63) connecting the output terminal and the input terminal of the third flip flop; And a fourth NAND gate (75) for inputting the output signals of the third and fourth flip-flops. Signal conditioner. The method of claim 2; A second NAND gate (73) for inputting a second control signal of the high speed signal processor (11) and an output signal of the second D flip-flop; And a third NAND gate 77 for inputting the output of the second NAND gate and outputting the output to the signal input terminal of the second D flip-flop. Signal conditioner.