KR0134964B1 - Amplifier circuit with an amplifier transistor - Google Patents

Abstract

none.

Description

Amplifier circuit with amplifier transistor

1 is a known circuit diagram of a tunable front end for an FM receiver.

2 shows an important part of the circuit of FIG.

3 shows an impedance curve for the coupling of switching elements according to the invention.

4 shows an embodiment of the invention.

5 shows a change in the circuit according to FIG.

6 shows another embodiment of the present invention.

Figure 7a is a circuit diagram according to the present invention.

7b illustrates a suitable embodiment.

* Description of the symbols for the main parts of the drawings *

1: bipolar transistor 1c: base terminal 1e

1e: inductance 1f: capacitor

1g, 1i: connection wire 1h: bonding band

10, 10a: Capacitor 10b: Inductance

11 Impedance Curve 12 Series Resonance Point

F: Operating frequency range 13: Parallel resonance point

The present invention relates to an amplifier circuit having an amplifier transistor.

Signal amplifier stages, such as tunable pre- stages for FM receivers, often suffer from parasitic self-excitation. This parasitic self-oscillation frequency is generally several times the operating frequency of the amplifier circuit. The risk of parasitic self-oscillation exists especially when transistors with very high cutoff frequencies are used as amplifier elements. The risk of parasitic oscillation depends on the input and output side connections of the amplifier elements, the design of the amplifier circuit and the amplifier elements used.

A known method of reducing the risk of parasitic self-oscillation is to insert a resistor or a ferrite bead acting as a resistor into the feed line of an amplifier element, such as an emitter, base or collector feed line. However, this method often reduces the action of the amplifier stage at the operating frequency. For example, when a ferrite bead that acts as a resistor or resistor is inserted into the base or emitter feed line of the amplifier transistor, the noise rate of the amplifier stage is increased.

1 shows a known circuit of a tunable pre-end for an FM receiver having a bipolar transistor 1, an input network 2 and an output network 3. The antenna signal is received at the input network 2 at the circuit point 4. The output signal of the amplifier stage is transmitted from the output network 3 to the next stage, for example the mixer stage, at the circuit point 5. The operating voltage of the amplifier stage from the power supply 9 is supplied to the circuit point 8. The input network 2 is connected to the amplifier transistor 1 via an emitter terminal 1a. The output network 3 is connected to the collector terminal 1b and the base terminal 1c. The capacitor 1 is provided between the base terminal 1c and the reference potential, and switches the base terminal to the reference potential with respect to the operating frequency. Thus, transistor 1 operates at the singular frequency of the common base circuit.

The input network 2 comprises a tunable selection circuit 2a consisting of a circuit coil 2b, a double varactor 2c and capacitors 2d and 2e for transforming. The coil 2f is for the inductive output of the signal to the transistor 1. Resistor 2g determines the emitter current of transistor 1. Capacitor 2h bridges resistor 2g with respect to the signal frequency. The tuning voltage 2j for the tuning network 2 is supplied via the feed resistor 2i.

The output network 3 comprises a choke 3a through which an operating voltage is supplied to the transistor 1. Resistor dividers with resistors 3b and 3c are used to set the base potential of transistor 1. The collector of transistor 1 is connected by a capacitor 3d to a tunable resonant circuit 3e consisting of a circuit coil 3f, a double varactor 3g and capacitors 3h, 3i and 3j. The tuning voltage 3L is supplied to the circuit point 3m of the double varactor 3g via the feed resistor 3K, and the tuning potential of the anode terminal of the double varactor 3g is supplied via the resistor 3n. Is connected to. The circuit form of the output network 3 has a maximum (maximum transmission) frequency tuning capability of the output signal voltage at the circuit node 5 while a pole having minimum transmission above the tuning frequency occurs. N circuits are shown. Generally speaking, the circuit is designed such that a poll for minimum transmission occurs at the image frequency. In some embodiments of this type of circuit, a capacitor 30 is additionally inserted between the circuit point 1b and the circuit point 1c. This capacitor is connected by the dotted line in FIG.

The present invention is based on the fact that, in the conventional circuit of FIG. 1, several additional resonances in the frequency range exceeding the operating frequency range occur together with the intended tuning resonance in the operating frequency range, and in some situations cause parasitic self-oscillation. Shall be. In the higher frequency range, parasitic resonances of this type generally occur in both the input network and the output network of the amplifier circuit. This parasitic resonance is due to the parasitic capacitance and inductance that include the parasitic components of the amplifier element. Such resonance is a risk factor that causes parasitic resonances in connection with the inevitable interconnection between the output and input networks.

Even when using standard components consistently meeting certain design rules (eg for PCBs), we have experienced that such an amplifier circuit structure is not sufficiently safe from the occurrence of parasitic oscillations. It is an object of the present invention to provide a circuit that meets the condition that the parasitic self oscillation does not occur as much as possible while at the same time suppressing such parasitic self oscillation does not impair operating capability in the operating frequency range. The object is that a first capacitor is connected in series with the control system of the amplifier transistor, one inductance and a second capacitor are provided, the second capacitor together with the first capacitor and the inductance to form a parallel resonant circuit, the parallel The resonant circuit is achieved by an amplifier circuit having an amplifier transistor, configured to be connected in series with the control system of the amplifier transistor, wherein the resonant frequency of the parallel resonant circuit is higher than the operating frequency range of the amplifier circuit, and is free of inductance and second capacitors. It is chosen to be equal to the parasitic self-oscillation frequency that the amplifier circuit may have.

The invention is described below on the basis of examples.

FIG. 2 is an important part of the circuit according to FIG. 1 in which means for preventing the occurrence of parasitic self-oscillation and reduction of operating performance in the operating frequency range in accordance with the present invention are devised. This is different from the circuit according to FIG. 1 in that the inductance 10b is connected in series with the capacitor 10 in addition to the existing capacitor 10 according to the present invention. Another capacitor 10a is connected between the base terminal 1c and the reference potential. Inductance 10b may be designed as a separate component, or may be formed as the inductance of a feed line or the magnetic inductance of a capacitor. 2A shows an equivalent circuit of capacitor 10a having feed line inductances 10b ', 10b. The inductance 10b together with the capacitance of the capacitor 10a forms a parallel resonant circuit.

The impedance curve for the coupling of the switching elements 10, 10a and 10b according to the invention is shown in FIG. 3. The network exhibits series resonance at point 12 of frequency axis f and parallel resonance at point 13 with impedance curve 11. The operating frequency range fs is above the series resonance 12 and below the parallel resonance 13. Based on this arrangement, substantially only the inductance 10b is valid in the operating frequency range, so that the value of the inductance is large in view of the operating frequency range, for example with respect to the capacitor 30 of the circuit according to FIG. Can be chosen freely. By using a combination of inductance 10b and capacitor 30 capacitance, positive feedback can be set for the operating frequency range, which results, for example, in the amplification performance of the amplifier stage. In addition, the series resonant frequency can be freely selected in accordance with the present invention to obtain a constant characteristic in the circuit, for example in connection with recovery time operation when the prepreg is coupled to the Peruvian.

The parallel resonant frequency 13 causes the base of the transistor 1 to be separated from the reference potential due to the large impedance of the coupling according to the invention near the resonant frequency. Thus, the amplification of the system is correspondingly reduced in the range of parallel resonance frequency 13. If the parallel resonant frequency 13 is equal to or nearly equal to the parasitic oscillation frequency that the conventional circuit oscillates, the present invention has the effect of preventing parasitic self oscillation, and the parasitic resonant frequency 13 is generally of the operating frequency. In order to be multiplied, the invention virtually does not affect the operating frequency operation of the amplifier circuit. It has been observed that the risk of self-oscillation exists only at these frequencies, in which parallel resonance occurs at the output (circuit node 1b) or input (circuit node 1a) of the amplifier element above the operating frequency range in operation. Use of the present invention is advantageous for minimizing the risk of parasitic self-oscillation. In this case, the parallel resonance frequency 13 is preferably selected in the parasitic resonance frequency range of the input or output according to the invention. In addition, the parasitic parallel resonance, which poses the risk of causing parasitic oscillation, is 4-7 times higher than the operating frequency in the studied circuit.

For an operating frequency fs of 100 MHz, the circuit according to the invention used for the FM pre-stage can be designed as follows. ;

Parasitic Parallel Resonance (13)

fp = 5, 100 MHz = 500 MHz,

Base inductance (10b) LB = 10nH,

Base blocking capacitance (10) CB = 10 nF,

Based on the data we obtained:

The parallel capacitance 10 a CP is approximately 10 PF and the series resonant frequency 12 fs is 15.9 MHz.

4 shows an embodiment of the present invention. This is different from the circuit of FIG. 3 in that the resistor 10c is connected in series to the capacitor 10a. This resistor 10c has the effect of alleviating the parallel resonance 13. This may be advantageous when the system tends to be unstable in the frequency range due to the inherent series resonance of the capacitor 10a at a frequency above the parallel resonance frequency 13 becomes effective due to the magnetic inductance 10d of the capacitor 10a. . In an embodiment in which the connection between components of the circuit is a printed circuit system, it is preferable to set the required inductance of the line route from 1c through the capacitor 10 to the reference potential with proper conduction path dimensioning. Using SMD components for capacitors 10 and 10a a reproducible state is achieved in this way.

5 is a variant of the circuit according to FIG. 4. In the circuit according to FIG. 5, the capacitor 10 is connected in parallel to the inductance 10e. In this case, the magnetic inductance of the capacitor 10 is not included in the parallel resonant circuit. This circuit may be desirable in some arrangements.

6 shows another embodiment of the present invention. This is different from the circuit of FIG. 4 in that a resistor 1d is provided to the collector line of the transistor 1. This resistor prevents the risk of parasitic oscillation, especially for frequencies much higher than the parallel resonant frequency 13. The fact that the effect of this resistor occurs (and is needed) at frequencies much higher than the operating frequency causes the value of this resistor to be chosen very low (e.g. 10-50 ohms). This result has the advantage that the effect of the resistor can be kept negligibly small over the operating frequency range.

7A is a circuit according to the present invention, in which the parallel resonance 13 is generated by a parallel resonance circuit composed of an inductance 1e and a capacitance 1f in the base feed of the transistor 1. The elements 1e and 1f and the resistor 1d may be integrated with the transistor 1, for example.

A suitable embodiment is shown in FIG. 7B. The transistor 1, the capacitor 1f and the resistor 1d are monolithically integrated in the substrate element s. The components are connected by vapor deposited conductive passages, and the inductance 1e is formed by the spiral conductive passage from the transistor base terminal 1c 'to the transistor connection terminal 1c via the bonding pad and the connection wire 1g. . The capacitor 1f is connected to the internal base terminal 1c 'by one terminal and to the transistor terminal 1c via the bonding pad 1h and the connection wire 1i by the other terminal. Since the parallel resonant frequency 13 is determined by the inductance sum of the elements 1e, 1g and 1i with respect to the capacitance of the capacitor 1f in the arrangement according to FIG. 7b, the resonant frequency is determined by the connection wires 1g and 1i. Can be affected by length and diameter. In the arrangement according to FIG. 7b, it is also possible to switch off the integrated parallel resonant circuit by not forming a connection 1i if necessary.

In another embodiment of the invention, as in the embodiment according to FIG. 4, the resistor 10c shown in FIG. 4 may be integrated in the same way in series with the integrated capacitor 1f.

The present invention can be applied to the amplifier circuit in the same way, where a field effect transistor is used as the amplifier element instead of the bipolar transistor. In this case, the gate source and drain connections of the field effect transistor correspond to the base, emitter and collector connections of the bipolar transistor.

Claims (18)

A first capacitor is connected in series with the control system of the amplifier transistor, one inductance and a second capacitor are provided, the second capacitor together with the first capacitor and the inductance form a parallel resonant circuit, the parallel resonant circuit being In an amplifier circuit having an amplifier transistor, configured to be connected in series with a control system of an amplifier transistor, the resonant frequency of the parallel resonant circuit is higher than the operating frequency range of the amplifier circuit, and the amplifier circuit will have no inductance and no second capacitor. An amplifier circuit, characterized in that it is selected equal to the parasitic oscillation frequency. 2. The amplifier circuit of claim 1 wherein the resonant frequency is higher than the operating frequency. 3. The amplifier circuit of claim 2, wherein the resonant frequency is four to seven times the operating frequency. 4. The amplifier circuit of claim 3, wherein the resonant frequency corresponds to one of the parasitic parallel resonant frequencies at the input of the amplifier transistor, and wherein the second capacitor is connected in parallel with the first capacitor. 4. The amplifier circuit of claim 3, wherein the resonant frequency corresponds to one of the parasitic parallel resonant frequencies at the output of the amplifier transistor, and wherein the second capacitor is connected in parallel with the first capacitor. 6. The amplifier circuit according to claim 4 or 5, wherein the inductance is formed by the inductance of the lead wire with respect to the first capacitor. The amplifier circuit according to claim 4 or 5, wherein a separate inductance is provided in series with the first capacitor, and a second capacitor is connected in parallel with the inductance. 7. The amplifier circuit of claim 6 wherein the resistor is connected in series with the second capacitor. 9. The amplifier circuit of claim 8 wherein the resistor is connected in series with the output electrode of the transistor. 10. The amplifier circuit of claim 9, wherein the capacitance of the first capacitor is greater than the capacitance of the second capacitor. 11. The amplifier circuit of claim 10 wherein the capacitance of the first capacitor is at least ten times greater than the capacitance of the second capacitor. 12. The amplifier circuit of claim 11 wherein the inductance is formed of a strip conductor. 8. The amplifier circuit of claim 7, wherein the resistor is connected in series with the second capacitor. 14. The amplifier circuit of claim 13 wherein the resistor is connected in series with the output electrode of the transistor. 15. The amplifier circuit of claim 14 wherein the capacitance of the first capacitor is greater than the capacitance of the second capacitor. 16. The amplifier circuit of claim 15 wherein the capacitance of the first capacitor is at least ten times greater than the capacitance of the second capacitor. 17. The amplifier circuit of claim 16 wherein the inductance is formed of a strip conductor. A first capacitor is connected in series with the control system of the amplifier transistor, and an inductance and a second capacitor are provided, the inductance and the second capacitor being a parallel resonant circuit in series with the first capacitor and with the control system of the amplifier transistor. In an amplifier circuit having an amplifier transistor connected in series, the parallel resonant circuit configured to be connected in series with a control system of an amplifier transistor, wherein the resonant frequency of the parallel resonant circuit is higher than an operating frequency range of the amplifier circuit, and the inductance and The amplifier circuit is selected to be equal to the parasitic oscillation frequency that the amplifier circuit can have in the absence of a second capacitor.

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