KR0134092Y1 - Radiator of semiconductor package - Google Patents
Radiator of semiconductor package Download PDFInfo
- Publication number
- KR0134092Y1 KR0134092Y1 KR2019940034332U KR19940034332U KR0134092Y1 KR 0134092 Y1 KR0134092 Y1 KR 0134092Y1 KR 2019940034332 U KR2019940034332 U KR 2019940034332U KR 19940034332 U KR19940034332 U KR 19940034332U KR 0134092 Y1 KR0134092 Y1 KR 0134092Y1
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- KR
- South Korea
- Prior art keywords
- semiconductor package
- heat sink
- marking
- semiconductor chip
- present
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 고안은 반도체 패키지 제품의 제조국명, 일련번호 등을 표시하는 마킹표식이 형성된 반도체 패키지 내장형 방열판에 관한 것으로, 반도체 패키지를 구성하는 방열판(1)의 저면에 요홈(2)을 형성하고 그 요홈(2)의 내표면에 소정의 마킹표식이 이루어지도록 함으로써 종래 이젝트핀에 의한 마킹방식에 비해 보다 명확한 선명도를 갖는 마킹표식이 실시되도록 함과 동시에 이젝트 부위의 플러쉬 발생문제를 해결하고, 나아가 작업의 편의성을 제공하여 제품의 품질향상과 작업능률의 향상을 가져올 수 있도록 한 것이다.The present invention relates to a semiconductor package built-in heat sink having a marking mark indicating the manufacturing country name, serial number, etc. of a semiconductor package product, and forms a recess (2) in the bottom surface of the heat sink (1) constituting the semiconductor package and the recess ( By making a predetermined marking mark on the inner surface of 2), a marking mark having a clearer sharpness can be implemented as compared to the marking method by a conventional eject pin, and at the same time, the problem of flush occurrence of the ejection part is solved, and further convenience of work is performed. In order to improve the quality of the product and improve the work efficiency.
Description
제1도의 (a)는 종래의 방열판이 내장된 쿼드형 반도체 패키지의 저면도.FIG. 1A is a bottom view of a quad type semiconductor package in which a heat sink is mounted.
(b)는 종래의 방열판이 내장된 쿼드형 반도체 패키지의 단면도.(b) is a cross-sectional view of a quad-type semiconductor package with a built-in heat sink.
(c)는 제1도 (b)의 가부분 확대도.(c) is an enlarged partial view of FIG. 1 (b).
제2도의 (a)는 종래의 방열판이 내장된 듀얼형 반도체 패키지의 저면도.FIG. 2A is a bottom view of a dual semiconductor package in which a heat sink is mounted.
(b)는 종래의 방열판이 내장된 듀얼형 반도체 패키지의 단면도.(b) is a cross-sectional view of a dual-type semiconductor package with a conventional heat sink.
(c)는 제2도 (b)의 나부분 확대도.(c) is an enlarged partial view of FIG. 2 (b).
제3도는 본 고안의 방열판을 이용한 리드프레임자재를 몰드금형에 삽입시킨 상태를 보여주는 단면도.3 is a cross-sectional view showing a state in which a lead frame material using a heat sink of the present invention is inserted into a mold mold.
제4도의 (a)는 본 고안의 방열판이 내장된 쿼드형 반도체 패키지의 저면도.Figure 4 (a) is a bottom view of a quad type semiconductor package with a heat sink of the present invention.
(b)는 본 고안의 방열판이 내장된 듀얼형 반도체 패키지의 저면도.(b) is a bottom view of a dual semiconductor package with a heat sink according to the present invention;
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 방열판 2 : 마킹요홈1: heat sink 2: marking groove
3 : 상부몰드금형 4 : 하부몰드금형3: upper mold mold 4: lower mold mold
5 : 이젝트핀5: eject pin
본 고안은 반도체 패키지 내장형 방열판에 관한 것으로, 특히 선명한 마킹표식을 유지할 수 있는 마킹요홈을 방열판에 형성하고, 이 마킹요홈에 몰딩시 플러쉬가 형성되지 않은 반도체 패키지 내장형 방열판에 관한 것이다.The present invention relates to a semiconductor package embedded heat sink, and more particularly, to a marking recess for maintaining a clear marking mark on a heat sink, and to a semiconductor package embedded heat sink having no flush when molded in the marking groove.
일반적으로 완성된 반도체 패키지 제품에는 반도체의 제조국형, 일련번호 등을 마킹하게 된다. 즉, 반도체 패키지의 제조공정중 하나인 몰딩공정에서 금형형상으로 반도체 패키지가 성형되는데, 이때 반도체 패키지가 금형에서 잘 떨어지도록 금형상에 구비된 이젝트핀이 패키지가 성형되는데, 이때 반도체 패키지가 금형에서 잘 떨어지도록 금형상에 구비된 이젝트핀이 패키지의 저면을 이젝트하는 과정에서 이젝트핀의 첨두 면에 새겨진 표식에 의해 패키지 표면에는 고유의 마킹요홈(10)이 형성되게 된다.In general, the finished semiconductor package product is marked with the manufacturing country, serial number, etc. of the semiconductor. In other words, the semiconductor package is molded into a mold in a molding process, which is one of the manufacturing processes of the semiconductor package. At this time, the eject pins provided on the mold are molded so that the semiconductor package falls off from the mold. In the process of ejecting the bottom surface of the package, the eject pin provided on the mold so as to fall off by the marking engraved on the peak surface of the eject pin to the unique marking groove 10 is formed on the surface of the package.
그러나, 제1도와 제2도의 (c)에 예시한 바와같이 패키지의 표면에 형성된 요홈(10)에는 그 주변으로 몰딩컴파운드의 찌꺼기인 플러쉬(11)가 형성되는 문제점을 안고 있다. 즉, 상기한 마킹요홈(10)이 몰딩컴파운드의 저면에 형성됨으로써, 플러쉬(11)의 형성을 가중시킨다. 또한, 마킹표식이 몰딩시 만들어지기 때문에 이젝트핀의 청결도에 의해 마킹상태가 심한 차이를 보이는등 마킹 선명도상의 문제가 있었다.However, as illustrated in (c) of FIG. 1 and FIG. 2, the recess 10 formed on the surface of the package has a problem in which the flush 11, which is a residue of the molding compound, is formed around the recess 10. That is, the marking groove 10 is formed on the bottom surface of the molding compound, thereby increasing the formation of the flush 11. In addition, since the marking mark is made during molding, there is a problem in the sharpness of the marking, such as a marked difference in the marking state due to the cleanliness of the eject pin.
이에, 본 고안에서는 상기의 문제점을 해결하기 위하여 반도체 패키지에 내장되는 방열판 표면에 미리 요홈을 형성함으로써, 선명한 마킹표식이 가능토록 하고, 이러한 요홈이 이젝트핀의 몰드컴파운드에 직접 접촉되지 않도록 함으로써, 이젝트로 인한 플러쉬 생성문제를 완전 해결할 수 있는 반도체 패키지 내장형 방열판을 제공함에 그 목적이 있는 것이다.Accordingly, in the present invention, in order to solve the above problems, by forming grooves on the surface of the heat sink embedded in the semiconductor package in advance, a clear marking mark is possible, and the grooves do not directly contact the mold compound of the eject pin, thereby ejecting The purpose of the present invention is to provide a heat sink having a semiconductor package that can completely solve the problem of flush generation caused by the chip.
이러한 목적을 달성하기 위한 본 고안의 구성은, 전자회로가 집적되어 있는 반도체칩과, 상기한 반도체칩의 신호를 외부로 전달하는 리드와, 상기한 리드와 반도체칩의 신호를 전기적으로 연결해주는 와이어와, 상기 반도체칩의 회로동작시 발생되는 열을 외부로 방출하도록 반도체칩의 저면에 부착된 방열판과, 상기한 반도체칩과 그 외의 구성 부품들의 회로적 성질 및 기능적 특성을 보호하기 위하여 컴파운드재로 감싸진 반도체 패키지를 구성함에 있어서, 상기한 방열판의 저면에는 몰딩시 몰딩컴파운드가 접촉되지 않는 위치의 중앙부에 선명한 마킹표식을 할 수 있는 마킹요홈을 더 형성한 것이다.The structure of the present invention for achieving this purpose is a semiconductor chip in which the electronic circuit is integrated, a lead for transmitting the signal of the semiconductor chip to the outside, and a wire for electrically connecting the signal of the lead and the semiconductor chip And a heat sink attached to the bottom surface of the semiconductor chip to radiate heat generated during the circuit operation of the semiconductor chip to the outside, and to protect the circuit properties and functional characteristics of the semiconductor chip and other components. In forming the enclosed semiconductor package, the bottom surface of the heat sink is further formed with a marking groove for clearly marking marking in the center of the position where the molding compound is not in contact with the molding.
이하, 본 고안을 첨부 예시 도면에 의해 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 고안은 반도체 패키지를 구성하는 방열판(1)의 저면 중앙부에 마킹요홈(2)을 형성하고, 이 요홈(2)의 표면에 소정의 마킹표식을 한다. 이러한 마킹요홈(2)은 몰딩시 몰딩컴파운드가 접촉되지 않는 위치에 형성됨으로서, 명확한 선명도를 갖는 마킹표식이 가능해지는 것이다.In the present invention, the marking groove 2 is formed in the center of the bottom surface of the heat sink 1 constituting the semiconductor package, and a predetermined marking is made on the surface of the groove 2. The marking groove 2 is formed at a position where the molding compound is not in contact with the molding, so that marking markings with clear clarity are possible.
즉, 본 고안에서는 상하부몰드금형(3)(4)을 사용하여 리드프레임자재의 몰딩 공정을 수행하는 과정에서 몰딩이 진행되지 않는 금속성의 방열판 저표면에 마킹요홈(2)이 형성되기 때문에 몰딩시 몰딩컴파운드와의 접촉이 없어 명확한 마킹표식의 선명도를 유지할 수 있는 것이며, 아울러 마킹이 지워지는 등의 문제점이 발생하지 않게되는 것이다.In other words, in the present invention, the molding recesses 2 are formed on the bottom surface of the metallic heat sink in which the molding is not performed in the process of molding the lead frame material using the upper and lower mold molds 3 and 4. There is no contact with the molding compound to maintain the sharpness of the clear marking markers, and also to avoid the problems such as erasing the marking.
또한, 본 고안은 반도체 패키지의 표면에 이젝트핀에 의한 마킹표식을 하지 않음으로써, 히트싱크가 내장된 초소형 반도체 패키지 제조시에는 더욱 효과적이며, 몰드금형상의 이젝트핀은 반도체 패키지 성형후, 이젝트 용도로만 사용하게 되므로, 다품종생산에 따른 다종류의 마킹된 이젝트핀을 구비하지 않아도 되는 이점이 있는 것이다. 뿐만 아니라, 상기한 마킹요홈(2)에 이젝트핀(5)이 삽입되면서 반도체 패키지를 이젝트하도록 함으로써, 정확한 이젝트를 할 수 있는 장점도 있는 것이다.In addition, since the present invention does not mark the surface of the semiconductor package by eject pins, the present invention is more effective in manufacturing a micro semiconductor package having a heat sink, and the mold mold eject pins are only used for ejecting after forming a semiconductor package Since it is used, there is an advantage that it is not necessary to have a variety of marked eject pins according to the production of a variety of varieties. In addition, by ejecting the semiconductor package while the eject pin 5 is inserted into the marking groove 2, there is an advantage that can be accurately ejected.
상술한 바와같은 본 고안은 반도체 패키지를 제조함에 있어서 제조원가를 절감할 수 있고, 아울러 금속성의 방열판 저면에 마킹요홈을 형성하고, 이 마킹요홈에는 몰딩컴파운드가 직접 접촉되지 않음으로써, 이젝트핀 부위의 플러쉬 발생문제를 해결할 수 있는 등 선명한 마킹표식으로 인한 반도체 패키지 제품의 품질향상과 작업능률을 향상시킬 수 있게 되는 것이다.The present invention as described above can reduce the manufacturing cost in manufacturing a semiconductor package, and also forming a marking groove on the bottom surface of the metal heat sink, the molding compound is not directly in contact with the marking groove, the flush of the eject pin portion It is possible to improve the quality and work efficiency of semiconductor package products by virtue of clear marking marking such as to solve the problem of occurrence.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019940034332U KR0134092Y1 (en) | 1994-12-16 | 1994-12-16 | Radiator of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019940034332U KR0134092Y1 (en) | 1994-12-16 | 1994-12-16 | Radiator of semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960025529U KR960025529U (en) | 1996-07-22 |
| KR0134092Y1 true KR0134092Y1 (en) | 1999-01-15 |
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ID=19401608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019940034332U KR0134092Y1 (en) | 1994-12-16 | 1994-12-16 | Radiator of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0134092Y1 (en) |
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1994
- 1994-12-16 KR KR2019940034332U patent/KR0134092Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR960025529U (en) | 1996-07-22 |
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