KR0133521B1 - Burst error adjusting circuit and method - Google Patents

Abstract

No content.

Description

Burst Error Correction Circuit and Method

1 is a conventional burst error correction circuit diagram.

FIG. 2 is a circuit diagram of the error pattern detector of FIG.

FIG. 3 is an explanatory diagram showing an example of an operation in which the error pattern detection unit of FIG. 1 detects an error pattern in data. FIG.

4 is a burst error correction circuit diagram of the present invention.

5 is a circuit diagram of an error pattern detection unit of FIG.

FIG. 6 is an explanatory diagram showing an example of an operation in which the error pattern detection unit of FIG. 4 detects an error pattern from data. FIG.

7 is a signal flow diagram for FIG.

* Explanation of symbols for main parts of the drawings

1,1 ': Error pattern detector 2,2': Shift register

3: comparator 4,6: counter

5: forefront detector 7: error position calculator

8: latch 9: microcomputer

The present invention relates to a burst error correction circuit and method for correcting a burst error caused by scratches or defects of a storage medium itself when data stored in a storage medium such as a disk or a tape is read. In particular, the present invention relates to a burst error correction circuit and a method using a fire code that enables a high speed correction of a burst error using a fire code.

FIG. 1 is a conventional burst error correction circuit, which is composed of a central processing unit 4c, a data input port 4a, an input / output control port 4b, and a tire 4d as shown in FIG. A microcomputer 4 to control, an error pattern detection unit 1 for detecting an error pattern by dividing the data X read in the recording medium into a given generation polynomial, and a latch 3 for storing data X, and the error pattern A shift register 2 for shifting the output signal of the detector 1 to the microcomputer 4 and a counter 5 for counting the number of bits shifted by the sound shift register 2 and inputting the microcomputer 4 to the microcomputer 4; ), And the OR gates OR1 (OR2)..., Which are inputted to the microcomputer 4 by ringing the number of bits and the ground of the shift register 2. It is comprised as (ORn-m).

Referring to the operation of the conventional burst error correction circuit configured as described above and the problems as follows.

When multiplying the generated polynomial g (x) of Firecode by reading and inputting the data X stored in the recording medium, the input data X is divided by the generated polynomial g (X) by the error pattern detection unit 1, The burst error pattern E (X) is output.

For example, assuming that the generated polynomial g (X) = X3 + X + 1, it is composed of a divider circuit as shown in FIG. 3, and it is assumed that the data X read from the recording medium is X4 + X2 + 1. The data X is instantaneously shifted and is stored in the latches 1a-1c. When is input and shifted next, 1 outputted from the latch 1c is added to the adder 1d-1c to latch 1a-. Is stored in 1c). When 1 is finally inputted, L is output from the latch 1c, so that the latches 1a-1c are stored and output.

The microcomputer 4 reads the data X stored in the recording medium, sequentially stores the data X in the latch 3, inputs the same to the air pattern detector 1, and the error pattern detector 1 generates the data X. When the remaining error pattern is output by dividing by g (X), the output error pattern is inputted to the shift register 2, shifted to each bit Bl-Bn, and the counter 5 is counted. Input to the microcomputer 4, when the count of the counter 5 is n, the microcomputer 4 detects that the shift to the last bit (Bn) of the shift register 2, the terminal (Il-) of the data port (4a) After setting In-m to the input mode, it is determined whether the signals of the bits Bl-Bn-m of the shift register 2 are all through the oragate ORl-ORn-m, and at this time, the bits Bl- When the signals of Bn-m) are not all, the signals stored in the shift register 2 are cyclically shifted one by one. The counter 5 determines whether the signals of each bit Bl-Bn-m are all the same, and counts the counter 5 2n-m, that is, the shift register 2 completely shifts one revolution. Until all the signals of the bits B1 -Bn-m are not equal, the data X determines that correction is impossible and stops. If the signals of the bits B1 -Bn-m are all, then the position 5 of the counter 5 subtracts n + 1 from the counted number to find the position I where the error occurred, and the terminal (In-n + of the data port 4a0). Raising 1- (n) to the input mode, inputs the signal of bits Bn-M + 1-Bn of the shift register 2, and outputs the terminal Ii-Ii + t-1 of the data port 4a. After setting the mode, the signal of the input bits (Bn-m + 1-Bn) is output and the error is corrected.

That is, for example, an error occurs when the actual data is, and when the error pattern is obtained, the error pattern is. The error pattern is output by the microcomputer 4, and the original data is corrected by adding to each bit.

However, in such a conventional bit error correction circuit, there is only one error pattern detection unit and no error position register. Therefore, the error correction capability is greatly limited. In fact, in error correction, the error pattern detection unit is divided into an error pattern detection unit and a contract polynomial. It is not only possible to correct the error properly by changing the parameter of the error pattern detection unit as a coefficient, but also because there is no provision of the fore-field detection unit, it is necessary to shift the number of code words so that the error is finally corrected. .

In view of such a conventional problem, the present invention includes two error detection units (XC + 1) and stores the remainder divided by P (X) in the error pattern register and the error position register, respectively, It is designed to reduce the error correction time to the maximum by checking the status of all counters as a counter and indicating the timing at that time, so that error correction can be checked even if only the maximum value of the calculation time is shifted. Hereinafter, the structure of the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram of a burst error correction circuit of the present invention, and FIG. 5 is a circuit diagram of a fourth error pattern detection unit. As shown therein, a central processing unit 9c, a data port 9a, an input / output control port 9b, and The microcomputer 9, which is composed of a timer 9d and the like, controls the operation of the entire system, and latches 1a and 1b in order to detect an error pattern by dividing the data X read on the recording medium by a given generating polynomial. )… (1C2 + 1), adder 1d (1E)... An error pattern detection unit 1 (1 ') composed of (1E2 + 1), a latch 8 for inputting and storing the data X as an input, and an output from the error pattern detection unit 1 (1'). Shift registers (2) and (2 ') which read the received signals through the adders (10) and (10'), shift them and input them to the microcomputer (9), and the shift registers (2) and (2 ') are shifted. A comparator 3 which compares and outputs the value of the number of bits, a counter 4 which detects a point of time when the output of the comparator 3 is ψ, and counts the number of clocks until the counter is reached, and the shift register 2 A counter detector 5 which checks whether the state of all of? Is detected, a counter 6 which detects and counters the point of time when the output of the counter detector 5 is ψ, and is output from the counter 4 and 6; The error position calculation unit 7 calculates an error position based on the signal and inputs it to the microcomputer 9.

Referring to Figure 7 the operational effects of the present invention configured as described above are as follows.

보다 작지 않고 또한 P(X)는 (Xc+1)을 나누지 않은 GF(q) 상에서 정의되는 기약다항식(prime polynomial)이며 GF는 유한필드(galois field)를 의미하고, q는 유한필드 GF 상에서 정의되는 원소의 개수를 의미한다. 그리고 파이어 포드의 블록길이는 (Xn+1)이 g(x)를 나누는 가장 작은 정수 n으로 되고, 여기서 에러정정이 가능한 원소의 수는

개로 정의되므로 p(x)의 차수를

보다 작지 않은 값으로 m이라 하면 P(X) = P0+P1.X+…+Pm.X^m으로 표현할 수 있으므로 생성다항식 g(x)는 다음의 식과 같이 표현될 수 있다.The fire code is first described, and in general, the fire code is generated as a cyclic burst correcting code defined on GF (q). The polynomial is g (x) = (Xc + 1). . Is defined as P (X), where P (X) is the largest order m

P (X), which is not less than, is also a prime polynomial defined on GF (q) without dividing (Xc + 1), GF means a galois field, and q is defined on a finite field GF. It means the number of elements to be. And Fireford's block length is the smallest integer n where (Xn + 1) divides g (x), where the number of elements

Is defined as, so the degree of p (x)

If m is not less than P (X) = P0 + P1.X +. Since it can be expressed as + Pm.X ^m , the generated polynomial g (x) can be expressed as

g (x) = (X ^c +1) .P (X) = (Xc + 1). (Po + P1.X ... + Pm.X ^m ) = Pm.X ^{c + m} +. + po

In the above formula, the coefficients go, g1... gz produces data X as shown in FIG. 5 polynomial G (X) = (Xc + 1). A division circuit divided by P (X) can be constructed.

If the receiver is R (X), then R (X) = V (X) + X ⁱ . B (X) (B (X): Burst Error Pattern Polynomial) is expressed as V (X) represents the sender. If B (X) is ψ, R (X) = V (X), and if B (X) is not ψ, Xi.B (X) / (Xc + 1) and Xi.B (X) in the shift register The remainder of / P (X) remains respectively.

If the burst error correction capability of this code is S1 and the burst error detection capability is S2 (S≥S1), then S1 (X) .X ^mi = X ⁿ .B (X) = [B (X) ÷ ( X ^{c + 1} )], S2 (X). Since Xn-i = Xn.B (X) = [B (X) ÷ P (X)], it is known that the comparison values of the comparators coincide by ni shifts.

Here, if P (X) = X ³ + X + 1, a divider circuit as shown in FIG. 6 is formed, and if the input data is 1ψ1ψ, that is, X ⁴ + X ² +1, the data X is sequentially shifted 1? 1? 1 is stored in the latches 1a, 1b, 1c formed in the error pattern detection unit 1 (1 '), and when? Is input and shifted, 1 output from the latch 1c is added to the adder 1d. In the latch 1a, 1b, and 1c, 1ψψψ1 is stored, and when 1 is input, ψ is outputted from the latch 1c, so the latches 1a, 1b, 1c are 11ψ. That is, the remaining 1 + X is stored and output.

As shown in FIG. 7, the microcomputer 9 reads the data X stored in the recording medium and sequentially stores the data X in the latch 8 and inputs them to the error pattern detection unit 1 (1 '). The detection unit 1 (1 ') outputs data obtained by dividing the data X into the polynomials Xc + 1 and P (X) in an error pattern and stores the data in the shift register 2 (2'). The comparator 3 then shifts the shift registers 2 and 2 'and checks whether the values match with the counter 4, and if they match, sets the value to? It is checked whether the output of? Becomes?, And the value of the counter 6 at the time when the output of the foreground detector 5 becomes? Is set to?. After that, the error positions are calculated by using the error position calculating unit 7, and λψ and λ1 output from the counters (4) and (6) are used. Error correction. Here, λψ = 1-i = -i mode becomes C and λ1 = 1-i = -i mode 1. If the values in -i mode, C, and mode 1 are λψ and λ1, -i = λψAψ1 + λ1A1C mode is obtained.

Where A? And A1 are A? 1 = A1C = 1, that is, mode n is an integer. As a result, the error position detection unit 1 (1 ') stores the A? In advance and substitutes the shift times?? And? 1 to determine the error position i. When i is detected, the microcomputer 9 reads the counter 4 value and the error pattern from the comparator 3.

In other words, this error pattern is multiplied by X ⁱ using the error position i to obtain the correct error pattern. By finalizing this value exclusively to the latch 8 value, the final corrected code value can be obtained.

Claims (2)

In the burst error correction circuit configured as a microcomputer (9) for controlling system operation and a latch (8) for storing data, the data read from the recording medium is divided into (X ^c +1) and P (X) to divide the error pattern. An error pattern detector (1) 1 'to be detected, a shift register (2) (2') for shifting an output signal of the error pattern detection book (1) (1 '), and the shift register (2) ( A comparator 3 for comparing the number of bits of 2 '), a counter 4 for counting coincidence points of the comparator 3, a foreground detector 5 for checking the state of the shift register 2, and A counter 6 for detecting the point of time when the output of the foreground detector 5 is ψ, and an error position calculation unit 7 for calculating an error position by inputting the outputs of the counters 4 and 6; A burst error correction circuit characterized by the above. The data X read from the recording medium is divided into the generated polynomials, the remaining error patterns are detected, and the two comparators are compared using the comparator 3 while shifting to the shift registers 2 and 2 '. To determine the position of the error in accordance with the matching time, and then check the state of the electrophoretic detector (5) which checks whether the state of the shift register (2) (2 ') or c-1 stage is applied. The error position i is detected by the error position calculation (7) which calculates the error position from the value of (6), and finally the error position i and the shift register (2) (2 ') are used by the microcomputer (9). A burst error correction method characterized by correcting a burst error within a maximum number of (1,1-c) shifts.

Images