KR0116662Y1 - Error detecting decoder - Google Patents

Abstract

The present invention relates to an error detection code decoder for implementing high-speed processing by performing error discrimination of data recorded on various recording media in parallel.

The present invention divides an error detection parallel data into an order of a function by separating the most significant bit from the least significant bit from the first register to temporarily store and output the data after synchronizing with the input clock. An order error detection code decoding means for outputting a result signal, and an error discriminating means for determining whether or not there is an error as a result value by ORing the data output from the order error detection code decoding means.

Description

Error detection code decoder

1 is a block diagram of a conventional error detection code decoder.

FIG. 2 is a view showing results of calculating received information m (11000001) when the circuit redundancy code is 16 and P (X) = X ¹⁶ + X ¹⁵ + X ² +1 according to FIG.

3 is a block diagram of the present invention error detection code decoder.

4 is a detailed configuration diagram of the sequence error detection code decoder of FIG.

5 is a diagram showing the result of calculating the reception information m (11000001) when the circuit redundancy code is 16 and P (X) = X ¹⁶ + X ¹⁵ + X ² +1 according to FIG.

Explanation of symbols for main parts of the drawings

100: 8-bit register 200: Sequence error detection code decoding section

300: 16 bit Register 400: Error discrimination unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection code decoder, and more particularly, to an error detection code decoder for implementing high-speed processing by performing error discrimination of data recorded on various recording media in parallel.

Generally, when recording information on various recording media, an error detection code (hereinafter abbreviated as EDC) decoder for determining the presence or absence of an error is provided.

Thus, errors occurring in the process of recording the information, the transmission, and the reception processing are determined so that the reliability of the data can be determined and the error can be corrected when an error occurs.

In the EDC decoder, a cyclic redundancy code (hereinafter abbreviated as CRC) is typically used.

In other words, when the information field is C = (C _k , C _k-1 , C _k-2 … C ₁ , C _o ), if this is expressed as polynomial, c (x) = (C _k X ^k + C _k-1 X ^k-1 +… + C ₂ + X ² + C ₁ X + C ₀ .

Dividing by the CRC function P (X) of order nk, (cx) X ^nk = P (x) q (x) + r (x)... … Represented by equation (1), m (x) = C (x) X ^n- r (x) = C (X) X ^nk + r (x) = q (x) p (x)... … Equation (2) is obtained.

Subtraction in the binary system in Equation (2) can be expressed as addition, so c (x) -r (x) and c (x) + r (x) are equivalent.

At this time, the order of m (x) is n when the order k of the information field is multiplied by the order n-k of the CRC function.

therefore,

m (x) = m _n X ⁿ + m _n-1 X ^n-1 +... … + m ₁ x + m _o ,

m = (m _n , m _n-1 , m _n-2 , …… m ₁ , m _o ).

In the case of error discrimination, if the received information is m '(x), this is divided by the CRC function P (X) to determine whether there is a remainder.

That is, if m '(x) = m (x), it is determined that there is no error because m' (x) = p (x) q (x). If m '(x) ≠ m (x), p (x) If you divide by), it is determined that an error occurs because the remainder exists.

FIG. 1 is a block diagram of a conventional error detection code decoder that detects an error in data as described above. As shown in FIG. 1, an exclusive logical sum of the data finally outputted and the serial data inputted therein is provided. An exclusive oragate 1, a first shift register 2 temporarily storing the output data of the first exclusive oragate 1, data temporarily stored in the first shift register 2 and the first data; A second exclusive oragate 3 for exclusively ORing the output data of the one exclusive oragate 1 and outputting the resultant signal, and a second for temporarily storing the output data of the second exclusive oragate 3; A third exclusive error that exclusively ORs the shift register 4, the output data of the second shift register 4, and the output data of the first exclusive oragate 1, and outputs the resultant signal. A third shift register 6 for temporarily storing and outputting the gate 5 and the output data of the third exclusive oragate 5 and feeding back the final exclusive data to the first exclusive oragate 1; And an orifice 7 for ORing each output bit of the first to third shift registers 2, 4 and 6 and outputting the resultant signal as an error discrimination value.

The operation of the conventional error detection code decoder configured as described above will be described in detail with reference to FIG. 2.

First, FIG. 1 is an EDC using P (X) = X ¹⁶ + X ¹⁵ + X ² +1, which is CRC16 (order C function is 16).

When the reception information 10000011 is passed in series, division is performed as a result, and the remainder is stored in the first to third shift registers 2, 4, and 6.

That is, the reception information 10000011 is exclusively ORed with the remaining data finally output from the third shift register 6 in the first exclusive orgate 1 so that the resultant signal is the first or second exclusive orifice 3. Is fed back to (5).

In addition, by first XOR Iowa output data of the gate (1) it is the first to the third shift register (2) (4) is stored in (6), once calculated the stored value (X ⁰ ~ X ¹⁵⁾ each is right one place You will be moved.

When all the data is completed by performing this shift, the remainder of the division is left in the first to third shift registers 2, 4 and 6.

The determination of the presence or absence of an error is determined by determining whether the remainder is 0 or not, so that all of the stored values (X ⁰ to X ¹⁵ ) are logically summed with the oragate 7 and then the result is determined.

2 is a value stored in the first to third shift registers (2) (4) (6) when all received information passes through the EDC decoder when the received information m (x) is m (x) = (11000001). The change is shown.

However, since the conventional error detection code decoder processes data to detect an error in serial, if the processed data is parallel, the data must be converted to serial data and processed. Therefore, there is a time delay due to serial conversion, which makes fast data processing impossible. there was.

For example, if the processing data is 8 bits, an additional 1/8 size clock is required for serial processing. In the case of high speed processing, the size of the clock processing 8 bits is 200 to 300 ns. A 40ns clock is required.

However, considering the stability of data processing, it is difficult to use a clock of 30-40 ns.

Accordingly, an object of the present invention is to solve the above-described problems, and an object of the present invention is to enable error detection of data recorded on various recording media in parallel so that high-speed data processing is possible. In providing.

Means for achieving the object of the present invention is a function that separates the first bit from the least significant bit to the most significant bit from the output data of the first register and the first register to temporarily store the error detection data in synchronization with the input clock It is achieved by a sequence error detection code decoding means for dividing by the order of and outputting a signal, and an error discriminating means for determining the presence or absence of an error by logically combining the data output from the sequence error detection code decoding means. Based on the accompanying drawings of the invention in detail as follows.

3 is a block diagram of an error detection code decoder of the present invention. As shown in FIG. 3, an 8-bit register 100 for temporarily storing input 8-bit data Data in synchronization with a clock CLK and outputting the same is shown in FIG. The first to eighth bits of the 8-bit data [7: 0] output from the bit register 100 are divided by the order of the function by separating the least significant bit (bit0) from the most significant bit (bit7) and outputting the resultant signal. 16-bit data output from the sequence error detection code decoding unit 200 including the sequence error detection code decoders 201 to 208 and the eighth sequence error detection code decoder 208 of the sequence error detection code decoding unit 200. And a 16-bit register 300 for temporarily storing the data in synchronization with a clock CLK and feeding back the data D [15: 0] to the first sequence error detection code decoder 201, and the sequence error detection code. Logic 16-bit data output from the decoding unit 200. W formed the resulting signal to the error detection unit 40 and outputting a data error determination value.

The operation and effects of the inventive error detection code decoder constructed as described above will be described in detail with reference to FIGS. 4 and 5.

First, when the input data for detecting an error is 8 bits (D [7: 0]), the 8-bit register 10 synchronizes the input 8-bit data D [7: 0] with the clock CLK. After saving temporarily, it outputs as 8-bit parallel data.

The 8-bit parallel data output from the 8-bit resister 100 is the sequence error detection code decoder 200 to separate the upper and lower bits of the 8-bit parallel data first to eighth order error detection code decoder 201. ~ 208).

That is, the least significant bit value bit0 of 8-bit parallel data output from the 8-bit register 100 is input to the first sequence error detection code decoder 201, and the next bit value bit1 is the second sequence error. The most significant bit value bit7 of 8-bit parallel data is input to the eighth order error detection code decoder 208 in this manner.

Accordingly, the first to eighth order error detection code decoders 201 to 208 process the input data bit0 to bit7, respectively, as follows.

First, the first sequence error detection code decoder 201 calculates the lowest bit value bit0 of 8-bit parallel data with 16-bit parallel data output from the 16-bit register 300 and outputs the result value.

That is, as shown in FIG. 4, the first sequence error detection code decoder 201 denotes an output of the 16-bit register 300 as D [0] to D [15], and the least significant bit bit0 as DBIT. When you do the following output (Q ').

Q [0] = D [15] + DBIT

Q [1] = D [0]

Q [2] = D [1] + D [15] + DBIT = D [1] + Q [0]

Q [14 ~ 3] = D [13 ~ 2]

Q [15] = D [14] + D [15] + DBIT = D [14] + Q [0]

In order to process 1bit data, a delay of up to two exclusive ogates 201c and 201b occurs, resulting in a delay of about 5-10 ns.

Therefore, since the data processing time of one sequence error detection code decoder is about 5-10ns, 8 sequence error detection code decoders are needed to process 8-bit parallel data. It takes

In this way, the first sequence error detection code decoder 201 processes the least significant bit value bit0 and applies the result value to the second sequence error detection code decoder 2020 as 16-bit data D [15: 0]. Similarly, the second sequence error detection code decoder 202 performs the same operation as the first sequence error detection code decoder 201 to process the second bit bit1, and the processing result value is the third order. The error detection code decoder 203 is input.

Since the first output of the 16-bit register 300 is the output value of the initialization state, all 16 bits are zero.

In this way, when the 8-bit parallel data processing sequentially input to the eighth order error detection code decoder 208 is completed, the result values are input to the 16-bit register 300 and the error discrimination unit 400, respectively.

Accordingly, the 16-bit register 300 temporarily stores the input 16-bit data in synchronization with the clock CLK, outputs the result, feeds it back to the first sequence error detection code decoder 201, and stores the next input data. Process the least significant bit value.

In addition, the error discrimination unit 400 performs logical OR on the input 16-bit data and outputs the result as a data error discrimination value.

5 shows the results of processing input values of the first to eighth order error detection code decoders applied to the present invention.

The CRC function is 16, P (X) = X ¹⁶ + X ¹⁵ + X ² +1, and the reception information m = 11000001.

Here, it can be seen that the result value of processing the input 8-bit parallel data by the first to eighth order error detection code decoders of the present invention is the same as the conventional result value of FIG.

In the present invention, an example of processing 8-bit parallel data is shown, but since the functions of the first to eighth order error detection code decoders can be changed according to the CRC function, all input data can be processed regardless of the input bits.

As described in detail above, the present invention has an effect of improving the processing speed of data since the error detection data input in parallel can be processed in parallel without serial conversion.

In addition, since the hardware due to serial conversion can be reduced, the overall hardware design can be easily effected.

Claims (3)

A first register that temporarily stores N-bit parallel data for error detection in synchronization with an input clock and outputs it simultaneously, a second register that temporarily stores m-bit data for error detection, and parallel from the first register Decoded sequence error detection code consisting of N arithmetic units consisting of M bits that are separated from the lowest to the highest and respectively inputted and outputted to the second register, and the error detection polynomial inputted from the second register is fed back to the second register. Means for detecting an error by calculating m-bit data calculated and outputted from said error detection code decoding means. The error detection code decoder according to claim 1, wherein the error judging means comprises an orifice for ORing all the m-bit data output from the most significant bit arithmetic unit. The method of claim 1, wherein the sequence error detection unit decoding means calculates one bit input from the error detection operation unit in which the least significant bit is input and the m bit value output from the second register, and then inputs the m bit value to the next lower bit. Outputting to the operation unit and performing the same in each operation unit, so that the most significant bit operation unit is configured to calculate the value computed in order after the most significant bit and the input m bit through the previous bits and all the operation units, and output again to the second register. Error detection code decoder.