KR0133490B1 - Poly crystalline silicon fabrication for tft - Google Patents
Poly crystalline silicon fabrication for tftInfo
- Publication number
- KR0133490B1 KR0133490B1 KR1019930028692A KR930028692A KR0133490B1 KR 0133490 B1 KR0133490 B1 KR 0133490B1 KR 1019930028692 A KR1019930028692 A KR 1019930028692A KR 930028692 A KR930028692 A KR 930028692A KR 0133490 B1 KR0133490 B1 KR 0133490B1
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- KR
- South Korea
- Prior art keywords
- polycrystalline silicon
- silicon
- thin film
- heat treatment
- film transistor
- Prior art date
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010409 thin film Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 239000011521 glass Substances 0.000 claims abstract description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 8
- 239000010408 film Substances 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000001459 lithography Methods 0.000 claims description 5
- 230000006911 nucleation Effects 0.000 claims description 3
- 238000010899 nucleation Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 10
- 238000002425 crystallisation Methods 0.000 description 14
- 230000008025 crystallization Effects 0.000 description 12
- 239000007790 solid phase Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 박막 트랜지스터용 다결정 실린콘 제조방법에 관한 것으로서, 종래에 열처리 시간이 길고, 결정립 크기의 균일도가 나쁜 문제점을 해결하기 위하여, 본 발명에서는 유리 기판(1)위에 홈을 형성하는 공정(A)과, 상기 기판(1)위에 열처리에 의해서 다결정 실리콘(3)을 형성하는 공정(B)과, 상기 다결정 실리콘(3)을 소정모양으로 만드는 공정(C)을 제공함으로써, 고성능의 트랜지스터를 제작할 수 있고, 균일한 특성을 가진 작은 크기의 트랜지스터도 쉽게 제작할 수 있다.The present invention relates to a method for manufacturing polycrystalline silicon for a thin film transistor, in order to solve the problem of long heat treatment time and poor uniformity of grain size in the prior art, in the present invention, the step of forming a groove on the glass substrate (A) ), A step (B) of forming polycrystalline silicon (3) by heat treatment on the substrate (1), and a step (C) of making the polycrystalline silicon (3) into a predetermined shape, thereby producing a high-performance transistor. It is possible to manufacture small size transistors with uniform characteristics.
Description
제1도의 일반적인 다결정 실리콘을 활성층으로 이용한 다결정 실리콘 박막 트랜지스터의 단면도.A cross-sectional view of a polycrystalline silicon thin film transistor using the general polycrystalline silicon of FIG. 1 as an active layer.
제2a,b도는 본 발명에 따른 제조공정도.2a, b is a manufacturing process diagram according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 웨이퍼 또는 유리기판 24, 7 : 실리콘 산화막(silicon dioxide)1: silicon wafer or glass substrate 24, 7: silicon dioxide
3 : 다결정 실리콘(polycrystalline silicon 또는 polysilicon)3: polycrystalline silicon or polysilicon
5, 6 : 인(P)이나 비소(As)가 도핑된 n+형 다결정 실리콘 또는 붕소(B)가 도핑된 p+형 다결정 실리콘 8 : 알루미늄(Al)5, 6: n + polycrystalline silicon doped with phosphorus (P) or arsenic (As) or p + polycrystalline silicon doped with boron (B) 8: aluminum (Al)
본 발명은 다결정 실리콘 박막 트랜지스터의 활성층인 다결정 실리콘의 제조방법에 관한 것이다.The present invention relates to a method for producing polycrystalline silicon which is an active layer of a polycrystalline silicon thin film transistor.
구체적으로, 다결정 실리콘 박막의 전기적 특성 및 다결정 실리콘내 결정립(grain)의 균일도를 향상시키기 위한 박막 트랜지스터 다결정 실리콘 제조방법에 관한 것이다.In particular, the present invention relates to a thin film transistor polycrystalline silicon manufacturing method for improving the electrical properties of the polycrystalline silicon thin film and the uniformity of the grain (grain) in the polycrystalline silicon.
일반적으로, 다결정 실리콘 박막 트랜지스터는 고화질의 액정표시기(liquid crystal display, LCD)의 판넥픽셀 스위치 또는 구동회로나, 4메가비트(4Mbit)이상의 고집적, 저소비전력의 SRAM(static random access memory, SRAM)의 풀업(pull-up)소자로 응용되고 있다.In general, a polycrystalline silicon thin film transistor is a panel pixel switch or driving circuit of a high-definition liquid crystal display (LCD), or a pull-up of high density, low power static random access memory (SRAM) of more than 4 megabits (4 Mbits). It is applied as a pull-up device.
이에 따라, 제1도는 일반적인 다결정 실리콘을 활성층으로 이용한 다결정 실리콘 박막 트랜지스터의 단면도를 나타낸 것으로서 그 제조방법을 간략히 설명하면 다음과 같다.Accordingly, FIG. 1 is a cross-sectional view of a polycrystalline silicon thin film transistor using general polycrystalline silicon as an active layer, and a brief description thereof will be given below.
제1도에서 보는 바와 같이 실리콘 웨이퍼 또는 유리기판(1)위에 저압화학기상증착(low pressure chemical chemical vapor deposition, LPCVD)법으로 실리콘 산화막(2)을 증착하고(유리기판인 경우 실리콘 산화막을 생략할 수도 있다)난 후 그 위에 플라즈마 화학기상증착(plasma enhanced vapor deposition, PECVD)법이나 저압화학기상증착법으로 비정질실리콘(amorphous silicon, a-Si)을 증착하여 고상(solid phase) 또는 액상(liquid phase)결정화로 다결정 실리콘(3)(6)을 형성한다.As shown in FIG. 1, the silicon oxide film 2 is deposited on the silicon wafer or the glass substrate 1 by low pressure chemical chemical vapor deposition (LPCVD), and in the case of the glass substrate, the silicon oxide film may be omitted. And then depositing amorphous silicon (a-Si) on the solid phase or liquid phase by plasma enhanced vapor deposition (PECVD) or low pressure chemical vapor deposition. Crystallization forms polycrystalline silicon (3) (6).
그 다음 리소그래피(lithography)와 건식식각으로 트랜지스터의 활성 영역(active area)을 정의하고, 그 후 일반적인 엘에스아이(LSI) 자기정렬(self-aligned) 기술을 이용하여 게이트(gate)실리콘 산화막(4), 게이트 다결정 실리콘(5), 소오스/드레인(source/drain),(6), 격리(isolation)실리콘 산화막(7) 그리고 금속전극(8)을 형성하여 다결정 실리콘 박막 트랜지스터를 완성한다.The active area of the transistor is then defined by lithography and dry etching, and then the gate silicon oxide film 4, using conventional LSI self-aligned techniques, A gate polycrystalline silicon 5, a source / drain, 6, an isolation silicon oxide film 7, and a metal electrode 8 are formed to complete the polycrystalline silicon thin film transistor.
상기 제1도의 박막 트랜지스터에서 트랜지스터의 전기적인 특성을 주로 상기 다결정 실리콘(3)에 의해서 결정된다.In the thin film transistor of FIG. 1, the electrical characteristics of the transistor are mainly determined by the polycrystalline silicon 3.
일반적으로 박막 트랜지스터용 다결정 실리콘은 화학기상증착법으로 600℃이하에서 증착된 비정질 실리콘이나 600℃이상에서 증착한 다결정 실리콘을 실리콘 자기이온-주입(Si+self isonimplantation)으로 비정질 실리콘을 만든 후 전기로 열처리(furnace annealing)에 의한 고상 결정화나 레이저 어닐링(laser annealing)에 의한 액상결정화로 제작되는데, 박막의 균일성과 생산성에서 유리한 고상결정화 방법이 널리 이용되고 있다.In general, a thin film transistor polysilicon is a polycrystalline silicon deposited on the amorphous silicon or above 600 ℃ deposition below 600 ℃ by chemical vapor deposition of silicon self-ion for-heat treatment Electrical after creating the amorphous silicon by implantation (Si + self isonimplantation) It is produced by the solid phase crystallization by (furnace annealing) or liquid crystallization by laser annealing (laser annealing), the solid phase crystallization method which is advantageous in the uniformity and productivity of the thin film is widely used.
현재 사용하고 있는 고정결정화의 열처리방법은 비정질 실리콘을 600℃이하의 온도에서 20시간 이상 장시간동안 열처리하는 방법으로, 이 방법으로 형성된 다결정 실리콘의 결정립은 크나 결정립내의 결함(defect)이 많고 열처리시간이 길어 제조 생산성이 낮은 문제점을 지니고 있다.Currently, the heat treatment method of the fixed crystallization is a method of heat-treating amorphous silicon for a long time more than 20 hours at a temperature of less than 600 ℃, the crystal grains of the polycrystalline silicon formed by this method is large, but there are many defects in the crystal grains and heat treatment time It has a long manufacturing productivity problem is low.
또한 고상결정화로 형성된 다결정 실리콘내의 결정립은 결정핵 생성(nucleation)시기 및 결정립 성장(grain growth)시간이 제작기 달라 결정립 크기의 균일도가 매우 나쁘다.In addition, the crystal grains in the polycrystalline silicon formed by the solid phase crystallization have very poor uniformity of grain size due to different nucleation timing and grain growth time.
이로 인해 박막 트랜지스터의 특성분포가 나쁘며, 아울러 작은 크기의 박막 트랜지스터 제조에 제한이 있게 되는 다른 문제점이 있다.Due to this, there is a bad characteristic distribution of the thin film transistor, and there is another problem that there is a limitation in manufacturing a small size thin film transistor.
이와 같이, 현재 사용되고 있는 평판 기판위의 고상결정화는 균일적(homogenous) 결정화 방법으로 비정질 실리콘내에서 결정핵이 생성되고 성장함으로써 결정화 시간이 길어지며, 이에 따라 결정립 크기가 균일하지 못한다.As such, solid phase crystallization on a flat plate substrate currently used is a homogenous crystallization method, and crystallization time is long due to the formation and growth of crystal nuclei in amorphous silicon, thereby resulting in uneven grain size.
또한 상기 고상결정화를 포함한 상변환(phase transformation)은 일반적으로 외부에서 가해지는 스트레스나 불순물에 의해 균일적 상변환에서 이질적 상변환으로 변화된다.In addition, phase transformation including the solid phase crystallization is generally changed from uniform phase transformation to heterogeneous phase transformation due to external stress or impurities.
따라서, 상기 문제점들을 해결하기 위하여 본 발명에서는 고상결정화시 기판과 박막의 경계부근에서 이질적(heterogeneous)결정화를 유도하여 결정화 열처리 시간을 단축하고, 결정핵 생성위치를 정렬화시켜 균일한 결정립의 다결정 실리콘을 형성하고자 한다.Therefore, in order to solve the above problems, the present invention induces heterogeneous crystallization near the boundary between the substrate and the thin film during the solid phase crystallization to shorten the crystallization heat treatment time, and to align the nucleus formation sites to uniform polycrystalline silicon. To form.
특히, 다결정 실리콘이 형성된 기판을 종래의 평판 대신에 홈이 만들어진 기판을 사용하는 박막 트랜지스터용 다결정 실리콘 제조방법을 제공하는 데 목적이 있다.In particular, it is an object of the present invention to provide a method for manufacturing polycrystalline silicon for thin film transistors using a substrate having polycrystalline silicon formed thereon instead of a conventional flat plate.
상기 목적을 달성하기 위하여 본 발명에서는 첨부된 제2도에 의거하여 그 상세한 설명을 한다.In order to achieve the above object, the present invention will be described in detail based on the attached FIG.
제2도의 (a)∼(c)는 본 발명에 따른 제조공정도를 나타낸다. 먼저, 제2도의 (a)는 박막 트랜지스터의 화성층인 다결정 실리콘 형성시 홈이 만들어져 있는 실리콘 웨이퍼 또는 유리기판(1)을 형성한다.(A)-(c) of FIG. 2 show the manufacturing process chart which concerns on this invention. First, (a) of FIG. 2 forms a silicon wafer or glass substrate 1 in which grooves are formed when polycrystalline silicon, which is a chemical layer of a thin film transistor, is formed.
제2도의 (b)는 상기 기판(1)위에 저압화학기상증착법이나 플라즈마 화학기상증착법으로 비정질 실리콘 박막을 증착한다.In FIG. 2B, an amorphous silicon thin film is deposited on the substrate 1 by low pressure chemical vapor deposition or plasma chemical vapor deposition.
그후 상기 비정질 실리콘 박막을 600℃ 이하의 전기로에서 일반적인 방법으로 열처리하여 고상결정화하거나 또는 급속 열처리(600℃이상)와 전기로 열처리(600℃이하)를 조합하여 결정핵 생성과 결정립 성장의 두 과정으로 분리하여 고상 결정화 시켜 다결정 실리콘(3)을 형성한다.Thereafter, the amorphous silicon thin film is subjected to heat treatment in a general manner in an electric furnace of 600 ° C. or lower, or solidified, or a combination of rapid heat treatment (above 600 ° C.) and electric furnace heat treatment (below 600 ° C.) is used to generate nuclei and grain growth. Separation and solid crystallization to form polycrystalline silicon (3).
그 다음 제2도의 (c)는 상기 형성된 다결정 실리콘(3)을 리소그래피와 건식식각으로 소정부분의 박막 트랜지스터의 활성 영역을 정의하고, 그후 일반적인 실리콘 엘에스아이 자기 정렬 기술을 이용하여 트랜지스터를 완성한다.Next, (c) of FIG. 2 defines the active region of a predetermined portion of the thin film transistor by lithography and dry etching the formed polycrystalline silicon 3, and then completes the transistor using a general silicon LS self-alignment technique.
상기에 대해 구체적인 예를 들면, 제2도의 (a), (b)에서 홈이 높이는 500Å이하, 폭 1㎛이하, 간격 1㎛이상으로 만들어져 있는 실리콘기판 또는 유리기판(1)위에 실리콘 산화막이나 실리콘 질화막(silicon nitride)을 화학기상증착법으로 증착한 후 리소그래피와 건식식각으로 소정형태의 홈(예로서, V홈)을 형성한 후 SiH4나 Si2H6를 이용하여 저압화학기상증착법으로 비정질 실리콘(두께 100Å이상)을 증착한다. 이 공정에서, 초기 V-홈위에 증착된느 실리콘의 구조가 비정질 실리콘이므로 양질의 다결정 실리콘 박막을 얻을 수 있다.For example, the silicon oxide film or the silicon on the silicon substrate or the glass substrate 1, which has a groove height of 500 m or less, a width of 1 m or less, and a thickness of 1 m or more, in (a) and (b) of FIG. After depositing a silicon nitride by chemical vapor deposition, a groove (eg, a V groove) of a predetermined type is formed by lithography and dry etching, and then amorphous silicon is deposited by low pressure chemical vapor deposition using SiH 4 or Si 2 H 6 . (Thickness 100Å or more) is deposited. In this process, since the structure of the silicon deposited on the initial V-groove is amorphous silicon, a high quality polycrystalline silicon thin film can be obtained.
제2도의 (c)에서는 증착된 비정질 실리콘 박막을 600℃이상의 온도에서 급속열처리로 결정핵을 생성한 600℃이하의 전기로 열처리에 의해서 결정립을 성장시켜 소정 모양의 다결정 실리콘(3)을 형성한다. 위와 같이, 본 발명은 600℃이하에서 공정을 수행할 수 있기 때문에 유리기판을 이용한 저온 다결정 실리콘 박막 트랜지스터 제작에 이용될 수 있다.In (c) of FIG. 2, crystal grains are grown by annealing an electric furnace of 600 ° C. or less, in which the deposited amorphous silicon thin film is formed by rapid heat treatment at a temperature of 600 ° C. or higher, thereby forming polycrystalline silicon 3 having a predetermined shape. . As described above, the present invention can be used to fabricate a low temperature polycrystalline silicon thin film transistor using a glass substrate because the process can be performed at 600 ° C. or less.
이상과 같이 본 발명에서 제안된 방법으로 고상결정화 다결정 실리콘을 형성하여 박막 트랜지스터를 제작하면 결정 핵 생성위치를 제어할 수 있기 때문에 고성능의 트랜지스터를 제작할 수 있을 뿐만 아니라 균일한 특성을 가진 작은 크기의 트랜지스터도 쉽게 제작할 수 있을 것으로 기대된다.As described above, if the thin film transistor is manufactured by forming the solid crystallized polycrystalline silicon by the method proposed in the present invention, the position of crystal nucleation can be controlled, and therefore, a high-performance transistor can be manufactured as well as a small transistor having uniform characteristics. It is also expected to be easy to manufacture.
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