KR0129584B1 - Semiconductor memory device - Google Patents

Abstract

A sense-amplifier enable automatic control circuit automatically changes an enable signal of the sense-amplifier(6) to a disable signal when the sense-amplifier(6) starts operating, thereby removing an unnecessary operation and an unnecessary power-consumption. The sense-amplifier enable automatic control circuit includes: a first exclusive-OR logic element(101) for performing a exclusive-OR logic operation about an output signal of the sense-amplifier(6); a latch(103) for latching an output signal of the first exclusive-OR logic element(101); a AND logic element(105) for performing an AND logic operation about both the output signal of the AND logic element(105) and the output signal of the address variation detector(4); a second exclusive-OR logic element(106) for performing a exclusive-OR logic operation about both the output signal of the AND logic element(105) and the output signal of the address variation detector(4), and providing the result signal as an enable signal of the sense-amplifier(6); and MOS transistor which receives an address transition pulse provided from the address variation detector(4), and temporarily changes an output signal of the latch(103) to a low level signal.

Description

Semiconductor Memory Devices for Automatic Control of Sense Amplifiers

1 is a block diagram illustrating a read path of a memory device to which a sense amplifier is applied.

2 is a detailed configuration diagram of the sense amplifier 6 according to the operation of FIG.

3 is an operating waveform diagram according to the configuration of FIG.

4 is a block diagram of a sense amplifier enable automatic control circuit according to the present invention.

5 is an operational waveform diagram according to the configuration of FIG.

* Explanation of symbols for the main parts of the drawings

10: Sense Amplifier Enable Automatic Control Circuit

101, 106: exclusive-OR device (EX0R) 102, 104: MOS transistor

103 latch portion 105 logical AND element

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to semiconductor memory devices for automatically controlling the enable / disable of a sense amplifier.

Referring to the prior art using FIGS. 1 to 3, FIG. 1 is a block diagram of a read path of a memory device to which a sense amplifier is applied, where 1 is an address buffer, 2 is an X, Y predecoder, 3 represents an X and Y decoder, 4 represents a cell array, 5 represents an address change detector (ATD), 6 represents a sense amplifier, 7 represents a latch unit, and 8 represents an output buffer.

When an address is input to the address buffer 1, the input address signal is supplied to the cell array 4 via the X, Y predecoder 2 and the X, Y decoder 3, and the address change detector 5 Detects the change in address from the address buffer 1 and outputs a sense amplifier enable signal. Accordingly, the sense amplifier 6 is operated according to the sense enable signal supplied from the address change detector 5, and senses and amplifies data in the cell array 4 corresponding to the input address so as to latch 7. ) The data latched by the latch unit 7 is read out through the output buffer 8.

FIG. 2 is a detailed configuration diagram of the sense amplifier 6 according to the operation of FIG. 1, and FIG. 3 is an operational waveform diagram according to the configuration of FIG. 2, where IN1 and IN2 are data input signals and SE is a sense enable signal. , Sout represents the output of the sense amplifier 6, and lat-out represents the output of the latch unit 7.

As shown in the figure, the sense amplifier 6 receives the data input signals IN1 and IN2 and the sense enable signal SE which are the control signals, senses and amplifies the data, and outputs the sense amplifier 6 ( Sout is latched by the latch portion 7 and applied to the pull buffer 8.

The driving of the sense amplifier 6 is performed when the sense enable signal SE becomes 'high', where the sense enable signal SE is operated for a long time ta so that the sense amplifier 6 is sufficiently operated. Is approved. Accordingly, since the sense amplifier 6 is operated for a predetermined time ta even after outputting the stable output signal Sout, the sense amplifier 6 has an unnecessary operation, causing power consumption.

Accordingly, an object of the present invention is to provide a semiconductor memory device that brings about low power consumption by preventing unnecessary operation of a sense amplifier. In order to achieve the above object, a semiconductor memory device of the present invention includes a sense amplifier for sensing and amplifying data from a memory cell; An address transition detector for detecting a transition of an address; First exclusive OR means which receives the positive output and the negative output of the sense amplifier and performs an exclusive OR; Latch means for latching an output of the first exclusive OR means in response to an address transition pulse provided inside the address transition detector; Logical AND means for receiving and outputting the output of the latch means and the output from the address transition detector; And second exclusive OR means for receiving the output of the AND product and the output from the address transition detector and performing an exclusive OR to provide an output of the enable signal Rosa to the sense amplifier. Preferably, the first transistor is connected between the input terminal of the latch means and the ground level and receives an output from the first exclusive OR means as a gate; And a second transistor connected between the output terminal of the latch means and a ground level and receiving the address transition pulse as a gate.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. 4 is a configuration diagram of a sense amplifier enable automatic control circuit according to an embodiment of the present invention, Figure 5 is an operational waveform diagram according to the configuration of Figure 4, Figure 10 is a sense amplifier enable according to this embodiment The automatic control circuit, B / B, represents the output of the sense amplifier 6, and a, b, b ', and c represent each operating point of the sense amplifier enable automatic control circuit 10.

As shown in the figure, the sense amplifier enable automatic control circuit 10 according to the present embodiment includes an exclusive OR (element) OR 101 that receives an output of the sense amplifier 6 and performs an exclusive OR operation. An N-type MOS transistor 102 that receives the output of the logic sum element 101 as a gate stage, a latch portion 103 having an input connected to a drain terminal of the MOS transistor 102, and an output terminal of the latch portion 103. The drain is connected, and the gate is an N-type MOS transistor 104 which receives an address transition pulse provided from the address transition detector 4, an output of the latch unit 103, and an output from the address change detector 4. A logical AND element 105 for receiving and OR processing, an output of the AND product 105, and an output of the address transition detector 4 are subjected to exclusive OR processing as an enable signal to the sense amplifier 6. An exclusive OR element 106 is provided.

It looks at the detailed operation of the present invention configured as described above.

When the sense enable signal SE is 'high' and the sense amplifier 6 is enabled, the sense amplifier 6 amplifies the input data signals IN1 and IN2 to output positive outputs having different logic states. (B) and negative output (/ B) are output. The positive output B and the negative output / B are input to the exclusive OR element 101, and the exclusive OR element 101 outputs 'high', which is an exclusive OR processed signal b. The signal (b) is 'low' level by the N-type MOS transistor 102 at a later stage, and is latched in a 'high' state to the latch unit 103 constituted by the inverter, and the output b of the latch unit 103 is ) Is ANDed together with the output a of the address transition detector 4 at the AND product 105 and output in a 'high' state. When the output c of the AND element 105 becomes 'high', the output c of the AND element 105 again becomes the exclusive AND element 106 together with the output a of the address transition detector 4. The exclusive OR is then performed to generate a 'low' level as the sense enable signal SE. As a result, the operation of the sense amplifier 6 is disabled.

As a result, when the sense amplifier 6 is driven by the sense enable signal SE, the sense amplifier 6 is automatically disabled in response to the output of the sense amplifier 6, so that the sense amplifier 6 is disabled for an unnecessary time. The operation state is not maintained.

On the other hand, when the output a of the address transition detector 4 becomes 'low', the output signal c of the logical AND element 105 becomes 'low', and the output signal 'b' of the latch section 103 is 'low'. ') Becomes' low' as the address transition pulse, which is an intermediate processing signal of the address transition detector 4, is applied to the gate of the MOS transistor 104 having a drain connected to the output terminal.

The present invention configured and operated as described above switches the sense amplifier to a disabled state as soon as it is confirmed that the sense amplifier operates, thereby reducing the unnecessary waste of power compared to the prior art.

Claims (2)

A sense amplifier for sensing and amplifying data from the memory cells; An address transition detector for detecting a transition of an address; First exclusive OR means which receives the positive output and the negative output of the sense amplifier and performs an exclusive OR; Latch means for latching an output of said first exclusive OR means in response to an address transition pulse provided within said address transition detector; Logical AND means for receiving and outputting the output of the latch means and the output from the address transition detector; And second exclusive OR means for receiving an output of the AND product and an output from the address transition detector and performing an exclusive OR to provide its output as an enable signal to the sense amplifier. 2. The apparatus of claim 1, further comprising: a first transistor connected between an input terminal of the latch means and a ground level and receiving an output from the first exclusive OR; And a second transistor connected between an output terminal of the latch means and a ground level and receiving the address transition pulse as a gate.