KR0126842B1 - A circuit for petecting signal route errors - Google Patents

Abstract

The present invention provides a signal path error detecting circuit which monitors whether or not a normal operation is performed on its signal path for assuring service continuity by continuously checking errors due to various causes in a digital transmission system's signal processing during service and taking a maintaining/repairing step. This circuit can perform a continuous function monitoring during service and be applied to various digital signal processors with low power consumption. This circuit includes a parallel/serial converting part (202); a comparing part (204); an error latching part (205); an error accumulating part (206); a delay part (203); and a serial latching part (201).

Description

Signal Path Error Detection Circuit

1 is an application diagram for performing error monitoring during mapping of an asynchronous dependent signal,

2 is a configuration diagram of a circuit for continuously performing performance monitoring of a signal according to the present invention during a service;

3 is a signal timing diagram of each part according to the present invention.

* Explanation of symbols for main parts of the drawings

100: signal mapper 200: error monitor

201: serial latch 202: parallel serial converter

203: delay 204: comparator

205: error latch unit 206: error accumulation and threshold difference comparator

The present invention continuously monitors the failure caused by various factors during the process of signal processing during the asynchronous signal or the reverse process during the asynchronous signal through the process of stuffing and inserting the overhead in the digital transmission device, and performs proper maintenance activities. The present invention relates to a signal path error detection circuit that monitors normal operation on its own signal path to ensure continuity of service.

According to the present invention, the existing bit-to-bit error monitoring method of the conventional transmission device is designed to monitor data on the same signal by redundancy of the signal processing unit itself, which requires twice the capacity of the circuit implementation and power consumption. Also, there is a problem in that the consumption is increased due to the duplication of the signal processing unit.

The present invention devised to solve all the problems of the prior art, it is possible to perform continuous device performance monitoring during the service, it is simpler and more efficient than the existing redundant circuit is configured as a low-power technique to a wide range of digital signal processing unit It is an object of the present invention to provide an applicable signal path error detection circuit.

In order to achieve the above object, the present invention includes a parallel / serial conversion means for performing a parallel / serial position conversion of the parallel latched synchronous parallel signal; Comparison means connected to said parallel / serial conversion means for searching for consistency of parallel / serial position conversion; Error latching means for maintaining a state for a time for which a numerical value of an error is set when there is no matching signal in said comparing means; An error accumulating means that receives an error signal generated when there is no coincidence in the comparing means through the error latch means and accumulates the signal as a periodic signal; Delay means connected to said error accumulating means and parallel / serial conversion means for delaying a data delay of a signal processing procedure on a synchronous frame; And a serial latch means for inputting a serial signal and a serial clock, receiving a latch active clock, and providing a signal to be compared to the comparison means.

Since all transmission systems must ensure continuity of service, the performance of the system must be continuously monitored to take action before failure occurs. This invention maps asynchronous signals of PDH dependent signal DSI level (1.544M), CEPT DSI level (2.048M), and DS3 level (44.736M) into synchronous signals (VC11, VC12, VC32) in SDH system in synchronous transmission system. In the signal processing section that performs the function of seam stuffing and overhead processing, de-stamping and its history, when the information signal is mapped to the frame without interference of the signal, that is, inserted into the information bit of the frame as shown in (0) of FIG. This circuit continuously monitors performance.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram illustrating an application of the present invention to a transmission system.

In the figure, 100 represents a signal reminder and 200 represents an error monitor.

As shown in the figure, the dependent signal of a certain bit (8 bits) is stored in the error monitor 200, and the parallel sync signal processed and finally output by the signal mapper 100 is latched to compare the correspondences with each other. . In the error monitor 100, the serial dependent signal a and the parallel signal are compared in units of bytes, and are inserted in the information area on the output frame of the signal reminder 100 through a stuffing process and an overhead process. Due to stuffing and delay in the buffer stage, the parallel synchronization signal can find the delay of the pure information bits during the frame-forming period of the signal on the frame in the time difference region having the maximum and minimum margin.

The MSB (the first bit of the 8 bits) of the signal latched by the serial dependent signal (a) and the MSB of the parallel synchronization signal may have different positions.

To compensate for this, the latch active clock c supplied to the serial latch 201 is parallel latched in the parallel / serial converter 202 in the control signal j through the delay 203. The same data can be compared by supplying the control signal of the clock period) and the serial transition period.

2 is a block diagram of a circuit for continuously performing the performance monitoring of the signal according to the present invention during the service, in the figure 201 is a serial latch, 202 is a parallel serial converter, 203 is a delay, 204 is a comparator, 205 is Error latch section 206 represents an error accumulator and a threshold comparator, respectively.

As shown in the figure, the parallel latched parallel signal d is searched for by the comparator 204 while the parallel / serial position conversion is continuously performed by the parallel / serial converter 202.

If there is no coincidence, an error signal (i) is generated in the comparator 204 and accumulated as a periodic signal in the error accumulator 206, and the accumulated error value k is continuously compared with a threshold value. If the threshold value is exceeded, an alarm 1 is generated.

The above description will be described in more detail as follows.

In the serial latch 201 of FIG. 2, the signal inserted into the signal reminder 200 as a slave serial signal is transferred to the latch active clock 5 of FIG. Stores information bits (8 bits) of the slave signal. The latch active clock is delayed by the data delay of the signal processing process on the synchronous frame through the delay unit 203 of FIG. 2 and used as the parallel latch active clock 6 of FIG.

The function of the serial latch 201 is that the delayed parallel latch active clock 6 of FIG. 2 has a parallel latch in the parallel / serial converter when the parallel latch clock is 1 and the parallel clock (e). The serial conversion is performed by the clock pulse of the < RTI ID = 0.0 >). ≪ / RTI > If there is no coincident signal (i.e., there is an error) between the two signals, the error latch unit 205 generates an error signal k of FIG. 3 as 1 to maintain the state of the error value for a reference time. do. The error state signal enters 206 in FIG. 2 and counts in the counter by the error accumulator clock in FIG. The parallel-to-serial converter of FIG. 2 is simply composed of a 2: 1 selector and 8-flop flip flops.

The error latch unit 205 is cleared only by the error latch active clock even when a coincidence pulse occurs repeatedly several times during the comparison period (Tc).

Therefore, the accumulation of error does not increase even if a successive coincidence pulse occurs before reset. (9) It exists in a continuous state until the pulse of Fig. 3 occurs. The error is increased by the error accumulation clock (72KHz), and the accumulated signal is cleared by the pulse read from the CPU, and the threshold of the error is accumulated in the CPU. When the accumulated error value exceeds the threshold value by writing it to the threshold determination unit, a pulse is transmitted to the CPU to generate an interrupt and is transmitted to the maintenance management circuit. Accumulated error value is continuously compared with the threshold value. If the value exceeds the threshold value, the threshold performance alarm is generated and the error performance value can be read whenever the CPU wants to read it. Initialization is done. After reset, the error counter is operated again and it consists of an algorithm that can accumulate errors.

This higher level logic circuit can be applied in the same algorithm with only the timing of FIG. The reverse process first stores 8 bits of the parallel signal on the frame, and then delays the parallel latch clock by the time delay from which the pure information of the serial signal is disassembled and extracted on the frame. The drive is the same as the above operation.

As described above, the present invention can perform continuous device performance monitoring during a service, and can be applied to a wide range of digital signal processing units as a low power scheme that is simpler and more efficient than conventional redundant circuits.

Claims (2)

An apparatus for performing error monitoring during mapping of an asynchronous dependent signal, comprising: serial / parallel conversion means (202) for continuously performing parallel / serial position conversion of the parallel latched synchronous parallel signal (d); Comparison means (204) connected to the parallel / serial conversion means (202) for searching for correspondence of the parallel / serial position conversion; Error latching means (205) for maintaining a state for a set time of an error value when there is no matching signal in said comparing means (204); An error accumulating means (206) accumulated in a fixed period signal by receiving an error signal (i) generated when there is no coincidence in the comparing means (204) through the error latch means (205); Delay means (203) connected to the error accumulation means and the parallel / serial conversion means (202) for delaying the data delay of the signal processing process on the synchronous frame; And serial latch means (201) for inputting a serial signal and a serial clock and receiving a latch active clock and providing a signal for comparison to the comparing means (204). The method of claim 1; The serial latch means 201 is configured to perform parallel latching and serial conversion in a ring type to serially convert data so that 8 bits can be compared simultaneously starting from the MSB (the first bit of the 8 bits). Signal path error detection circuit.