KR0126126B1 - Video signal generation circuit - Google Patents

Abstract

Disclosed is a video signal generating circuit which reads the contents of a letter generating font memory in a graphic mode. The video signal generating circuit comprises a display memory(11) a CRTC(Cathode Ray Tube Controller)(12), letter generating font memory(17), serial/parallel converter(21), a rapid analyzing logic(22), a counting means(13), a first latch(14), a second latch(15), a first decoding means(18), a multiplexing means(16), a font reading data dividing means(20), and a second decoding means(19). Thus, 8x8 font of BIOS is used in the graphic mode and the letter generating font memory used in a text mode can be commonly used.

Description

Video signal generation circuit

1 is a block diagram of a conventional video generation circuit.

1 is a block diagram of a video signal generation circuit according to the present invention.

* Description of the symbols for the main parts of the drawings *

1,11: Display memory 2,21: CRTC

3,17: Character generation font memory 4,21: Parallel / serial converter

5,22: Attribute analysis logic 13: Counter

14, 15: latch 16: multiplexer

18, 19: decoder 20: font read data classification logic

The present invention relates to a video signal generation circuit which reads the contents of a character generating font memory without difficulty in the graphic mode.

1 is a configuration diagram of a conventional video signal generation circuit, and as shown in the drawing, a display memory 1, a cathode ray tube controller (CRTC) 2, a character generating font memory 3, and a parallel / serial converter 4 ), And attribute analysis logic 5.

The character font is generated by reading the character code from the display memory 1 and acting as an address of the character generating font memory 3 together with the row address of the CRTC 2 to determine the height of the character. Here, the character generation font memory 3 has various fonts embedded therein, which is conventionally used only in the text mode.

Therefore, in the graphic mode in which all images on the screen are mapped to the display memory 1 in a 1: 1 manner, a font composed of 8 × 8 dots of a basic input output system read only memory (BIOS) is used. Accordingly, when used in a display device other than 640 × 200 resolution, for example, when used in a display device having a 640 × 400 resolution, there is a problem in that the shape of the letter deteriorates because it must be double-scanned to make 25 lines. In addition, it is difficult to draw good fonts on the screen in graphics mode because it is limited to make various fonts such as 8 × 14, 8 × 16, 8 × 24, etc. with 8 × 8 fonts. As a result, the burden on the CPU is increased, thereby lowering the overall path through of the CPU.

In order to solve the above problems, an object of the present invention is to provide a video signal generation circuit that uses an 8x8 font of a BIOS in a graphics mode and also shares a character generating font memory used in a test mode.

In order to achieve the above object, the present invention provides a display memory for generating a character code, a CRTC for determining the height of a character, a character generating font memory in which various font data are stored, a serial / serial converter for converting font data serially, and the parallel. A video signal generation circuit configured to include attribute analysis logic for outputting a video signal connected to a serial / serial converter and reading the contents of the character generation font memory without difficulty in a graphics mode, wherein a CPU accesses the character generation font memory. Counting means for reading image data of one character in order, first latch means for determining a code of a character to be read by the CPU, determining a type of a character to be read by the CPU, and accessing the character generation font memory of the CPU. Latch means for latching an address to enable the second latch means; First decoding means for analyzing the address latched by the second latch means to block access to the character generation font memory of the CRTC, the display memory, the CRTC, the counter means, the first and second latch means, and the first A multiplexing means connected to the decoding and character generating font memory to mediate access to the character generating font memory of the CPU and the CRTC by inputting the display memory, the CRTC, the counting means, and the outputs of the first and second latch means and the first decoding means. Font read data classification means connected to the character generating font memory and a parallel / serial converter and separating font data buses and transmitting them to the parallel / serial converter in order to suppress collision of font data accessed by the CPU and the CRTC; A phone connected to the font read data classification means and separated from the font read data classification means And second decoding means for selecting data to be transmitted to the parallel / serial converter.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a block diagram of a video signal generation circuit according to an embodiment of the present invention. As shown in the drawing, the display memory 11, the CRTC 12, the counter 13, the latches 14 and 15, the multiplexer 16, and the character generation are illustrated in FIG. It consists of punt memory 17, decoders 18 and 19, font read data classification logic 20, history / serial converter 21, and attribute analysis logic 22.

The display memory 11 generates a character code, and the CRTC 12 generates a row address for determining a character height.

The counter 13 functions to read image data of one character in order when the character generation font memory 17 of the CPU is accessed.

The latch 14 functions to determine the character code value read from the CPU, and the latch 15 defines a box type of the character to be read from the CPU and the character generation font memory 17 of the CPU. It latches an address to enable access.

The decoder 18 is connected to the latch 15 to analyze the address latched by the latch 15 to prevent access of the character generation font memory 17 of the CRTC and to generate the character generation font memory 17 of the CPU. ) To enable access.

The multiplexer 16 is connected to the display memory 11, the CRTC 12, the counter 13, the latches 14, 15, and the decoder 18 so that the CPU and the CRTC 12 may generate character font memory 17. It mediates access according to the output of the decoder 18.

The decoder 19 functions to select font data separated by the font read data classification logic 20, and the parallel / serial converter 21 outputs fonts to the font read data classification logic 20. It converts the data into a serial and outputs to the attribute analysis logic 22 for outputting as a video signal.

The operation of the video signal generation circuit configured as described above is as follows.

First, the latch 15 determines the font type (8x8, 8x16) among the contents of the character generating font memory 17 by inputting an address and an input / output write signal (I / OW) from the CPU. The CRTC 12 is outputted to the multiplexer 16 so that there is no conflict in access to the character generating font memory 17 of the CPU. The latch 14 receives data from the CPU and input / output write signals (I / O W) as inputs, defines a code value of a character to be read, and outputs the code value to the multiplexer 16. The counter 13 inputs an input / output read signal (I / OR) and an input / output write signal (I / OW) from the CPU, and the CPU inputs and outputs a constant input / output address of the character generating font memory 17. When you want to read through, if you read data consecutively for 1 character, 1 character information is output in order.

The multiplexer 16 includes a character code and a row address output from the display memory 11, a CRTC 12, one character data output from the counter 13, and a character code value output from the latch 14. The font type data output from the latch 15 is input, and the data of the character generating font memory 17 is arbitrated under the control of the decoder 18 generating the character generating font memory access 1 of the CPU. Make it accessible.

The decoder 19 inputs an address from the CPU and selects one of the CPU data bus and the video signal generation route to prevent a collision between the CPU data bus and the video signal generation route at an I / O address where the CPU reads a font. Select and output to the font read data classification logic 20.

The font read data classification logic 20 is connected to the character generation font memory 17, the decoder 19, and the data bus to distinguish the video signal generation route from the font reading of the CPU to the parallel / serial converter 21. Output the data.

In the present invention configured and operated as described above, various fonts on the screen can be definitively displayed using the character generating font memory even in the graphic mode, and the CPU is used to make a font suitable for a display device in the conventional 8 × 8 font. There is no need to reconstruct the font, and there is an application effect of reducing the memory capacity in an adapter that allocates a lot of font information to a memory map.

Claims (1)

A display memory 11 for generating a character code, a CRTC 12 for determining a height of a character, a character generating font memory 17 storing various font data, a serial / serial converter 21 for converting font data serially, And attribute analysis logic 22 which is connected to the parallel / serial converter 21 and outputs a video signal to a video signal generation circuit which reads the contents of the character generating font memory 17 without difficulty in a graphic mode. In; Counting means 13 for reading the image data of one character in order when the CPU accesses the character generating font memory 17, First latch means 14 for determining the code of the character to be read by the CPU, A second latch means 15 for determining a form of a character to be read by the CPU and for latching an address to enable access to the character generating font memory 17 of the CPU, the second latch means 15 being connected to the second latch means 15 A first decoding means 18 for blocking access to the character generating font memory 17 of the CRTC 12 by analyzing the address latched by the second latch means 15, the display memory 17 and the CRTC ( 12, the counter means 13, the first and second latch means 14 and 15, the first decoding means 18, and the character generating font memory 17 connected to the display memory 11 and the CRTC 12. ), The counting means 13, the output of the first and second latch means 14, 15 and the first decoding means 18. Multiplexing means 16 for mediating access to the CPU and the CRTC 12 character generation font memory 17 by inputting to the CPU, the character generation font memory 17 and the parallel / serial converter 21 connected to the CPU; And font read data classification means 20 for separating font data buses and transmitting them to the parallel / serial converter in order to suppress collision of font data accessed by CRTC 12, and font read data classification means 20. And a second decoding means (19) connected to select font data separated by said font read data discrimination means (20) for transmission to said parallel / serial converter (21).