KR0125869B1 - Method of ion implantion for asymmetry self-alignment - Google Patents

Abstract

An ion-implanting method of asymmetrical self align used for FET(Field Effect Transistor) is disclosed. The asymmetrical self-aligned ion implanting method comprises the steps of: forming a gate electrode of W-Al; depositing a germanium on the gate electrode; spin-coating a photoresist layer; removing a photoresist of ion-implanted region among source or drain regions; side etching the germanium layer using the remained photoresist pattern as a mask; removing the remained photoresist pattern; and implanting silicon ions into the resultant structure.

Description

Asymmetric self-aligned ion implantation method

1 is a cross-sectional view showing the self-aligned ion implantation method in the conventional FET fabrication of FIG.

2 is a cross-sectional view showing a step by step asymmetric self-aligned ion implantation method according to the present invention,

3 is a graph showing the relationship between the gate length and the K value,

4 is a graph showing the relationship between the gate length and the drain conductance (g _D ),

5 is a graph showing the relationship between etching time and side etching according to the present invention.

* Description of the symbols for the main parts of the drawings *

1: A12: W-A1

3: SiO ₂ 4: Ge

5: photoresist

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-aligned ion implantation method. In particular, in the manufacture of GaAs metal semiconductor FEFs, asymmetric self-aligned ions for preventing short channel effects occurring when the gate length is 0.5 μm or less It relates to a method of injecting.

A conventional ion implantation method for manufacturing FEF will be described with reference to the drawings of FIG. First, a W-A1 gate 2 is formed (FIG. 1A), and a SiO ₂ film 3 to be used as a mask in ion implantation is deposited by plasma enhanced CVD (PECVD) (FIG. 1B). ), The photoresist 5 is applied (FIG. 1 (C)), the photoresist 5 of the portion that becomes the source and drain regions is removed (FIG. 1 (D)), and the SiO ₂ film is etched. (FIG. 1E), the photoresist is removed (FIG. 1F), and Si is ion implanted using an ion implanter to form an n ⁺ inversion layer (FIG. 1G).

However, when the gate length of the FET implanted by the above method is 0.5 μm or less, the short channel effect phenomenon is remarkable because the source and the drain region n ⁺ conductive layer are very close. As a result, the threshold voltage becomes 300 mV or more, and as shown in FIG. 3, the K value is rather decreased when the gate length is 0.5 mu m. In addition, as shown in FIG. 4, when the gate length is 0.5 mu m, the drain conductance gD becomes high at 45 mS / mm.

Accordingly, an object of the present invention is to provide an asymmetric ion implantation method for preventing a short channel effect phenomenon in manufacturing an EFT.

In order to achieve the above object, the present invention provides a method of forming a W-A1 gate electrode, depositing Ge, applying a photoresist, and applying a region to an ion implantation process. And removing the resist, side etching the Ge in the region, removing the rest of the photoresist, and implanting Si into the region. have.

In the present invention, in the FET fabrication, Ge is used instead of SiO ₂ as a mask for ion implantation, so that the side-etching length can be accurately adjusted to within several μm by controlling the etching time. have. This is because when SiO ₂ is used, it is difficult to adjust the accurate etching rate under the influence of oxygen, but when Ge is used, the etching rate can be adjusted accurately.

In addition, since the present invention uses SF ₆ gas for the etching of Ge, it is possible to etch only Ge without affecting the W-A1 and GaAs substrates, so even if the etching time is inadvertently exceeded, there is no problem. It doesn't work.

Specific embodiments of the present invention will be described in detail below with reference to FIG. However, the present invention is not limited thereto.

First, the W-A1 gate 2 is formed by a conventional method (FIG. 2A), and then Ge (4) is formed on the entire surface with a thickness of about 400 GPa (FIG. 2B). ). The photoresist 5 is applied thereon to a thickness of about 1 μm (FIG. 2C), and the photoresist of the Si implanted region to be the source or drain region is removed by photolithography using an aligner. (Figure 2 (D)). Next, Ge (4) was used using Reactive Ion Eching (RIE) under the condition that the used gas was SF ₆ , the flow rate was 1000SCCM, the pressure was 150mTorr, the RF power was 0.16W / cm ^2, and the etching rate was 2000 mW / m. ) Is side etched (FIG. 2E). After removing the photoresist 5 (FIG. 2F), Si ions are asymmetrically implanted using an ion implanter (FIG. 2G).

In the FET manufactured by the above-described method, since only one region of the source or drain region is ion implanted, a short channel effect in which the n ⁺ conductive layer on the source and drain side is generated in close proximity even when the gate length is 0.5 μm. The phenomenon can be prevented. By preventing the short channel effect, the FET characteristic can be lowered to 20 mV or less.

An excellent effect of the present invention due to the short channel effect phenomenon will be described below with reference to FIGS. 3 and 4.

3 is a graph showing a comparison between the present invention and the prior art, showing the relationship between the gate value and the value of the transistor, the K value. As can be seen in FIG. 3, when the gate length is 0.5 μm, the K value decreases in the FET according to the prior art, while the FET according to the present invention does not exhibit such a reduction phenomenon and is about 220 ms / V · mm. It can be seen that the K value is large.

4 is a graph showing the relationship between the drain conductance g _D versus the gate length in comparison with the present invention. As shown in FIG. 4, when the gate length is 0.5 μm, the drain conductance g _D rapidly increases to 45 ms / mm due to the short channel effect in the FET according to the prior art, whereas according to the present invention, Since it is about 15ms / mm, it shows much better characteristics.

In the embodiment of the present invention, a graph showing the length of the side etching according to the etching time is shown in FIG. In the present invention, since Ge is used as a mask during ion implantation, the length of the side etching can be achieved in proportion to the etching time. As can be seen from FIG. 5, it can be seen that in this embodiment, the etching rate is accurately achieved at 2000 mA / min. In addition, since the SF ₆ gas is used for side etching, the W-A1 substrate is not etched and thus, even if the etching time is accidentally exceeded, it is safe.

As described above, the present invention is effective in preventing short channel effects caused by short gate lengths. As a result, the threshold hold voltage can be lowered to 20 mV or less, the K value can be obtained up to 220 ms / V · mm without being reduced, and the drain conductance (g _D ) value is good. In addition, since Ge is used as a mask used for ion implantation, the etching rate can be accurately controlled.

Claims (1)

Forming a W-A1 gate electrode, depositing Ge, applying a photoresist, removing the photoresist in a region to be ion implanted by a photo process, and in the region, the Ge Side etching, removing the remainder of the photoresist, and implanting Si into the region.

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